1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip
4 *
5 * Copyright (C) 2021 Cirrus Logic, Inc. and
6 * Cirrus Logic International Semiconductor Ltd.
7 */
8
9 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <sound/core.h>
13 #include <linux/mutex.h>
14 #include <linux/iopoll.h>
15
16 #include "patch_cs8409.h"
17
18 /******************************************************************************
19 * CS8409 Specific Functions
20 ******************************************************************************/
21
cs8409_parse_auto_config(struct hda_codec * codec)22 static int cs8409_parse_auto_config(struct hda_codec *codec)
23 {
24 struct cs8409_spec *spec = codec->spec;
25 int err;
26 int i;
27
28 err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0);
29 if (err < 0)
30 return err;
31
32 err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg);
33 if (err < 0)
34 return err;
35
36 /* keep the ADCs powered up when it's dynamically switchable */
37 if (spec->gen.dyn_adc_switch) {
38 unsigned int done = 0;
39
40 for (i = 0; i < spec->gen.input_mux.num_items; i++) {
41 int idx = spec->gen.dyn_adc_idx[i];
42
43 if (done & (1 << idx))
44 continue;
45 snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]);
46 done |= 1 << idx;
47 }
48 }
49
50 return 0;
51 }
52
53 static void cs8409_disable_i2c_clock_worker(struct work_struct *work);
54
cs8409_alloc_spec(struct hda_codec * codec)55 static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec)
56 {
57 struct cs8409_spec *spec;
58
59 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
60 if (!spec)
61 return NULL;
62 codec->spec = spec;
63 spec->codec = codec;
64 codec->power_save_node = 1;
65 mutex_init(&spec->i2c_mux);
66 INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker);
67 snd_hda_gen_spec_init(&spec->gen);
68
69 return spec;
70 }
71
cs8409_vendor_coef_get(struct hda_codec * codec,unsigned int idx)72 static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx)
73 {
74 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
75 return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0);
76 }
77
cs8409_vendor_coef_set(struct hda_codec * codec,unsigned int idx,unsigned int coef)78 static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx,
79 unsigned int coef)
80 {
81 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx);
82 snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef);
83 }
84
85 /*
86 * cs8409_enable_i2c_clock - Disable I2C clocks
87 * @codec: the codec instance
88 * Disable I2C clocks.
89 * This must be called when the i2c mutex is unlocked.
90 */
cs8409_disable_i2c_clock(struct hda_codec * codec)91 static void cs8409_disable_i2c_clock(struct hda_codec *codec)
92 {
93 struct cs8409_spec *spec = codec->spec;
94
95 mutex_lock(&spec->i2c_mux);
96 if (spec->i2c_clck_enabled) {
97 cs8409_vendor_coef_set(spec->codec, 0x0,
98 cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7);
99 spec->i2c_clck_enabled = 0;
100 }
101 mutex_unlock(&spec->i2c_mux);
102 }
103
104 /*
105 * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use
106 */
cs8409_disable_i2c_clock_worker(struct work_struct * work)107 static void cs8409_disable_i2c_clock_worker(struct work_struct *work)
108 {
109 struct cs8409_spec *spec = container_of(work, struct cs8409_spec, i2c_clk_work.work);
110
111 cs8409_disable_i2c_clock(spec->codec);
112 }
113
114 /*
115 * cs8409_enable_i2c_clock - Enable I2C clocks
116 * @codec: the codec instance
117 * Enable I2C clocks.
118 * This must be called when the i2c mutex is locked.
119 */
cs8409_enable_i2c_clock(struct hda_codec * codec)120 static void cs8409_enable_i2c_clock(struct hda_codec *codec)
121 {
122 struct cs8409_spec *spec = codec->spec;
123
124 /* Cancel the disable timer, but do not wait for any running disable functions to finish.
125 * If the disable timer runs out before cancel, the delayed work thread will be blocked,
126 * waiting for the mutex to become unlocked. This mutex will be locked for the duration of
127 * any i2c transaction, so the disable function will run to completion immediately
128 * afterwards in the scenario. The next enable call will re-enable the clock, regardless.
129 */
130 cancel_delayed_work(&spec->i2c_clk_work);
131
132 if (!spec->i2c_clck_enabled) {
133 cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8);
134 spec->i2c_clck_enabled = 1;
135 }
136 queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25));
137 }
138
139 /**
140 * cs8409_i2c_wait_complete - Wait for I2C transaction
141 * @codec: the codec instance
142 *
143 * Wait for I2C transaction to complete.
144 * Return -ETIMEDOUT if transaction wait times out.
145 */
cs8409_i2c_wait_complete(struct hda_codec * codec)146 static int cs8409_i2c_wait_complete(struct hda_codec *codec)
147 {
148 unsigned int retval;
149
150 return read_poll_timeout(cs8409_vendor_coef_get, retval, retval & 0x18,
151 CS42L42_I2C_SLEEP_US, CS42L42_I2C_TIMEOUT_US, false, codec, CS8409_I2C_STS);
152 }
153
154 /**
155 * cs8409_set_i2c_dev_addr - Set i2c address for transaction
156 * @codec: the codec instance
157 * @addr: I2C Address
158 */
cs8409_set_i2c_dev_addr(struct hda_codec * codec,unsigned int addr)159 static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr)
160 {
161 struct cs8409_spec *spec = codec->spec;
162
163 if (spec->dev_addr != addr) {
164 cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr);
165 spec->dev_addr = addr;
166 }
167 }
168
169 /**
170 * cs8409_i2c_set_page - CS8409 I2C set page register.
171 * @scodec: the codec instance
172 * @i2c_reg: Page register
173 *
174 * Returns negative on error.
175 */
cs8409_i2c_set_page(struct sub_codec * scodec,unsigned int i2c_reg)176 static int cs8409_i2c_set_page(struct sub_codec *scodec, unsigned int i2c_reg)
177 {
178 struct hda_codec *codec = scodec->codec;
179
180 if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) {
181 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8);
182 if (cs8409_i2c_wait_complete(codec) < 0)
183 return -EIO;
184 scodec->last_page = i2c_reg >> 8;
185 }
186
187 return 0;
188 }
189
190 /**
191 * cs8409_i2c_read - CS8409 I2C Read.
192 * @scodec: the codec instance
193 * @addr: Register to read
194 *
195 * Returns negative on error, otherwise returns read value in bits 0-7.
196 */
cs8409_i2c_read(struct sub_codec * scodec,unsigned int addr)197 static int cs8409_i2c_read(struct sub_codec *scodec, unsigned int addr)
198 {
199 struct hda_codec *codec = scodec->codec;
200 struct cs8409_spec *spec = codec->spec;
201 unsigned int i2c_reg_data;
202 unsigned int read_data;
203
204 if (scodec->suspended)
205 return -EPERM;
206
207 mutex_lock(&spec->i2c_mux);
208 cs8409_enable_i2c_clock(codec);
209 cs8409_set_i2c_dev_addr(codec, scodec->addr);
210
211 if (cs8409_i2c_set_page(scodec, addr))
212 goto error;
213
214 i2c_reg_data = (addr << 8) & 0x0ffff;
215 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
216 if (cs8409_i2c_wait_complete(codec) < 0)
217 goto error;
218
219 /* Register in bits 15-8 and the data in 7-0 */
220 read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD);
221
222 mutex_unlock(&spec->i2c_mux);
223
224 return read_data & 0x0ff;
225
226 error:
227 mutex_unlock(&spec->i2c_mux);
228 codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
229 return -EIO;
230 }
231
232 /**
233 * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence.
234 * @scodec: the codec instance
235 * @seq: Register Sequence to read
236 * @count: Number of registeres to read
237 *
238 * Returns negative on error, values are read into value element of cs8409_i2c_param sequence.
239 */
cs8409_i2c_bulk_read(struct sub_codec * scodec,struct cs8409_i2c_param * seq,int count)240 static int cs8409_i2c_bulk_read(struct sub_codec *scodec, struct cs8409_i2c_param *seq, int count)
241 {
242 struct hda_codec *codec = scodec->codec;
243 struct cs8409_spec *spec = codec->spec;
244 unsigned int i2c_reg_data;
245 int i;
246
247 if (scodec->suspended)
248 return -EPERM;
249
250 mutex_lock(&spec->i2c_mux);
251 cs8409_set_i2c_dev_addr(codec, scodec->addr);
252
253 for (i = 0; i < count; i++) {
254 cs8409_enable_i2c_clock(codec);
255 if (cs8409_i2c_set_page(scodec, seq[i].addr))
256 goto error;
257
258 i2c_reg_data = (seq[i].addr << 8) & 0x0ffff;
259 cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data);
260
261 if (cs8409_i2c_wait_complete(codec) < 0)
262 goto error;
263
264 seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff;
265 }
266
267 mutex_unlock(&spec->i2c_mux);
268
269 return 0;
270
271 error:
272 mutex_unlock(&spec->i2c_mux);
273 codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
274 return -EIO;
275 }
276
277 /**
278 * cs8409_i2c_write - CS8409 I2C Write.
279 * @scodec: the codec instance
280 * @addr: Register to write to
281 * @value: Data to write
282 *
283 * Returns negative on error, otherwise returns 0.
284 */
cs8409_i2c_write(struct sub_codec * scodec,unsigned int addr,unsigned int value)285 static int cs8409_i2c_write(struct sub_codec *scodec, unsigned int addr, unsigned int value)
286 {
287 struct hda_codec *codec = scodec->codec;
288 struct cs8409_spec *spec = codec->spec;
289 unsigned int i2c_reg_data;
290
291 if (scodec->suspended)
292 return -EPERM;
293
294 mutex_lock(&spec->i2c_mux);
295
296 cs8409_enable_i2c_clock(codec);
297 cs8409_set_i2c_dev_addr(codec, scodec->addr);
298
299 if (cs8409_i2c_set_page(scodec, addr))
300 goto error;
301
302 i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff);
303 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
304
305 if (cs8409_i2c_wait_complete(codec) < 0)
306 goto error;
307
308 mutex_unlock(&spec->i2c_mux);
309 return 0;
310
311 error:
312 mutex_unlock(&spec->i2c_mux);
313 codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr);
314 return -EIO;
315 }
316
317 /**
318 * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence.
319 * @scodec: the codec instance
320 * @seq: Register Sequence to write
321 * @count: Number of registeres to write
322 *
323 * Returns negative on error.
324 */
cs8409_i2c_bulk_write(struct sub_codec * scodec,const struct cs8409_i2c_param * seq,int count)325 static int cs8409_i2c_bulk_write(struct sub_codec *scodec, const struct cs8409_i2c_param *seq,
326 int count)
327 {
328 struct hda_codec *codec = scodec->codec;
329 struct cs8409_spec *spec = codec->spec;
330 unsigned int i2c_reg_data;
331 int i;
332
333 if (scodec->suspended)
334 return -EPERM;
335
336 mutex_lock(&spec->i2c_mux);
337 cs8409_set_i2c_dev_addr(codec, scodec->addr);
338
339 for (i = 0; i < count; i++) {
340 cs8409_enable_i2c_clock(codec);
341 if (cs8409_i2c_set_page(scodec, seq[i].addr))
342 goto error;
343
344 i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff);
345 cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data);
346
347 if (cs8409_i2c_wait_complete(codec) < 0)
348 goto error;
349 }
350
351 mutex_unlock(&spec->i2c_mux);
352
353 return 0;
354
355 error:
356 mutex_unlock(&spec->i2c_mux);
357 codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr);
358 return -EIO;
359 }
360
cs8409_init(struct hda_codec * codec)361 static int cs8409_init(struct hda_codec *codec)
362 {
363 int ret = snd_hda_gen_init(codec);
364
365 if (!ret)
366 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT);
367
368 return ret;
369 }
370
cs8409_build_controls(struct hda_codec * codec)371 static int cs8409_build_controls(struct hda_codec *codec)
372 {
373 int err;
374
375 err = snd_hda_gen_build_controls(codec);
376 if (err < 0)
377 return err;
378 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD);
379
380 return 0;
381 }
382
383 /* Enable/Disable Unsolicited Response */
cs8409_enable_ur(struct hda_codec * codec,int flag)384 static void cs8409_enable_ur(struct hda_codec *codec, int flag)
385 {
386 struct cs8409_spec *spec = codec->spec;
387 unsigned int ur_gpios = 0;
388 int i;
389
390 for (i = 0; i < spec->num_scodecs; i++)
391 ur_gpios |= spec->scodecs[i]->irq_mask;
392
393 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK,
394 flag ? ur_gpios : 0);
395
396 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE,
397 flag ? AC_UNSOL_ENABLED : 0);
398 }
399
cs8409_fix_caps(struct hda_codec * codec,unsigned int nid)400 static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid)
401 {
402 int caps;
403
404 /* CS8409 is simple HDA bridge and intended to be used with a remote
405 * companion codec. Most of input/output PIN(s) have only basic
406 * capabilities. Receive and Transmit NID(s) have only OUTC and INC
407 * capabilities and no presence detect capable (PDC) and call to
408 * snd_hda_gen_build_controls() will mark them as non detectable
409 * phantom jacks. However, a companion codec may be
410 * connected to these pins which supports jack detect
411 * capabilities. We have to override pin capabilities,
412 * otherwise they will not be created as input devices.
413 */
414 caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP);
415 if (caps >= 0)
416 snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP,
417 (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT)));
418
419 snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP));
420 }
421
422 /******************************************************************************
423 * CS42L42 Specific Functions
424 ******************************************************************************/
425
cs42l42_volume_info(struct snd_kcontrol * kctrl,struct snd_ctl_elem_info * uinfo)426 int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo)
427 {
428 unsigned int ofs = get_amp_offset(kctrl);
429 u8 chs = get_amp_channels(kctrl);
430
431 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
432 uinfo->value.integer.step = 1;
433 uinfo->count = chs == 3 ? 2 : 1;
434
435 switch (ofs) {
436 case CS42L42_VOL_DAC:
437 uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN;
438 uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX;
439 break;
440 case CS42L42_VOL_ADC:
441 uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN;
442 uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX;
443 break;
444 default:
445 break;
446 }
447
448 return 0;
449 }
450
cs42l42_volume_get(struct snd_kcontrol * kctrl,struct snd_ctl_elem_value * uctrl)451 int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
452 {
453 struct hda_codec *codec = snd_kcontrol_chip(kctrl);
454 struct cs8409_spec *spec = codec->spec;
455 struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
456 int chs = get_amp_channels(kctrl);
457 unsigned int ofs = get_amp_offset(kctrl);
458 long *valp = uctrl->value.integer.value;
459
460 switch (ofs) {
461 case CS42L42_VOL_DAC:
462 if (chs & BIT(0))
463 *valp++ = cs42l42->vol[ofs];
464 if (chs & BIT(1))
465 *valp = cs42l42->vol[ofs+1];
466 break;
467 case CS42L42_VOL_ADC:
468 if (chs & BIT(0))
469 *valp = cs42l42->vol[ofs];
470 break;
471 default:
472 break;
473 }
474
475 return 0;
476 }
477
cs42l42_mute(struct sub_codec * cs42l42,int vol_type,unsigned int chs,bool mute)478 static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type,
479 unsigned int chs, bool mute)
480 {
481 if (mute) {
482 if (vol_type == CS42L42_VOL_DAC) {
483 if (chs & BIT(0))
484 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHA, 0x3f);
485 if (chs & BIT(1))
486 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHB, 0x3f);
487 } else if (vol_type == CS42L42_VOL_ADC) {
488 if (chs & BIT(0))
489 cs8409_i2c_write(cs42l42, CS42L42_REG_AMIC_VOL, 0x9f);
490 }
491 } else {
492 if (vol_type == CS42L42_VOL_DAC) {
493 if (chs & BIT(0))
494 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHA,
495 -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET])
496 & CS42L42_REG_HS_VOL_MASK);
497 if (chs & BIT(1))
498 cs8409_i2c_write(cs42l42, CS42L42_REG_HS_VOL_CHB,
499 -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET])
500 & CS42L42_REG_HS_VOL_MASK);
501 } else if (vol_type == CS42L42_VOL_ADC) {
502 if (chs & BIT(0))
503 cs8409_i2c_write(cs42l42, CS42L42_REG_AMIC_VOL,
504 cs42l42->vol[CS42L42_ADC_VOL_OFFSET]
505 & CS42L42_REG_AMIC_VOL_MASK);
506 }
507 }
508 }
509
cs42l42_volume_put(struct snd_kcontrol * kctrl,struct snd_ctl_elem_value * uctrl)510 int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl)
511 {
512 struct hda_codec *codec = snd_kcontrol_chip(kctrl);
513 struct cs8409_spec *spec = codec->spec;
514 struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)];
515 int chs = get_amp_channels(kctrl);
516 unsigned int ofs = get_amp_offset(kctrl);
517 long *valp = uctrl->value.integer.value;
518
519 switch (ofs) {
520 case CS42L42_VOL_DAC:
521 if (chs & BIT(0))
522 cs42l42->vol[ofs] = *valp;
523 if (chs & BIT(1)) {
524 valp++;
525 cs42l42->vol[ofs + 1] = *valp;
526 }
527 if (spec->playback_started)
528 cs42l42_mute(cs42l42, CS42L42_VOL_DAC, chs, false);
529 break;
530 case CS42L42_VOL_ADC:
531 if (chs & BIT(0))
532 cs42l42->vol[ofs] = *valp;
533 if (spec->capture_started)
534 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, chs, false);
535 break;
536 default:
537 break;
538 }
539
540 return 0;
541 }
542
cs42l42_playback_pcm_hook(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream,int action)543 static void cs42l42_playback_pcm_hook(struct hda_pcm_stream *hinfo,
544 struct hda_codec *codec,
545 struct snd_pcm_substream *substream,
546 int action)
547 {
548 struct cs8409_spec *spec = codec->spec;
549 struct sub_codec *cs42l42;
550 int i;
551 bool mute;
552
553 switch (action) {
554 case HDA_GEN_PCM_ACT_PREPARE:
555 mute = false;
556 spec->playback_started = 1;
557 break;
558 case HDA_GEN_PCM_ACT_CLEANUP:
559 mute = true;
560 spec->playback_started = 0;
561 break;
562 default:
563 return;
564 }
565
566 for (i = 0; i < spec->num_scodecs; i++) {
567 cs42l42 = spec->scodecs[i];
568 cs42l42_mute(cs42l42, CS42L42_VOL_DAC, 0x3, mute);
569 }
570 }
571
cs42l42_capture_pcm_hook(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream,int action)572 static void cs42l42_capture_pcm_hook(struct hda_pcm_stream *hinfo,
573 struct hda_codec *codec,
574 struct snd_pcm_substream *substream,
575 int action)
576 {
577 struct cs8409_spec *spec = codec->spec;
578 struct sub_codec *cs42l42;
579 int i;
580 bool mute;
581
582 switch (action) {
583 case HDA_GEN_PCM_ACT_PREPARE:
584 mute = false;
585 spec->capture_started = 1;
586 break;
587 case HDA_GEN_PCM_ACT_CLEANUP:
588 mute = true;
589 spec->capture_started = 0;
590 break;
591 default:
592 return;
593 }
594
595 for (i = 0; i < spec->num_scodecs; i++) {
596 cs42l42 = spec->scodecs[i];
597 cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute);
598 }
599 }
600
601 /* Configure CS42L42 slave codec for jack autodetect */
cs42l42_enable_jack_detect(struct sub_codec * cs42l42)602 static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42)
603 {
604 cs8409_i2c_write(cs42l42, 0x1b70, cs42l42->hsbias_hiz);
605 /* Clear WAKE# */
606 cs8409_i2c_write(cs42l42, 0x1b71, 0x00C1);
607 /* Wait ~2.5ms */
608 usleep_range(2500, 3000);
609 /* Set mode WAKE# output follows the combination logic directly */
610 cs8409_i2c_write(cs42l42, 0x1b71, 0x00C0);
611 /* Clear interrupts status */
612 cs8409_i2c_read(cs42l42, 0x130f);
613 /* Enable interrupt */
614 cs8409_i2c_write(cs42l42, 0x1320, 0xF3);
615 }
616
617 /* Enable and run CS42L42 slave codec jack auto detect */
cs42l42_run_jack_detect(struct sub_codec * cs42l42)618 static void cs42l42_run_jack_detect(struct sub_codec *cs42l42)
619 {
620 /* Clear interrupts */
621 cs8409_i2c_read(cs42l42, 0x1308);
622 cs8409_i2c_read(cs42l42, 0x1b77);
623 cs8409_i2c_write(cs42l42, 0x1320, 0xFF);
624 cs8409_i2c_read(cs42l42, 0x130f);
625
626 cs8409_i2c_write(cs42l42, 0x1102, 0x87);
627 cs8409_i2c_write(cs42l42, 0x1f06, 0x86);
628 cs8409_i2c_write(cs42l42, 0x1b74, 0x07);
629 cs8409_i2c_write(cs42l42, 0x131b, 0xFD);
630 cs8409_i2c_write(cs42l42, 0x1120, 0x80);
631 /* Wait ~100us*/
632 usleep_range(100, 200);
633 cs8409_i2c_write(cs42l42, 0x111f, 0x77);
634 cs8409_i2c_write(cs42l42, 0x1120, 0xc0);
635 }
636
cs42l42_handle_tip_sense(struct sub_codec * cs42l42,unsigned int reg_ts_status)637 static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status)
638 {
639 int status_changed = 0;
640
641 /* TIP_SENSE INSERT/REMOVE */
642 switch (reg_ts_status) {
643 case CS42L42_JACK_INSERTED:
644 if (!cs42l42->hp_jack_in) {
645 if (cs42l42->no_type_dect) {
646 status_changed = 1;
647 cs42l42->hp_jack_in = 1;
648 cs42l42->mic_jack_in = 0;
649 } else {
650 cs42l42_run_jack_detect(cs42l42);
651 }
652 }
653 break;
654
655 case CS42L42_JACK_REMOVED:
656 if (cs42l42->hp_jack_in || cs42l42->mic_jack_in) {
657 status_changed = 1;
658 cs42l42->hp_jack_in = 0;
659 cs42l42->mic_jack_in = 0;
660 }
661 break;
662 default:
663 /* jack in transition */
664 break;
665 }
666
667 return status_changed;
668 }
669
cs42l42_jack_unsol_event(struct sub_codec * cs42l42)670 static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42)
671 {
672 int status_changed = 0;
673 int reg_cdc_status;
674 int reg_hs_status;
675 int reg_ts_status;
676 int type;
677
678 /* Read jack detect status registers */
679 reg_cdc_status = cs8409_i2c_read(cs42l42, 0x1308);
680 reg_hs_status = cs8409_i2c_read(cs42l42, 0x1124);
681 reg_ts_status = cs8409_i2c_read(cs42l42, 0x130f);
682
683 /* If status values are < 0, read error has occurred. */
684 if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0)
685 return -EIO;
686
687 /* HSDET_AUTO_DONE */
688 if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE) {
689
690 /* Disable HSDET_AUTO_DONE */
691 cs8409_i2c_write(cs42l42, 0x131b, 0xFF);
692
693 type = ((reg_hs_status & CS42L42_HSTYPE_MASK) + 1);
694
695 if (cs42l42->no_type_dect) {
696 status_changed = cs42l42_handle_tip_sense(cs42l42, reg_ts_status);
697 } else if (type == 4) {
698 /* Type 4 not supported */
699 status_changed = cs42l42_handle_tip_sense(cs42l42, CS42L42_JACK_REMOVED);
700 } else {
701 if (!cs42l42->hp_jack_in) {
702 status_changed = 1;
703 cs42l42->hp_jack_in = 1;
704 }
705 /* type = 3 has no mic */
706 if ((!cs42l42->mic_jack_in) && (type != 3)) {
707 status_changed = 1;
708 cs42l42->mic_jack_in = 1;
709 }
710 }
711 /* Configure the HSDET mode. */
712 cs8409_i2c_write(cs42l42, 0x1120, 0x80);
713 /* Enable the HPOUT ground clamp and configure the HP pull-down */
714 cs8409_i2c_write(cs42l42, 0x1F06, 0x02);
715 /* Re-Enable Tip Sense Interrupt */
716 cs8409_i2c_write(cs42l42, 0x1320, 0xF3);
717 } else {
718 status_changed = cs42l42_handle_tip_sense(cs42l42, reg_ts_status);
719 }
720
721 return status_changed;
722 }
723
cs42l42_resume(struct sub_codec * cs42l42)724 static void cs42l42_resume(struct sub_codec *cs42l42)
725 {
726 struct hda_codec *codec = cs42l42->codec;
727 unsigned int gpio_data;
728 struct cs8409_i2c_param irq_regs[] = {
729 { 0x1308, 0x00 },
730 { 0x1309, 0x00 },
731 { 0x130A, 0x00 },
732 { 0x130F, 0x00 },
733 };
734
735 /* Bring CS42L42 out of Reset */
736 gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
737 gpio_data |= cs42l42->reset_gpio;
738 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, gpio_data);
739 usleep_range(10000, 15000);
740
741 cs42l42->suspended = 0;
742
743 /* Initialize CS42L42 companion codec */
744 cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num);
745 usleep_range(20000, 25000);
746
747 /* Clear interrupts, by reading interrupt status registers */
748 cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs));
749
750 if (cs42l42->full_scale_vol)
751 cs8409_i2c_write(cs42l42, 0x2001, 0x01);
752
753 cs42l42_enable_jack_detect(cs42l42);
754 }
755
756 #ifdef CONFIG_PM
cs42l42_suspend(struct sub_codec * cs42l42)757 static void cs42l42_suspend(struct sub_codec *cs42l42)
758 {
759 struct hda_codec *codec = cs42l42->codec;
760 unsigned int gpio_data;
761 int reg_cdc_status = 0;
762 const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = {
763 { 0x1F06, 0x02 },
764 { 0x1129, 0x00 },
765 { 0x2301, 0x3F },
766 { 0x2302, 0x3F },
767 { 0x2303, 0x3F },
768 { 0x2001, 0x0F },
769 { 0x2A01, 0x00 },
770 { 0x1207, 0x00 },
771 { 0x1101, 0xFE },
772 { 0x1102, 0x8C },
773 { 0x1101, 0xFF },
774 };
775
776 cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq));
777
778 if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status,
779 (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US,
780 true, cs42l42, 0x1308) < 0)
781 codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n");
782
783 /* Power down CS42L42 ASP/EQ/MIX/HP */
784 cs8409_i2c_write(cs42l42, 0x1102, 0x9C);
785 cs42l42->suspended = 1;
786 cs42l42->last_page = 0;
787 cs42l42->hp_jack_in = 0;
788 cs42l42->mic_jack_in = 0;
789
790 /* Put CS42L42 into Reset */
791 gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0);
792 gpio_data &= ~cs42l42->reset_gpio;
793 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, gpio_data);
794 }
795 #endif
796
cs8409_free(struct hda_codec * codec)797 static void cs8409_free(struct hda_codec *codec)
798 {
799 struct cs8409_spec *spec = codec->spec;
800
801 /* Cancel i2c clock disable timer, and disable clock if left enabled */
802 cancel_delayed_work_sync(&spec->i2c_clk_work);
803 cs8409_disable_i2c_clock(codec);
804
805 snd_hda_gen_free(codec);
806 }
807
808 /******************************************************************************
809 * BULLSEYE / WARLOCK / CYBORG Specific Functions
810 * CS8409/CS42L42
811 ******************************************************************************/
812
813 /*
814 * In the case of CS8409 we do not have unsolicited events from NID's 0x24
815 * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will
816 * generate interrupt via gpio 4 to notify jack events. We have to overwrite
817 * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
818 * and then notify status via generic snd_hda_jack_unsol_event() call.
819 */
cs8409_cs42l42_jack_unsol_event(struct hda_codec * codec,unsigned int res)820 static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res)
821 {
822 struct cs8409_spec *spec = codec->spec;
823 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
824 struct hda_jack_tbl *jk;
825
826 /* jack_unsol_event() will be called every time gpio line changing state.
827 * In this case gpio4 line goes up as a result of reading interrupt status
828 * registers in previous cs8409_jack_unsol_event() call.
829 * We don't need to handle this event, ignoring...
830 */
831 if (res & cs42l42->irq_mask)
832 return;
833
834 if (cs42l42_jack_unsol_event(cs42l42)) {
835 snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID,
836 cs42l42->hp_jack_in ? 0 : PIN_OUT);
837 /* Report jack*/
838 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0);
839 if (jk)
840 snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
841 AC_UNSOL_RES_TAG);
842 /* Report jack*/
843 jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0);
844 if (jk)
845 snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
846 AC_UNSOL_RES_TAG);
847 }
848 }
849
850 #ifdef CONFIG_PM
851 /* Manage PDREF, when transition to D3hot */
cs8409_cs42l42_suspend(struct hda_codec * codec)852 static int cs8409_cs42l42_suspend(struct hda_codec *codec)
853 {
854 struct cs8409_spec *spec = codec->spec;
855 int i;
856
857 spec->init_done = 0;
858
859 cs8409_enable_ur(codec, 0);
860
861 for (i = 0; i < spec->num_scodecs; i++)
862 cs42l42_suspend(spec->scodecs[i]);
863
864 /* Cancel i2c clock disable timer, and disable clock if left enabled */
865 cancel_delayed_work_sync(&spec->i2c_clk_work);
866 cs8409_disable_i2c_clock(codec);
867
868 snd_hda_shutup_pins(codec);
869
870 return 0;
871 }
872 #endif
873
874 /* Vendor specific HW configuration
875 * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
876 */
cs8409_cs42l42_hw_init(struct hda_codec * codec)877 static void cs8409_cs42l42_hw_init(struct hda_codec *codec)
878 {
879 const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg;
880 const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn;
881 struct cs8409_spec *spec = codec->spec;
882 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
883
884 if (spec->gpio_mask) {
885 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
886 spec->gpio_mask);
887 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
888 spec->gpio_dir);
889 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
890 spec->gpio_data);
891 }
892
893 for (; seq->nid; seq++)
894 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
895
896 if (codec->fixup_id == CS8409_BULLSEYE) {
897 for (; seq_bullseye->nid; seq_bullseye++)
898 cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff);
899 }
900
901 /* DMIC1_MO=00b, DMIC1/2_SR=1 */
902 if (codec->fixup_id == CS8409_WARLOCK || codec->fixup_id == CS8409_CYBORG)
903 cs8409_vendor_coef_set(codec, 0x09, 0x0003);
904
905 cs42l42_resume(cs42l42);
906
907 /* Enable Unsolicited Response */
908 cs8409_enable_ur(codec, 1);
909 }
910
911 static const struct hda_codec_ops cs8409_cs42l42_patch_ops = {
912 .build_controls = cs8409_build_controls,
913 .build_pcms = snd_hda_gen_build_pcms,
914 .init = cs8409_init,
915 .free = cs8409_free,
916 .unsol_event = cs8409_cs42l42_jack_unsol_event,
917 #ifdef CONFIG_PM
918 .suspend = cs8409_cs42l42_suspend,
919 #endif
920 };
921
cs8409_cs42l42_exec_verb(struct hdac_device * dev,unsigned int cmd,unsigned int flags,unsigned int * res)922 static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
923 unsigned int *res)
924 {
925 struct hda_codec *codec = container_of(dev, struct hda_codec, core);
926 struct cs8409_spec *spec = codec->spec;
927 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
928
929 unsigned int nid = ((cmd >> 20) & 0x07f);
930 unsigned int verb = ((cmd >> 8) & 0x0fff);
931
932 /* CS8409 pins have no AC_PINSENSE_PRESENCE
933 * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34
934 * and return correct pin sense values for read_pin_sense() call from
935 * hda_jack based on CS42L42 jack detect status.
936 */
937 switch (nid) {
938 case CS8409_CS42L42_HP_PIN_NID:
939 if (verb == AC_VERB_GET_PIN_SENSE) {
940 *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
941 return 0;
942 }
943 break;
944 case CS8409_CS42L42_AMIC_PIN_NID:
945 if (verb == AC_VERB_GET_PIN_SENSE) {
946 *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
947 return 0;
948 }
949 break;
950 default:
951 break;
952 }
953
954 return spec->exec_verb(dev, cmd, flags, res);
955 }
956
cs8409_cs42l42_fixups(struct hda_codec * codec,const struct hda_fixup * fix,int action)957 void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
958 {
959 struct cs8409_spec *spec = codec->spec;
960
961 switch (action) {
962 case HDA_FIXUP_ACT_PRE_PROBE:
963 snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs);
964 /* verb exec op override */
965 spec->exec_verb = codec->core.exec_verb;
966 codec->core.exec_verb = cs8409_cs42l42_exec_verb;
967
968 spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec;
969 spec->num_scodecs = 1;
970 spec->scodecs[CS8409_CODEC0]->codec = codec;
971 codec->patch_ops = cs8409_cs42l42_patch_ops;
972
973 spec->gen.suppress_auto_mute = 1;
974 spec->gen.no_primary_hp = 1;
975 spec->gen.suppress_vmaster = 1;
976
977 /* GPIO 5 out, 3,4 in */
978 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio;
979 spec->gpio_data = 0;
980 spec->gpio_mask = 0x03f;
981
982 /* Basic initial sequence for specific hw configuration */
983 snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs);
984
985 cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID);
986 cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID);
987
988 /* Set TIP_SENSE_EN for analog front-end of tip sense.
989 * Additionally set HSBIAS_SENSE_EN and Full Scale volume for some variants.
990 */
991 switch (codec->fixup_id) {
992 case CS8409_WARLOCK:
993 spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
994 spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1;
995 break;
996 case CS8409_BULLSEYE:
997 spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020;
998 spec->scodecs[CS8409_CODEC0]->full_scale_vol = 0;
999 break;
1000 case CS8409_CYBORG:
1001 spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x00a0;
1002 spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1;
1003 break;
1004 default:
1005 spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0003;
1006 spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1;
1007 break;
1008 }
1009
1010 break;
1011 case HDA_FIXUP_ACT_PROBE:
1012 /* Fix Sample Rate to 48kHz */
1013 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1014 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1015 /* add hooks */
1016 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1017 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1018 /* Set initial DMIC volume to -26 dB */
1019 snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID,
1020 HDA_INPUT, 0, 0xff, 0x19);
1021 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1022 &cs42l42_dac_volume_mixer);
1023 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume",
1024 &cs42l42_adc_volume_mixer);
1025 /* Disable Unsolicited Response during boot */
1026 cs8409_enable_ur(codec, 0);
1027 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1028 break;
1029 case HDA_FIXUP_ACT_INIT:
1030 cs8409_cs42l42_hw_init(codec);
1031 spec->init_done = 1;
1032 if (spec->init_done && spec->build_ctrl_done
1033 && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1034 cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1035 break;
1036 case HDA_FIXUP_ACT_BUILD:
1037 spec->build_ctrl_done = 1;
1038 /* Run jack auto detect first time on boot
1039 * after controls have been added, to check if jack has
1040 * been already plugged in.
1041 * Run immediately after init.
1042 */
1043 if (spec->init_done && spec->build_ctrl_done
1044 && !spec->scodecs[CS8409_CODEC0]->hp_jack_in)
1045 cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]);
1046 break;
1047 default:
1048 break;
1049 }
1050 }
1051
1052 /******************************************************************************
1053 * Dolphin Specific Functions
1054 * CS8409/ 2 X CS42L42
1055 ******************************************************************************/
1056
1057 /*
1058 * In the case of CS8409 we do not have unsolicited events when
1059 * hs mic and hp are connected. Companion codec CS42L42 will
1060 * generate interrupt via irq_mask to notify jack events. We have to overwrite
1061 * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers
1062 * and then notify status via generic snd_hda_jack_unsol_event() call.
1063 */
dolphin_jack_unsol_event(struct hda_codec * codec,unsigned int res)1064 static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res)
1065 {
1066 struct cs8409_spec *spec = codec->spec;
1067 struct sub_codec *cs42l42;
1068 struct hda_jack_tbl *jk;
1069
1070 cs42l42 = spec->scodecs[CS8409_CODEC0];
1071 if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1072 cs42l42_jack_unsol_event(cs42l42)) {
1073 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0);
1074 if (jk)
1075 snd_hda_jack_unsol_event(codec,
1076 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1077 AC_UNSOL_RES_TAG);
1078
1079 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0);
1080 if (jk)
1081 snd_hda_jack_unsol_event(codec,
1082 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1083 AC_UNSOL_RES_TAG);
1084 }
1085
1086 cs42l42 = spec->scodecs[CS8409_CODEC1];
1087 if (!cs42l42->suspended && (~res & cs42l42->irq_mask) &&
1088 cs42l42_jack_unsol_event(cs42l42)) {
1089 jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0);
1090 if (jk)
1091 snd_hda_jack_unsol_event(codec,
1092 (jk->tag << AC_UNSOL_RES_TAG_SHIFT) &
1093 AC_UNSOL_RES_TAG);
1094 }
1095 }
1096
1097 /* Vendor specific HW configuration
1098 * PLL, ASP, I2C, SPI, GPIOs, DMIC etc...
1099 */
dolphin_hw_init(struct hda_codec * codec)1100 static void dolphin_hw_init(struct hda_codec *codec)
1101 {
1102 const struct cs8409_cir_param *seq = dolphin_hw_cfg;
1103 struct cs8409_spec *spec = codec->spec;
1104 struct sub_codec *cs42l42;
1105 int i;
1106
1107 if (spec->gpio_mask) {
1108 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK,
1109 spec->gpio_mask);
1110 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION,
1111 spec->gpio_dir);
1112 snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA,
1113 spec->gpio_data);
1114 }
1115
1116 for (; seq->nid; seq++)
1117 cs8409_vendor_coef_set(codec, seq->cir, seq->coeff);
1118
1119 for (i = 0; i < spec->num_scodecs; i++) {
1120 cs42l42 = spec->scodecs[i];
1121 cs42l42_resume(cs42l42);
1122 }
1123
1124 /* Enable Unsolicited Response */
1125 cs8409_enable_ur(codec, 1);
1126 }
1127
1128 static const struct hda_codec_ops cs8409_dolphin_patch_ops = {
1129 .build_controls = cs8409_build_controls,
1130 .build_pcms = snd_hda_gen_build_pcms,
1131 .init = cs8409_init,
1132 .free = cs8409_free,
1133 .unsol_event = dolphin_jack_unsol_event,
1134 #ifdef CONFIG_PM
1135 .suspend = cs8409_cs42l42_suspend,
1136 #endif
1137 };
1138
dolphin_exec_verb(struct hdac_device * dev,unsigned int cmd,unsigned int flags,unsigned int * res)1139 static int dolphin_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags,
1140 unsigned int *res)
1141 {
1142 struct hda_codec *codec = container_of(dev, struct hda_codec, core);
1143 struct cs8409_spec *spec = codec->spec;
1144 struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0];
1145
1146 unsigned int nid = ((cmd >> 20) & 0x07f);
1147 unsigned int verb = ((cmd >> 8) & 0x0fff);
1148
1149 /* CS8409 pins have no AC_PINSENSE_PRESENCE
1150 * capabilities. We have to intercept calls for CS42L42 pins
1151 * and return correct pin sense values for read_pin_sense() call from
1152 * hda_jack based on CS42L42 jack detect status.
1153 */
1154 switch (nid) {
1155 case DOLPHIN_HP_PIN_NID:
1156 case DOLPHIN_LO_PIN_NID:
1157 if (nid == DOLPHIN_LO_PIN_NID)
1158 cs42l42 = spec->scodecs[CS8409_CODEC1];
1159 if (verb == AC_VERB_GET_PIN_SENSE) {
1160 *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1161 return 0;
1162 }
1163 break;
1164 case DOLPHIN_AMIC_PIN_NID:
1165 if (verb == AC_VERB_GET_PIN_SENSE) {
1166 *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0;
1167 return 0;
1168 }
1169 break;
1170 default:
1171 break;
1172 }
1173
1174 return spec->exec_verb(dev, cmd, flags, res);
1175 }
1176
dolphin_fixups(struct hda_codec * codec,const struct hda_fixup * fix,int action)1177 void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action)
1178 {
1179 struct cs8409_spec *spec = codec->spec;
1180 struct snd_kcontrol_new *kctrl;
1181 int i;
1182
1183 switch (action) {
1184 case HDA_FIXUP_ACT_PRE_PROBE:
1185 snd_hda_add_verbs(codec, dolphin_init_verbs);
1186 /* verb exec op override */
1187 spec->exec_verb = codec->core.exec_verb;
1188 codec->core.exec_verb = dolphin_exec_verb;
1189
1190 spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0;
1191 spec->scodecs[CS8409_CODEC0]->codec = codec;
1192 spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1;
1193 spec->scodecs[CS8409_CODEC1]->codec = codec;
1194 spec->num_scodecs = 2;
1195
1196 codec->patch_ops = cs8409_dolphin_patch_ops;
1197
1198 /* GPIO 1,5 out, 0,4 in */
1199 spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio |
1200 spec->scodecs[CS8409_CODEC1]->reset_gpio;
1201 spec->gpio_data = 0;
1202 spec->gpio_mask = 0x03f;
1203
1204 /* Basic initial sequence for specific hw configuration */
1205 snd_hda_sequence_write(codec, dolphin_init_verbs);
1206
1207 snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true,
1208 SND_JACK_HEADPHONE, NULL);
1209
1210 snd_hda_jack_add_kctl(codec, DOLPHIN_AMIC_PIN_NID, "Microphone", true,
1211 SND_JACK_MICROPHONE, NULL);
1212
1213 cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID);
1214 cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID);
1215 cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID);
1216
1217 break;
1218 case HDA_FIXUP_ACT_PROBE:
1219 /* Fix Sample Rate to 48kHz */
1220 spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback;
1221 spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture;
1222 /* add hooks */
1223 spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook;
1224 spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook;
1225 snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume",
1226 &cs42l42_dac_volume_mixer);
1227 snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer);
1228 kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume",
1229 &cs42l42_dac_volume_mixer);
1230 /* Update Line Out kcontrol template */
1231 kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1,
1232 HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE;
1233 cs8409_enable_ur(codec, 0);
1234 snd_hda_codec_set_name(codec, "CS8409/CS42L42");
1235 break;
1236 case HDA_FIXUP_ACT_INIT:
1237 dolphin_hw_init(codec);
1238 spec->init_done = 1;
1239 if (spec->init_done && spec->build_ctrl_done) {
1240 for (i = 0; i < spec->num_scodecs; i++) {
1241 if (!spec->scodecs[i]->hp_jack_in)
1242 cs42l42_run_jack_detect(spec->scodecs[i]);
1243 }
1244 }
1245 break;
1246 case HDA_FIXUP_ACT_BUILD:
1247 spec->build_ctrl_done = 1;
1248 /* Run jack auto detect first time on boot
1249 * after controls have been added, to check if jack has
1250 * been already plugged in.
1251 * Run immediately after init.
1252 */
1253 if (spec->init_done && spec->build_ctrl_done) {
1254 for (i = 0; i < spec->num_scodecs; i++) {
1255 if (!spec->scodecs[i]->hp_jack_in)
1256 cs42l42_run_jack_detect(spec->scodecs[i]);
1257 }
1258 }
1259 break;
1260 default:
1261 break;
1262 }
1263 }
1264
patch_cs8409(struct hda_codec * codec)1265 static int patch_cs8409(struct hda_codec *codec)
1266 {
1267 int err;
1268
1269 if (!cs8409_alloc_spec(codec))
1270 return -ENOMEM;
1271
1272 snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups);
1273
1274 codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id,
1275 codec->bus->pci->subsystem_vendor,
1276 codec->bus->pci->subsystem_device);
1277
1278 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE);
1279
1280 err = cs8409_parse_auto_config(codec);
1281 if (err < 0) {
1282 cs8409_free(codec);
1283 return err;
1284 }
1285
1286 snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE);
1287 return 0;
1288 }
1289
1290 static const struct hda_device_id snd_hda_id_cs8409[] = {
1291 HDA_CODEC_ENTRY(0x10138409, "CS8409", patch_cs8409),
1292 {} /* terminator */
1293 };
1294 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cs8409);
1295
1296 static struct hda_codec_driver cs8409_driver = {
1297 .id = snd_hda_id_cs8409,
1298 };
1299 module_hda_codec_driver(cs8409_driver);
1300
1301 MODULE_LICENSE("GPL");
1302 MODULE_DESCRIPTION("Cirrus Logic HDA bridge");
1303
