1 // SPDX-License-Identifier: GPL-1.0+
2 /*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23 /*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42 /*#define DBGTBUF(info) dump_tbufs(info)*/
43 /*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46 #include <linux/module.h>
47 #include <linux/errno.h>
48 #include <linux/signal.h>
49 #include <linux/sched.h>
50 #include <linux/timer.h>
51 #include <linux/interrupt.h>
52 #include <linux/pci.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55 #include <linux/serial.h>
56 #include <linux/major.h>
57 #include <linux/string.h>
58 #include <linux/fcntl.h>
59 #include <linux/ptrace.h>
60 #include <linux/ioport.h>
61 #include <linux/mm.h>
62 #include <linux/seq_file.h>
63 #include <linux/slab.h>
64 #include <linux/netdevice.h>
65 #include <linux/vmalloc.h>
66 #include <linux/init.h>
67 #include <linux/delay.h>
68 #include <linux/ioctl.h>
69 #include <linux/termios.h>
70 #include <linux/bitops.h>
71 #include <linux/workqueue.h>
72 #include <linux/hdlc.h>
73 #include <linux/synclink.h>
74
75 #include <asm/io.h>
76 #include <asm/irq.h>
77 #include <asm/dma.h>
78 #include <asm/types.h>
79 #include <linux/uaccess.h>
80
81 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82 #define SYNCLINK_GENERIC_HDLC 1
83 #else
84 #define SYNCLINK_GENERIC_HDLC 0
85 #endif
86
87 /*
88 * module identification
89 */
90 static char *driver_name = "SyncLink GT";
91 static char *slgt_driver_name = "synclink_gt";
92 static char *tty_dev_prefix = "ttySLG";
93 MODULE_LICENSE("GPL");
94 #define MGSL_MAGIC 0x5401
95 #define MAX_DEVICES 32
96
97 static const struct pci_device_id pci_table[] = {
98 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
99 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {0,}, /* terminate list */
103 };
104 MODULE_DEVICE_TABLE(pci, pci_table);
105
106 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
107 static void remove_one(struct pci_dev *dev);
108 static struct pci_driver pci_driver = {
109 .name = "synclink_gt",
110 .id_table = pci_table,
111 .probe = init_one,
112 .remove = remove_one,
113 };
114
115 static bool pci_registered;
116
117 /*
118 * module configuration and status
119 */
120 static struct slgt_info *slgt_device_list;
121 static int slgt_device_count;
122
123 static int ttymajor;
124 static int debug_level;
125 static int maxframe[MAX_DEVICES];
126
127 module_param(ttymajor, int, 0);
128 module_param(debug_level, int, 0);
129 module_param_array(maxframe, int, NULL, 0);
130
131 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
132 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
133 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
134
135 /*
136 * tty support and callbacks
137 */
138 static struct tty_driver *serial_driver;
139
140 static void wait_until_sent(struct tty_struct *tty, int timeout);
141 static void flush_buffer(struct tty_struct *tty);
142 static void tx_release(struct tty_struct *tty);
143
144 /*
145 * generic HDLC support
146 */
147 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
148
149
150 /*
151 * device specific structures, macros and functions
152 */
153
154 #define SLGT_MAX_PORTS 4
155 #define SLGT_REG_SIZE 256
156
157 /*
158 * conditional wait facility
159 */
160 struct cond_wait {
161 struct cond_wait *next;
162 wait_queue_head_t q;
163 wait_queue_entry_t wait;
164 unsigned int data;
165 };
166 static void flush_cond_wait(struct cond_wait **head);
167
168 /*
169 * DMA buffer descriptor and access macros
170 */
171 struct slgt_desc
172 {
173 __le16 count;
174 __le16 status;
175 __le32 pbuf; /* physical address of data buffer */
176 __le32 next; /* physical address of next descriptor */
177
178 /* driver book keeping */
179 char *buf; /* virtual address of data buffer */
180 unsigned int pdesc; /* physical address of this descriptor */
181 dma_addr_t buf_dma_addr;
182 unsigned short buf_count;
183 };
184
185 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
186 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
187 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
188 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
189 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
190 #define desc_count(a) (le16_to_cpu((a).count))
191 #define desc_status(a) (le16_to_cpu((a).status))
192 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
193 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
194 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
195 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
196 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
197
198 struct _input_signal_events {
199 int ri_up;
200 int ri_down;
201 int dsr_up;
202 int dsr_down;
203 int dcd_up;
204 int dcd_down;
205 int cts_up;
206 int cts_down;
207 };
208
209 /*
210 * device instance data structure
211 */
212 struct slgt_info {
213 void *if_ptr; /* General purpose pointer (used by SPPP) */
214 struct tty_port port;
215
216 struct slgt_info *next_device; /* device list link */
217
218 int magic;
219
220 char device_name[25];
221 struct pci_dev *pdev;
222
223 int port_count; /* count of ports on adapter */
224 int adapter_num; /* adapter instance number */
225 int port_num; /* port instance number */
226
227 /* array of pointers to port contexts on this adapter */
228 struct slgt_info *port_array[SLGT_MAX_PORTS];
229
230 int line; /* tty line instance number */
231
232 struct mgsl_icount icount;
233
234 int timeout;
235 int x_char; /* xon/xoff character */
236 unsigned int read_status_mask;
237 unsigned int ignore_status_mask;
238
239 wait_queue_head_t status_event_wait_q;
240 wait_queue_head_t event_wait_q;
241 struct timer_list tx_timer;
242 struct timer_list rx_timer;
243
244 unsigned int gpio_present;
245 struct cond_wait *gpio_wait_q;
246
247 spinlock_t lock; /* spinlock for synchronizing with ISR */
248
249 struct work_struct task;
250 u32 pending_bh;
251 bool bh_requested;
252 bool bh_running;
253
254 int isr_overflow;
255 bool irq_requested; /* true if IRQ requested */
256 bool irq_occurred; /* for diagnostics use */
257
258 /* device configuration */
259
260 unsigned int bus_type;
261 unsigned int irq_level;
262 unsigned long irq_flags;
263
264 unsigned char __iomem * reg_addr; /* memory mapped registers address */
265 u32 phys_reg_addr;
266 bool reg_addr_requested;
267
268 MGSL_PARAMS params; /* communications parameters */
269 u32 idle_mode;
270 u32 max_frame_size; /* as set by device config */
271
272 unsigned int rbuf_fill_level;
273 unsigned int rx_pio;
274 unsigned int if_mode;
275 unsigned int base_clock;
276 unsigned int xsync;
277 unsigned int xctrl;
278
279 /* device status */
280
281 bool rx_enabled;
282 bool rx_restart;
283
284 bool tx_enabled;
285 bool tx_active;
286
287 unsigned char signals; /* serial signal states */
288 int init_error; /* initialization error */
289
290 unsigned char *tx_buf;
291 int tx_count;
292
293 char *flag_buf;
294 bool drop_rts_on_tx_done;
295 struct _input_signal_events input_signal_events;
296
297 int dcd_chkcount; /* check counts to prevent */
298 int cts_chkcount; /* too many IRQs if a signal */
299 int dsr_chkcount; /* is floating */
300 int ri_chkcount;
301
302 char *bufs; /* virtual address of DMA buffer lists */
303 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
304
305 unsigned int rbuf_count;
306 struct slgt_desc *rbufs;
307 unsigned int rbuf_current;
308 unsigned int rbuf_index;
309 unsigned int rbuf_fill_index;
310 unsigned short rbuf_fill_count;
311
312 unsigned int tbuf_count;
313 struct slgt_desc *tbufs;
314 unsigned int tbuf_current;
315 unsigned int tbuf_start;
316
317 unsigned char *tmp_rbuf;
318 unsigned int tmp_rbuf_count;
319
320 /* SPPP/Cisco HDLC device parts */
321
322 int netcount;
323 spinlock_t netlock;
324 #if SYNCLINK_GENERIC_HDLC
325 struct net_device *netdev;
326 #endif
327
328 };
329
330 static MGSL_PARAMS default_params = {
331 .mode = MGSL_MODE_HDLC,
332 .loopback = 0,
333 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
334 .encoding = HDLC_ENCODING_NRZI_SPACE,
335 .clock_speed = 0,
336 .addr_filter = 0xff,
337 .crc_type = HDLC_CRC_16_CCITT,
338 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
339 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
340 .data_rate = 9600,
341 .data_bits = 8,
342 .stop_bits = 1,
343 .parity = ASYNC_PARITY_NONE
344 };
345
346
347 #define BH_RECEIVE 1
348 #define BH_TRANSMIT 2
349 #define BH_STATUS 4
350 #define IO_PIN_SHUTDOWN_LIMIT 100
351
352 #define DMABUFSIZE 256
353 #define DESC_LIST_SIZE 4096
354
355 #define MASK_PARITY BIT1
356 #define MASK_FRAMING BIT0
357 #define MASK_BREAK BIT14
358 #define MASK_OVERRUN BIT4
359
360 #define GSR 0x00 /* global status */
361 #define JCR 0x04 /* JTAG control */
362 #define IODR 0x08 /* GPIO direction */
363 #define IOER 0x0c /* GPIO interrupt enable */
364 #define IOVR 0x10 /* GPIO value */
365 #define IOSR 0x14 /* GPIO interrupt status */
366 #define TDR 0x80 /* tx data */
367 #define RDR 0x80 /* rx data */
368 #define TCR 0x82 /* tx control */
369 #define TIR 0x84 /* tx idle */
370 #define TPR 0x85 /* tx preamble */
371 #define RCR 0x86 /* rx control */
372 #define VCR 0x88 /* V.24 control */
373 #define CCR 0x89 /* clock control */
374 #define BDR 0x8a /* baud divisor */
375 #define SCR 0x8c /* serial control */
376 #define SSR 0x8e /* serial status */
377 #define RDCSR 0x90 /* rx DMA control/status */
378 #define TDCSR 0x94 /* tx DMA control/status */
379 #define RDDAR 0x98 /* rx DMA descriptor address */
380 #define TDDAR 0x9c /* tx DMA descriptor address */
381 #define XSR 0x40 /* extended sync pattern */
382 #define XCR 0x44 /* extended control */
383
384 #define RXIDLE BIT14
385 #define RXBREAK BIT14
386 #define IRQ_TXDATA BIT13
387 #define IRQ_TXIDLE BIT12
388 #define IRQ_TXUNDER BIT11 /* HDLC */
389 #define IRQ_RXDATA BIT10
390 #define IRQ_RXIDLE BIT9 /* HDLC */
391 #define IRQ_RXBREAK BIT9 /* async */
392 #define IRQ_RXOVER BIT8
393 #define IRQ_DSR BIT7
394 #define IRQ_CTS BIT6
395 #define IRQ_DCD BIT5
396 #define IRQ_RI BIT4
397 #define IRQ_ALL 0x3ff0
398 #define IRQ_MASTER BIT0
399
400 #define slgt_irq_on(info, mask) \
401 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
402 #define slgt_irq_off(info, mask) \
403 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
404
405 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
406 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
407 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
408 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
409 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
410 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
411
412 static void msc_set_vcr(struct slgt_info *info);
413
414 static int startup(struct slgt_info *info);
415 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
416 static void shutdown(struct slgt_info *info);
417 static void program_hw(struct slgt_info *info);
418 static void change_params(struct slgt_info *info);
419
420 static int adapter_test(struct slgt_info *info);
421
422 static void reset_port(struct slgt_info *info);
423 static void async_mode(struct slgt_info *info);
424 static void sync_mode(struct slgt_info *info);
425
426 static void rx_stop(struct slgt_info *info);
427 static void rx_start(struct slgt_info *info);
428 static void reset_rbufs(struct slgt_info *info);
429 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
430 static bool rx_get_frame(struct slgt_info *info);
431 static bool rx_get_buf(struct slgt_info *info);
432
433 static void tx_start(struct slgt_info *info);
434 static void tx_stop(struct slgt_info *info);
435 static void tx_set_idle(struct slgt_info *info);
436 static unsigned int tbuf_bytes(struct slgt_info *info);
437 static void reset_tbufs(struct slgt_info *info);
438 static void tdma_reset(struct slgt_info *info);
439 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
440
441 static void get_gtsignals(struct slgt_info *info);
442 static void set_gtsignals(struct slgt_info *info);
443 static void set_rate(struct slgt_info *info, u32 data_rate);
444
445 static void bh_transmit(struct slgt_info *info);
446 static void isr_txeom(struct slgt_info *info, unsigned short status);
447
448 static void tx_timeout(struct timer_list *t);
449 static void rx_timeout(struct timer_list *t);
450
451 /*
452 * ioctl handlers
453 */
454 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
455 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
456 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
457 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
458 static int set_txidle(struct slgt_info *info, int idle_mode);
459 static int tx_enable(struct slgt_info *info, int enable);
460 static int tx_abort(struct slgt_info *info);
461 static int rx_enable(struct slgt_info *info, int enable);
462 static int modem_input_wait(struct slgt_info *info,int arg);
463 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
464 static int get_interface(struct slgt_info *info, int __user *if_mode);
465 static int set_interface(struct slgt_info *info, int if_mode);
466 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
467 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
468 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
469 static int get_xsync(struct slgt_info *info, int __user *if_mode);
470 static int set_xsync(struct slgt_info *info, int if_mode);
471 static int get_xctrl(struct slgt_info *info, int __user *if_mode);
472 static int set_xctrl(struct slgt_info *info, int if_mode);
473
474 /*
475 * driver functions
476 */
477 static void release_resources(struct slgt_info *info);
478
479 /*
480 * DEBUG OUTPUT CODE
481 */
482 #ifndef DBGINFO
483 #define DBGINFO(fmt)
484 #endif
485 #ifndef DBGERR
486 #define DBGERR(fmt)
487 #endif
488 #ifndef DBGBH
489 #define DBGBH(fmt)
490 #endif
491 #ifndef DBGISR
492 #define DBGISR(fmt)
493 #endif
494
495 #ifdef DBGDATA
trace_block(struct slgt_info * info,const char * data,int count,const char * label)496 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
497 {
498 int i;
499 int linecount;
500 printk("%s %s data:\n",info->device_name, label);
501 while(count) {
502 linecount = (count > 16) ? 16 : count;
503 for(i=0; i < linecount; i++)
504 printk("%02X ",(unsigned char)data[i]);
505 for(;i<17;i++)
506 printk(" ");
507 for(i=0;i<linecount;i++) {
508 if (data[i]>=040 && data[i]<=0176)
509 printk("%c",data[i]);
510 else
511 printk(".");
512 }
513 printk("\n");
514 data += linecount;
515 count -= linecount;
516 }
517 }
518 #else
519 #define DBGDATA(info, buf, size, label)
520 #endif
521
522 #ifdef DBGTBUF
dump_tbufs(struct slgt_info * info)523 static void dump_tbufs(struct slgt_info *info)
524 {
525 int i;
526 printk("tbuf_current=%d\n", info->tbuf_current);
527 for (i=0 ; i < info->tbuf_count ; i++) {
528 printk("%d: count=%04X status=%04X\n",
529 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
530 }
531 }
532 #else
533 #define DBGTBUF(info)
534 #endif
535
536 #ifdef DBGRBUF
dump_rbufs(struct slgt_info * info)537 static void dump_rbufs(struct slgt_info *info)
538 {
539 int i;
540 printk("rbuf_current=%d\n", info->rbuf_current);
541 for (i=0 ; i < info->rbuf_count ; i++) {
542 printk("%d: count=%04X status=%04X\n",
543 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
544 }
545 }
546 #else
547 #define DBGRBUF(info)
548 #endif
549
sanity_check(struct slgt_info * info,char * devname,const char * name)550 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
551 {
552 #ifdef SANITY_CHECK
553 if (!info) {
554 printk("null struct slgt_info for (%s) in %s\n", devname, name);
555 return 1;
556 }
557 if (info->magic != MGSL_MAGIC) {
558 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
559 return 1;
560 }
561 #else
562 if (!info)
563 return 1;
564 #endif
565 return 0;
566 }
567
568 /*
569 * line discipline callback wrappers
570 *
571 * The wrappers maintain line discipline references
572 * while calling into the line discipline.
573 *
574 * ldisc_receive_buf - pass receive data to line discipline
575 */
ldisc_receive_buf(struct tty_struct * tty,const __u8 * data,char * flags,int count)576 static void ldisc_receive_buf(struct tty_struct *tty,
577 const __u8 *data, char *flags, int count)
578 {
579 struct tty_ldisc *ld;
580 if (!tty)
581 return;
582 ld = tty_ldisc_ref(tty);
583 if (ld) {
584 if (ld->ops->receive_buf)
585 ld->ops->receive_buf(tty, data, flags, count);
586 tty_ldisc_deref(ld);
587 }
588 }
589
590 /* tty callbacks */
591
open(struct tty_struct * tty,struct file * filp)592 static int open(struct tty_struct *tty, struct file *filp)
593 {
594 struct slgt_info *info;
595 int retval, line;
596 unsigned long flags;
597
598 line = tty->index;
599 if (line >= slgt_device_count) {
600 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
601 return -ENODEV;
602 }
603
604 info = slgt_device_list;
605 while(info && info->line != line)
606 info = info->next_device;
607 if (sanity_check(info, tty->name, "open"))
608 return -ENODEV;
609 if (info->init_error) {
610 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
611 return -ENODEV;
612 }
613
614 tty->driver_data = info;
615 info->port.tty = tty;
616
617 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
618
619 mutex_lock(&info->port.mutex);
620
621 spin_lock_irqsave(&info->netlock, flags);
622 if (info->netcount) {
623 retval = -EBUSY;
624 spin_unlock_irqrestore(&info->netlock, flags);
625 mutex_unlock(&info->port.mutex);
626 goto cleanup;
627 }
628 info->port.count++;
629 spin_unlock_irqrestore(&info->netlock, flags);
630
631 if (info->port.count == 1) {
632 /* 1st open on this device, init hardware */
633 retval = startup(info);
634 if (retval < 0) {
635 mutex_unlock(&info->port.mutex);
636 goto cleanup;
637 }
638 }
639 mutex_unlock(&info->port.mutex);
640 retval = block_til_ready(tty, filp, info);
641 if (retval) {
642 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
643 goto cleanup;
644 }
645
646 retval = 0;
647
648 cleanup:
649 if (retval) {
650 if (tty->count == 1)
651 info->port.tty = NULL; /* tty layer will release tty struct */
652 if(info->port.count)
653 info->port.count--;
654 }
655
656 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
657 return retval;
658 }
659
close(struct tty_struct * tty,struct file * filp)660 static void close(struct tty_struct *tty, struct file *filp)
661 {
662 struct slgt_info *info = tty->driver_data;
663
664 if (sanity_check(info, tty->name, "close"))
665 return;
666 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
667
668 if (tty_port_close_start(&info->port, tty, filp) == 0)
669 goto cleanup;
670
671 mutex_lock(&info->port.mutex);
672 if (tty_port_initialized(&info->port))
673 wait_until_sent(tty, info->timeout);
674 flush_buffer(tty);
675 tty_ldisc_flush(tty);
676
677 shutdown(info);
678 mutex_unlock(&info->port.mutex);
679
680 tty_port_close_end(&info->port, tty);
681 info->port.tty = NULL;
682 cleanup:
683 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
684 }
685
hangup(struct tty_struct * tty)686 static void hangup(struct tty_struct *tty)
687 {
688 struct slgt_info *info = tty->driver_data;
689 unsigned long flags;
690
691 if (sanity_check(info, tty->name, "hangup"))
692 return;
693 DBGINFO(("%s hangup\n", info->device_name));
694
695 flush_buffer(tty);
696
697 mutex_lock(&info->port.mutex);
698 shutdown(info);
699
700 spin_lock_irqsave(&info->port.lock, flags);
701 info->port.count = 0;
702 info->port.tty = NULL;
703 spin_unlock_irqrestore(&info->port.lock, flags);
704 tty_port_set_active(&info->port, 0);
705 mutex_unlock(&info->port.mutex);
706
707 wake_up_interruptible(&info->port.open_wait);
708 }
709
set_termios(struct tty_struct * tty,struct ktermios * old_termios)710 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
711 {
712 struct slgt_info *info = tty->driver_data;
713 unsigned long flags;
714
715 DBGINFO(("%s set_termios\n", tty->driver->name));
716
717 change_params(info);
718
719 /* Handle transition to B0 status */
720 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
721 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
722 spin_lock_irqsave(&info->lock,flags);
723 set_gtsignals(info);
724 spin_unlock_irqrestore(&info->lock,flags);
725 }
726
727 /* Handle transition away from B0 status */
728 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
729 info->signals |= SerialSignal_DTR;
730 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
731 info->signals |= SerialSignal_RTS;
732 spin_lock_irqsave(&info->lock,flags);
733 set_gtsignals(info);
734 spin_unlock_irqrestore(&info->lock,flags);
735 }
736
737 /* Handle turning off CRTSCTS */
738 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
739 tty->hw_stopped = 0;
740 tx_release(tty);
741 }
742 }
743
update_tx_timer(struct slgt_info * info)744 static void update_tx_timer(struct slgt_info *info)
745 {
746 /*
747 * use worst case speed of 1200bps to calculate transmit timeout
748 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
749 */
750 if (info->params.mode == MGSL_MODE_HDLC) {
751 int timeout = (tbuf_bytes(info) * 7) + 1000;
752 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
753 }
754 }
755
write(struct tty_struct * tty,const unsigned char * buf,int count)756 static int write(struct tty_struct *tty,
757 const unsigned char *buf, int count)
758 {
759 int ret = 0;
760 struct slgt_info *info = tty->driver_data;
761 unsigned long flags;
762
763 if (sanity_check(info, tty->name, "write"))
764 return -EIO;
765
766 DBGINFO(("%s write count=%d\n", info->device_name, count));
767
768 if (!info->tx_buf || (count > info->max_frame_size))
769 return -EIO;
770
771 if (!count || tty->flow.stopped || tty->hw_stopped)
772 return 0;
773
774 spin_lock_irqsave(&info->lock, flags);
775
776 if (info->tx_count) {
777 /* send accumulated data from send_char() */
778 if (!tx_load(info, info->tx_buf, info->tx_count))
779 goto cleanup;
780 info->tx_count = 0;
781 }
782
783 if (tx_load(info, buf, count))
784 ret = count;
785
786 cleanup:
787 spin_unlock_irqrestore(&info->lock, flags);
788 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
789 return ret;
790 }
791
put_char(struct tty_struct * tty,unsigned char ch)792 static int put_char(struct tty_struct *tty, unsigned char ch)
793 {
794 struct slgt_info *info = tty->driver_data;
795 unsigned long flags;
796 int ret = 0;
797
798 if (sanity_check(info, tty->name, "put_char"))
799 return 0;
800 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
801 if (!info->tx_buf)
802 return 0;
803 spin_lock_irqsave(&info->lock,flags);
804 if (info->tx_count < info->max_frame_size) {
805 info->tx_buf[info->tx_count++] = ch;
806 ret = 1;
807 }
808 spin_unlock_irqrestore(&info->lock,flags);
809 return ret;
810 }
811
send_xchar(struct tty_struct * tty,char ch)812 static void send_xchar(struct tty_struct *tty, char ch)
813 {
814 struct slgt_info *info = tty->driver_data;
815 unsigned long flags;
816
817 if (sanity_check(info, tty->name, "send_xchar"))
818 return;
819 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
820 info->x_char = ch;
821 if (ch) {
822 spin_lock_irqsave(&info->lock,flags);
823 if (!info->tx_enabled)
824 tx_start(info);
825 spin_unlock_irqrestore(&info->lock,flags);
826 }
827 }
828
wait_until_sent(struct tty_struct * tty,int timeout)829 static void wait_until_sent(struct tty_struct *tty, int timeout)
830 {
831 struct slgt_info *info = tty->driver_data;
832 unsigned long orig_jiffies, char_time;
833
834 if (!info )
835 return;
836 if (sanity_check(info, tty->name, "wait_until_sent"))
837 return;
838 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
839 if (!tty_port_initialized(&info->port))
840 goto exit;
841
842 orig_jiffies = jiffies;
843
844 /* Set check interval to 1/5 of estimated time to
845 * send a character, and make it at least 1. The check
846 * interval should also be less than the timeout.
847 * Note: use tight timings here to satisfy the NIST-PCTS.
848 */
849
850 if (info->params.data_rate) {
851 char_time = info->timeout/(32 * 5);
852 if (!char_time)
853 char_time++;
854 } else
855 char_time = 1;
856
857 if (timeout)
858 char_time = min_t(unsigned long, char_time, timeout);
859
860 while (info->tx_active) {
861 msleep_interruptible(jiffies_to_msecs(char_time));
862 if (signal_pending(current))
863 break;
864 if (timeout && time_after(jiffies, orig_jiffies + timeout))
865 break;
866 }
867 exit:
868 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
869 }
870
write_room(struct tty_struct * tty)871 static unsigned int write_room(struct tty_struct *tty)
872 {
873 struct slgt_info *info = tty->driver_data;
874 unsigned int ret;
875
876 if (sanity_check(info, tty->name, "write_room"))
877 return 0;
878 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
879 DBGINFO(("%s write_room=%u\n", info->device_name, ret));
880 return ret;
881 }
882
flush_chars(struct tty_struct * tty)883 static void flush_chars(struct tty_struct *tty)
884 {
885 struct slgt_info *info = tty->driver_data;
886 unsigned long flags;
887
888 if (sanity_check(info, tty->name, "flush_chars"))
889 return;
890 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
891
892 if (info->tx_count <= 0 || tty->flow.stopped ||
893 tty->hw_stopped || !info->tx_buf)
894 return;
895
896 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
897
898 spin_lock_irqsave(&info->lock,flags);
899 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
900 info->tx_count = 0;
901 spin_unlock_irqrestore(&info->lock,flags);
902 }
903
flush_buffer(struct tty_struct * tty)904 static void flush_buffer(struct tty_struct *tty)
905 {
906 struct slgt_info *info = tty->driver_data;
907 unsigned long flags;
908
909 if (sanity_check(info, tty->name, "flush_buffer"))
910 return;
911 DBGINFO(("%s flush_buffer\n", info->device_name));
912
913 spin_lock_irqsave(&info->lock, flags);
914 info->tx_count = 0;
915 spin_unlock_irqrestore(&info->lock, flags);
916
917 tty_wakeup(tty);
918 }
919
920 /*
921 * throttle (stop) transmitter
922 */
tx_hold(struct tty_struct * tty)923 static void tx_hold(struct tty_struct *tty)
924 {
925 struct slgt_info *info = tty->driver_data;
926 unsigned long flags;
927
928 if (sanity_check(info, tty->name, "tx_hold"))
929 return;
930 DBGINFO(("%s tx_hold\n", info->device_name));
931 spin_lock_irqsave(&info->lock,flags);
932 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
933 tx_stop(info);
934 spin_unlock_irqrestore(&info->lock,flags);
935 }
936
937 /*
938 * release (start) transmitter
939 */
tx_release(struct tty_struct * tty)940 static void tx_release(struct tty_struct *tty)
941 {
942 struct slgt_info *info = tty->driver_data;
943 unsigned long flags;
944
945 if (sanity_check(info, tty->name, "tx_release"))
946 return;
947 DBGINFO(("%s tx_release\n", info->device_name));
948 spin_lock_irqsave(&info->lock, flags);
949 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
950 info->tx_count = 0;
951 spin_unlock_irqrestore(&info->lock, flags);
952 }
953
954 /*
955 * Service an IOCTL request
956 *
957 * Arguments
958 *
959 * tty pointer to tty instance data
960 * cmd IOCTL command code
961 * arg command argument/context
962 *
963 * Return 0 if success, otherwise error code
964 */
ioctl(struct tty_struct * tty,unsigned int cmd,unsigned long arg)965 static int ioctl(struct tty_struct *tty,
966 unsigned int cmd, unsigned long arg)
967 {
968 struct slgt_info *info = tty->driver_data;
969 void __user *argp = (void __user *)arg;
970 int ret;
971
972 if (sanity_check(info, tty->name, "ioctl"))
973 return -ENODEV;
974 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
975
976 if (cmd != TIOCMIWAIT) {
977 if (tty_io_error(tty))
978 return -EIO;
979 }
980
981 switch (cmd) {
982 case MGSL_IOCWAITEVENT:
983 return wait_mgsl_event(info, argp);
984 case TIOCMIWAIT:
985 return modem_input_wait(info,(int)arg);
986 case MGSL_IOCSGPIO:
987 return set_gpio(info, argp);
988 case MGSL_IOCGGPIO:
989 return get_gpio(info, argp);
990 case MGSL_IOCWAITGPIO:
991 return wait_gpio(info, argp);
992 case MGSL_IOCGXSYNC:
993 return get_xsync(info, argp);
994 case MGSL_IOCSXSYNC:
995 return set_xsync(info, (int)arg);
996 case MGSL_IOCGXCTRL:
997 return get_xctrl(info, argp);
998 case MGSL_IOCSXCTRL:
999 return set_xctrl(info, (int)arg);
1000 }
1001 mutex_lock(&info->port.mutex);
1002 switch (cmd) {
1003 case MGSL_IOCGPARAMS:
1004 ret = get_params(info, argp);
1005 break;
1006 case MGSL_IOCSPARAMS:
1007 ret = set_params(info, argp);
1008 break;
1009 case MGSL_IOCGTXIDLE:
1010 ret = get_txidle(info, argp);
1011 break;
1012 case MGSL_IOCSTXIDLE:
1013 ret = set_txidle(info, (int)arg);
1014 break;
1015 case MGSL_IOCTXENABLE:
1016 ret = tx_enable(info, (int)arg);
1017 break;
1018 case MGSL_IOCRXENABLE:
1019 ret = rx_enable(info, (int)arg);
1020 break;
1021 case MGSL_IOCTXABORT:
1022 ret = tx_abort(info);
1023 break;
1024 case MGSL_IOCGSTATS:
1025 ret = get_stats(info, argp);
1026 break;
1027 case MGSL_IOCGIF:
1028 ret = get_interface(info, argp);
1029 break;
1030 case MGSL_IOCSIF:
1031 ret = set_interface(info,(int)arg);
1032 break;
1033 default:
1034 ret = -ENOIOCTLCMD;
1035 }
1036 mutex_unlock(&info->port.mutex);
1037 return ret;
1038 }
1039
get_icount(struct tty_struct * tty,struct serial_icounter_struct * icount)1040 static int get_icount(struct tty_struct *tty,
1041 struct serial_icounter_struct *icount)
1042
1043 {
1044 struct slgt_info *info = tty->driver_data;
1045 struct mgsl_icount cnow; /* kernel counter temps */
1046 unsigned long flags;
1047
1048 spin_lock_irqsave(&info->lock,flags);
1049 cnow = info->icount;
1050 spin_unlock_irqrestore(&info->lock,flags);
1051
1052 icount->cts = cnow.cts;
1053 icount->dsr = cnow.dsr;
1054 icount->rng = cnow.rng;
1055 icount->dcd = cnow.dcd;
1056 icount->rx = cnow.rx;
1057 icount->tx = cnow.tx;
1058 icount->frame = cnow.frame;
1059 icount->overrun = cnow.overrun;
1060 icount->parity = cnow.parity;
1061 icount->brk = cnow.brk;
1062 icount->buf_overrun = cnow.buf_overrun;
1063
1064 return 0;
1065 }
1066
1067 /*
1068 * support for 32 bit ioctl calls on 64 bit systems
1069 */
1070 #ifdef CONFIG_COMPAT
get_params32(struct slgt_info * info,struct MGSL_PARAMS32 __user * user_params)1071 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1072 {
1073 struct MGSL_PARAMS32 tmp_params;
1074
1075 DBGINFO(("%s get_params32\n", info->device_name));
1076 memset(&tmp_params, 0, sizeof(tmp_params));
1077 tmp_params.mode = (compat_ulong_t)info->params.mode;
1078 tmp_params.loopback = info->params.loopback;
1079 tmp_params.flags = info->params.flags;
1080 tmp_params.encoding = info->params.encoding;
1081 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1082 tmp_params.addr_filter = info->params.addr_filter;
1083 tmp_params.crc_type = info->params.crc_type;
1084 tmp_params.preamble_length = info->params.preamble_length;
1085 tmp_params.preamble = info->params.preamble;
1086 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1087 tmp_params.data_bits = info->params.data_bits;
1088 tmp_params.stop_bits = info->params.stop_bits;
1089 tmp_params.parity = info->params.parity;
1090 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1091 return -EFAULT;
1092 return 0;
1093 }
1094
set_params32(struct slgt_info * info,struct MGSL_PARAMS32 __user * new_params)1095 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1096 {
1097 struct MGSL_PARAMS32 tmp_params;
1098
1099 DBGINFO(("%s set_params32\n", info->device_name));
1100 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1101 return -EFAULT;
1102
1103 spin_lock(&info->lock);
1104 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1105 info->base_clock = tmp_params.clock_speed;
1106 } else {
1107 info->params.mode = tmp_params.mode;
1108 info->params.loopback = tmp_params.loopback;
1109 info->params.flags = tmp_params.flags;
1110 info->params.encoding = tmp_params.encoding;
1111 info->params.clock_speed = tmp_params.clock_speed;
1112 info->params.addr_filter = tmp_params.addr_filter;
1113 info->params.crc_type = tmp_params.crc_type;
1114 info->params.preamble_length = tmp_params.preamble_length;
1115 info->params.preamble = tmp_params.preamble;
1116 info->params.data_rate = tmp_params.data_rate;
1117 info->params.data_bits = tmp_params.data_bits;
1118 info->params.stop_bits = tmp_params.stop_bits;
1119 info->params.parity = tmp_params.parity;
1120 }
1121 spin_unlock(&info->lock);
1122
1123 program_hw(info);
1124
1125 return 0;
1126 }
1127
slgt_compat_ioctl(struct tty_struct * tty,unsigned int cmd,unsigned long arg)1128 static long slgt_compat_ioctl(struct tty_struct *tty,
1129 unsigned int cmd, unsigned long arg)
1130 {
1131 struct slgt_info *info = tty->driver_data;
1132 int rc;
1133
1134 if (sanity_check(info, tty->name, "compat_ioctl"))
1135 return -ENODEV;
1136 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1137
1138 switch (cmd) {
1139 case MGSL_IOCSPARAMS32:
1140 rc = set_params32(info, compat_ptr(arg));
1141 break;
1142
1143 case MGSL_IOCGPARAMS32:
1144 rc = get_params32(info, compat_ptr(arg));
1145 break;
1146
1147 case MGSL_IOCGPARAMS:
1148 case MGSL_IOCSPARAMS:
1149 case MGSL_IOCGTXIDLE:
1150 case MGSL_IOCGSTATS:
1151 case MGSL_IOCWAITEVENT:
1152 case MGSL_IOCGIF:
1153 case MGSL_IOCSGPIO:
1154 case MGSL_IOCGGPIO:
1155 case MGSL_IOCWAITGPIO:
1156 case MGSL_IOCGXSYNC:
1157 case MGSL_IOCGXCTRL:
1158 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1159 break;
1160 default:
1161 rc = ioctl(tty, cmd, arg);
1162 }
1163 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1164 return rc;
1165 }
1166 #else
1167 #define slgt_compat_ioctl NULL
1168 #endif /* ifdef CONFIG_COMPAT */
1169
1170 /*
1171 * proc fs support
1172 */
line_info(struct seq_file * m,struct slgt_info * info)1173 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1174 {
1175 char stat_buf[30];
1176 unsigned long flags;
1177
1178 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1179 info->device_name, info->phys_reg_addr,
1180 info->irq_level, info->max_frame_size);
1181
1182 /* output current serial signal states */
1183 spin_lock_irqsave(&info->lock,flags);
1184 get_gtsignals(info);
1185 spin_unlock_irqrestore(&info->lock,flags);
1186
1187 stat_buf[0] = 0;
1188 stat_buf[1] = 0;
1189 if (info->signals & SerialSignal_RTS)
1190 strcat(stat_buf, "|RTS");
1191 if (info->signals & SerialSignal_CTS)
1192 strcat(stat_buf, "|CTS");
1193 if (info->signals & SerialSignal_DTR)
1194 strcat(stat_buf, "|DTR");
1195 if (info->signals & SerialSignal_DSR)
1196 strcat(stat_buf, "|DSR");
1197 if (info->signals & SerialSignal_DCD)
1198 strcat(stat_buf, "|CD");
1199 if (info->signals & SerialSignal_RI)
1200 strcat(stat_buf, "|RI");
1201
1202 if (info->params.mode != MGSL_MODE_ASYNC) {
1203 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1204 info->icount.txok, info->icount.rxok);
1205 if (info->icount.txunder)
1206 seq_printf(m, " txunder:%d", info->icount.txunder);
1207 if (info->icount.txabort)
1208 seq_printf(m, " txabort:%d", info->icount.txabort);
1209 if (info->icount.rxshort)
1210 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1211 if (info->icount.rxlong)
1212 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1213 if (info->icount.rxover)
1214 seq_printf(m, " rxover:%d", info->icount.rxover);
1215 if (info->icount.rxcrc)
1216 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1217 } else {
1218 seq_printf(m, "\tASYNC tx:%d rx:%d",
1219 info->icount.tx, info->icount.rx);
1220 if (info->icount.frame)
1221 seq_printf(m, " fe:%d", info->icount.frame);
1222 if (info->icount.parity)
1223 seq_printf(m, " pe:%d", info->icount.parity);
1224 if (info->icount.brk)
1225 seq_printf(m, " brk:%d", info->icount.brk);
1226 if (info->icount.overrun)
1227 seq_printf(m, " oe:%d", info->icount.overrun);
1228 }
1229
1230 /* Append serial signal status to end */
1231 seq_printf(m, " %s\n", stat_buf+1);
1232
1233 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1234 info->tx_active,info->bh_requested,info->bh_running,
1235 info->pending_bh);
1236 }
1237
1238 /* Called to print information about devices
1239 */
synclink_gt_proc_show(struct seq_file * m,void * v)1240 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1241 {
1242 struct slgt_info *info;
1243
1244 seq_puts(m, "synclink_gt driver\n");
1245
1246 info = slgt_device_list;
1247 while( info ) {
1248 line_info(m, info);
1249 info = info->next_device;
1250 }
1251 return 0;
1252 }
1253
1254 /*
1255 * return count of bytes in transmit buffer
1256 */
chars_in_buffer(struct tty_struct * tty)1257 static unsigned int chars_in_buffer(struct tty_struct *tty)
1258 {
1259 struct slgt_info *info = tty->driver_data;
1260 unsigned int count;
1261 if (sanity_check(info, tty->name, "chars_in_buffer"))
1262 return 0;
1263 count = tbuf_bytes(info);
1264 DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
1265 return count;
1266 }
1267
1268 /*
1269 * signal remote device to throttle send data (our receive data)
1270 */
throttle(struct tty_struct * tty)1271 static void throttle(struct tty_struct * tty)
1272 {
1273 struct slgt_info *info = tty->driver_data;
1274 unsigned long flags;
1275
1276 if (sanity_check(info, tty->name, "throttle"))
1277 return;
1278 DBGINFO(("%s throttle\n", info->device_name));
1279 if (I_IXOFF(tty))
1280 send_xchar(tty, STOP_CHAR(tty));
1281 if (C_CRTSCTS(tty)) {
1282 spin_lock_irqsave(&info->lock,flags);
1283 info->signals &= ~SerialSignal_RTS;
1284 set_gtsignals(info);
1285 spin_unlock_irqrestore(&info->lock,flags);
1286 }
1287 }
1288
1289 /*
1290 * signal remote device to stop throttling send data (our receive data)
1291 */
unthrottle(struct tty_struct * tty)1292 static void unthrottle(struct tty_struct * tty)
1293 {
1294 struct slgt_info *info = tty->driver_data;
1295 unsigned long flags;
1296
1297 if (sanity_check(info, tty->name, "unthrottle"))
1298 return;
1299 DBGINFO(("%s unthrottle\n", info->device_name));
1300 if (I_IXOFF(tty)) {
1301 if (info->x_char)
1302 info->x_char = 0;
1303 else
1304 send_xchar(tty, START_CHAR(tty));
1305 }
1306 if (C_CRTSCTS(tty)) {
1307 spin_lock_irqsave(&info->lock,flags);
1308 info->signals |= SerialSignal_RTS;
1309 set_gtsignals(info);
1310 spin_unlock_irqrestore(&info->lock,flags);
1311 }
1312 }
1313
1314 /*
1315 * set or clear transmit break condition
1316 * break_state -1=set break condition, 0=clear
1317 */
set_break(struct tty_struct * tty,int break_state)1318 static int set_break(struct tty_struct *tty, int break_state)
1319 {
1320 struct slgt_info *info = tty->driver_data;
1321 unsigned short value;
1322 unsigned long flags;
1323
1324 if (sanity_check(info, tty->name, "set_break"))
1325 return -EINVAL;
1326 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1327
1328 spin_lock_irqsave(&info->lock,flags);
1329 value = rd_reg16(info, TCR);
1330 if (break_state == -1)
1331 value |= BIT6;
1332 else
1333 value &= ~BIT6;
1334 wr_reg16(info, TCR, value);
1335 spin_unlock_irqrestore(&info->lock,flags);
1336 return 0;
1337 }
1338
1339 #if SYNCLINK_GENERIC_HDLC
1340
1341 /**
1342 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1343 * @dev: pointer to network device structure
1344 * @encoding: serial encoding setting
1345 * @parity: FCS setting
1346 *
1347 * Set encoding and frame check sequence (FCS) options.
1348 *
1349 * Return: 0 if success, otherwise error code
1350 */
hdlcdev_attach(struct net_device * dev,unsigned short encoding,unsigned short parity)1351 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1352 unsigned short parity)
1353 {
1354 struct slgt_info *info = dev_to_port(dev);
1355 unsigned char new_encoding;
1356 unsigned short new_crctype;
1357
1358 /* return error if TTY interface open */
1359 if (info->port.count)
1360 return -EBUSY;
1361
1362 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1363
1364 switch (encoding)
1365 {
1366 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1367 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1368 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1369 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1370 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1371 default: return -EINVAL;
1372 }
1373
1374 switch (parity)
1375 {
1376 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1377 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1378 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1379 default: return -EINVAL;
1380 }
1381
1382 info->params.encoding = new_encoding;
1383 info->params.crc_type = new_crctype;
1384
1385 /* if network interface up, reprogram hardware */
1386 if (info->netcount)
1387 program_hw(info);
1388
1389 return 0;
1390 }
1391
1392 /**
1393 * hdlcdev_xmit - called by generic HDLC layer to send a frame
1394 * @skb: socket buffer containing HDLC frame
1395 * @dev: pointer to network device structure
1396 */
hdlcdev_xmit(struct sk_buff * skb,struct net_device * dev)1397 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1398 struct net_device *dev)
1399 {
1400 struct slgt_info *info = dev_to_port(dev);
1401 unsigned long flags;
1402
1403 DBGINFO(("%s hdlc_xmit\n", dev->name));
1404
1405 if (!skb->len)
1406 return NETDEV_TX_OK;
1407
1408 /* stop sending until this frame completes */
1409 netif_stop_queue(dev);
1410
1411 /* update network statistics */
1412 dev->stats.tx_packets++;
1413 dev->stats.tx_bytes += skb->len;
1414
1415 /* save start time for transmit timeout detection */
1416 netif_trans_update(dev);
1417
1418 spin_lock_irqsave(&info->lock, flags);
1419 tx_load(info, skb->data, skb->len);
1420 spin_unlock_irqrestore(&info->lock, flags);
1421
1422 /* done with socket buffer, so free it */
1423 dev_kfree_skb(skb);
1424
1425 return NETDEV_TX_OK;
1426 }
1427
1428 /**
1429 * hdlcdev_open - called by network layer when interface enabled
1430 * @dev: pointer to network device structure
1431 *
1432 * Claim resources and initialize hardware.
1433 *
1434 * Return: 0 if success, otherwise error code
1435 */
hdlcdev_open(struct net_device * dev)1436 static int hdlcdev_open(struct net_device *dev)
1437 {
1438 struct slgt_info *info = dev_to_port(dev);
1439 int rc;
1440 unsigned long flags;
1441
1442 if (!try_module_get(THIS_MODULE))
1443 return -EBUSY;
1444
1445 DBGINFO(("%s hdlcdev_open\n", dev->name));
1446
1447 /* generic HDLC layer open processing */
1448 rc = hdlc_open(dev);
1449 if (rc)
1450 return rc;
1451
1452 /* arbitrate between network and tty opens */
1453 spin_lock_irqsave(&info->netlock, flags);
1454 if (info->port.count != 0 || info->netcount != 0) {
1455 DBGINFO(("%s hdlc_open busy\n", dev->name));
1456 spin_unlock_irqrestore(&info->netlock, flags);
1457 return -EBUSY;
1458 }
1459 info->netcount=1;
1460 spin_unlock_irqrestore(&info->netlock, flags);
1461
1462 /* claim resources and init adapter */
1463 if ((rc = startup(info)) != 0) {
1464 spin_lock_irqsave(&info->netlock, flags);
1465 info->netcount=0;
1466 spin_unlock_irqrestore(&info->netlock, flags);
1467 return rc;
1468 }
1469
1470 /* assert RTS and DTR, apply hardware settings */
1471 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1472 program_hw(info);
1473
1474 /* enable network layer transmit */
1475 netif_trans_update(dev);
1476 netif_start_queue(dev);
1477
1478 /* inform generic HDLC layer of current DCD status */
1479 spin_lock_irqsave(&info->lock, flags);
1480 get_gtsignals(info);
1481 spin_unlock_irqrestore(&info->lock, flags);
1482 if (info->signals & SerialSignal_DCD)
1483 netif_carrier_on(dev);
1484 else
1485 netif_carrier_off(dev);
1486 return 0;
1487 }
1488
1489 /**
1490 * hdlcdev_close - called by network layer when interface is disabled
1491 * @dev: pointer to network device structure
1492 *
1493 * Shutdown hardware and release resources.
1494 *
1495 * Return: 0 if success, otherwise error code
1496 */
hdlcdev_close(struct net_device * dev)1497 static int hdlcdev_close(struct net_device *dev)
1498 {
1499 struct slgt_info *info = dev_to_port(dev);
1500 unsigned long flags;
1501
1502 DBGINFO(("%s hdlcdev_close\n", dev->name));
1503
1504 netif_stop_queue(dev);
1505
1506 /* shutdown adapter and release resources */
1507 shutdown(info);
1508
1509 hdlc_close(dev);
1510
1511 spin_lock_irqsave(&info->netlock, flags);
1512 info->netcount=0;
1513 spin_unlock_irqrestore(&info->netlock, flags);
1514
1515 module_put(THIS_MODULE);
1516 return 0;
1517 }
1518
1519 /**
1520 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1521 * @dev: pointer to network device structure
1522 * @ifr: pointer to network interface request structure
1523 * @cmd: IOCTL command code
1524 *
1525 * Return: 0 if success, otherwise error code
1526 */
hdlcdev_ioctl(struct net_device * dev,struct if_settings * ifs)1527 static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs)
1528 {
1529 const size_t size = sizeof(sync_serial_settings);
1530 sync_serial_settings new_line;
1531 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1532 struct slgt_info *info = dev_to_port(dev);
1533 unsigned int flags;
1534
1535 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1536
1537 /* return error if TTY interface open */
1538 if (info->port.count)
1539 return -EBUSY;
1540
1541 memset(&new_line, 0, sizeof(new_line));
1542
1543 switch (ifs->type) {
1544 case IF_GET_IFACE: /* return current sync_serial_settings */
1545
1546 ifs->type = IF_IFACE_SYNC_SERIAL;
1547 if (ifs->size < size) {
1548 ifs->size = size; /* data size wanted */
1549 return -ENOBUFS;
1550 }
1551
1552 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1553 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1554 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1555 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1556
1557 switch (flags){
1558 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1559 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1560 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1561 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1562 default: new_line.clock_type = CLOCK_DEFAULT;
1563 }
1564
1565 new_line.clock_rate = info->params.clock_speed;
1566 new_line.loopback = info->params.loopback ? 1:0;
1567
1568 if (copy_to_user(line, &new_line, size))
1569 return -EFAULT;
1570 return 0;
1571
1572 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1573
1574 if(!capable(CAP_NET_ADMIN))
1575 return -EPERM;
1576 if (copy_from_user(&new_line, line, size))
1577 return -EFAULT;
1578
1579 switch (new_line.clock_type)
1580 {
1581 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1582 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1583 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1584 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1585 case CLOCK_DEFAULT: flags = info->params.flags &
1586 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1587 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1588 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1589 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1590 default: return -EINVAL;
1591 }
1592
1593 if (new_line.loopback != 0 && new_line.loopback != 1)
1594 return -EINVAL;
1595
1596 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1597 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1598 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1599 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1600 info->params.flags |= flags;
1601
1602 info->params.loopback = new_line.loopback;
1603
1604 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1605 info->params.clock_speed = new_line.clock_rate;
1606 else
1607 info->params.clock_speed = 0;
1608
1609 /* if network interface up, reprogram hardware */
1610 if (info->netcount)
1611 program_hw(info);
1612 return 0;
1613
1614 default:
1615 return hdlc_ioctl(dev, ifs);
1616 }
1617 }
1618
1619 /**
1620 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1621 * @dev: pointer to network device structure
1622 * @txqueue: unused
1623 */
hdlcdev_tx_timeout(struct net_device * dev,unsigned int txqueue)1624 static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1625 {
1626 struct slgt_info *info = dev_to_port(dev);
1627 unsigned long flags;
1628
1629 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1630
1631 dev->stats.tx_errors++;
1632 dev->stats.tx_aborted_errors++;
1633
1634 spin_lock_irqsave(&info->lock,flags);
1635 tx_stop(info);
1636 spin_unlock_irqrestore(&info->lock,flags);
1637
1638 netif_wake_queue(dev);
1639 }
1640
1641 /**
1642 * hdlcdev_tx_done - called by device driver when transmit completes
1643 * @info: pointer to device instance information
1644 *
1645 * Reenable network layer transmit if stopped.
1646 */
hdlcdev_tx_done(struct slgt_info * info)1647 static void hdlcdev_tx_done(struct slgt_info *info)
1648 {
1649 if (netif_queue_stopped(info->netdev))
1650 netif_wake_queue(info->netdev);
1651 }
1652
1653 /**
1654 * hdlcdev_rx - called by device driver when frame received
1655 * @info: pointer to device instance information
1656 * @buf: pointer to buffer contianing frame data
1657 * @size: count of data bytes in buf
1658 *
1659 * Pass frame to network layer.
1660 */
hdlcdev_rx(struct slgt_info * info,char * buf,int size)1661 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1662 {
1663 struct sk_buff *skb = dev_alloc_skb(size);
1664 struct net_device *dev = info->netdev;
1665
1666 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1667
1668 if (skb == NULL) {
1669 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1670 dev->stats.rx_dropped++;
1671 return;
1672 }
1673
1674 skb_put_data(skb, buf, size);
1675
1676 skb->protocol = hdlc_type_trans(skb, dev);
1677
1678 dev->stats.rx_packets++;
1679 dev->stats.rx_bytes += size;
1680
1681 netif_rx(skb);
1682 }
1683
1684 static const struct net_device_ops hdlcdev_ops = {
1685 .ndo_open = hdlcdev_open,
1686 .ndo_stop = hdlcdev_close,
1687 .ndo_start_xmit = hdlc_start_xmit,
1688 .ndo_siocwandev = hdlcdev_ioctl,
1689 .ndo_tx_timeout = hdlcdev_tx_timeout,
1690 };
1691
1692 /**
1693 * hdlcdev_init - called by device driver when adding device instance
1694 * @info: pointer to device instance information
1695 *
1696 * Do generic HDLC initialization.
1697 *
1698 * Return: 0 if success, otherwise error code
1699 */
hdlcdev_init(struct slgt_info * info)1700 static int hdlcdev_init(struct slgt_info *info)
1701 {
1702 int rc;
1703 struct net_device *dev;
1704 hdlc_device *hdlc;
1705
1706 /* allocate and initialize network and HDLC layer objects */
1707
1708 dev = alloc_hdlcdev(info);
1709 if (!dev) {
1710 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1711 return -ENOMEM;
1712 }
1713
1714 /* for network layer reporting purposes only */
1715 dev->mem_start = info->phys_reg_addr;
1716 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1717 dev->irq = info->irq_level;
1718
1719 /* network layer callbacks and settings */
1720 dev->netdev_ops = &hdlcdev_ops;
1721 dev->watchdog_timeo = 10 * HZ;
1722 dev->tx_queue_len = 50;
1723
1724 /* generic HDLC layer callbacks and settings */
1725 hdlc = dev_to_hdlc(dev);
1726 hdlc->attach = hdlcdev_attach;
1727 hdlc->xmit = hdlcdev_xmit;
1728
1729 /* register objects with HDLC layer */
1730 rc = register_hdlc_device(dev);
1731 if (rc) {
1732 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1733 free_netdev(dev);
1734 return rc;
1735 }
1736
1737 info->netdev = dev;
1738 return 0;
1739 }
1740
1741 /**
1742 * hdlcdev_exit - called by device driver when removing device instance
1743 * @info: pointer to device instance information
1744 *
1745 * Do generic HDLC cleanup.
1746 */
hdlcdev_exit(struct slgt_info * info)1747 static void hdlcdev_exit(struct slgt_info *info)
1748 {
1749 unregister_hdlc_device(info->netdev);
1750 free_netdev(info->netdev);
1751 info->netdev = NULL;
1752 }
1753
1754 #endif /* ifdef CONFIG_HDLC */
1755
1756 /*
1757 * get async data from rx DMA buffers
1758 */
rx_async(struct slgt_info * info)1759 static void rx_async(struct slgt_info *info)
1760 {
1761 struct mgsl_icount *icount = &info->icount;
1762 unsigned int start, end;
1763 unsigned char *p;
1764 unsigned char status;
1765 struct slgt_desc *bufs = info->rbufs;
1766 int i, count;
1767 int chars = 0;
1768 int stat;
1769 unsigned char ch;
1770
1771 start = end = info->rbuf_current;
1772
1773 while(desc_complete(bufs[end])) {
1774 count = desc_count(bufs[end]) - info->rbuf_index;
1775 p = bufs[end].buf + info->rbuf_index;
1776
1777 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1778 DBGDATA(info, p, count, "rx");
1779
1780 for(i=0 ; i < count; i+=2, p+=2) {
1781 ch = *p;
1782 icount->rx++;
1783
1784 stat = 0;
1785
1786 status = *(p + 1) & (BIT1 + BIT0);
1787 if (status) {
1788 if (status & BIT1)
1789 icount->parity++;
1790 else if (status & BIT0)
1791 icount->frame++;
1792 /* discard char if tty control flags say so */
1793 if (status & info->ignore_status_mask)
1794 continue;
1795 if (status & BIT1)
1796 stat = TTY_PARITY;
1797 else if (status & BIT0)
1798 stat = TTY_FRAME;
1799 }
1800 tty_insert_flip_char(&info->port, ch, stat);
1801 chars++;
1802 }
1803
1804 if (i < count) {
1805 /* receive buffer not completed */
1806 info->rbuf_index += i;
1807 mod_timer(&info->rx_timer, jiffies + 1);
1808 break;
1809 }
1810
1811 info->rbuf_index = 0;
1812 free_rbufs(info, end, end);
1813
1814 if (++end == info->rbuf_count)
1815 end = 0;
1816
1817 /* if entire list searched then no frame available */
1818 if (end == start)
1819 break;
1820 }
1821
1822 if (chars)
1823 tty_flip_buffer_push(&info->port);
1824 }
1825
1826 /*
1827 * return next bottom half action to perform
1828 */
bh_action(struct slgt_info * info)1829 static int bh_action(struct slgt_info *info)
1830 {
1831 unsigned long flags;
1832 int rc;
1833
1834 spin_lock_irqsave(&info->lock,flags);
1835
1836 if (info->pending_bh & BH_RECEIVE) {
1837 info->pending_bh &= ~BH_RECEIVE;
1838 rc = BH_RECEIVE;
1839 } else if (info->pending_bh & BH_TRANSMIT) {
1840 info->pending_bh &= ~BH_TRANSMIT;
1841 rc = BH_TRANSMIT;
1842 } else if (info->pending_bh & BH_STATUS) {
1843 info->pending_bh &= ~BH_STATUS;
1844 rc = BH_STATUS;
1845 } else {
1846 /* Mark BH routine as complete */
1847 info->bh_running = false;
1848 info->bh_requested = false;
1849 rc = 0;
1850 }
1851
1852 spin_unlock_irqrestore(&info->lock,flags);
1853
1854 return rc;
1855 }
1856
1857 /*
1858 * perform bottom half processing
1859 */
bh_handler(struct work_struct * work)1860 static void bh_handler(struct work_struct *work)
1861 {
1862 struct slgt_info *info = container_of(work, struct slgt_info, task);
1863 int action;
1864
1865 info->bh_running = true;
1866
1867 while((action = bh_action(info))) {
1868 switch (action) {
1869 case BH_RECEIVE:
1870 DBGBH(("%s bh receive\n", info->device_name));
1871 switch(info->params.mode) {
1872 case MGSL_MODE_ASYNC:
1873 rx_async(info);
1874 break;
1875 case MGSL_MODE_HDLC:
1876 while(rx_get_frame(info));
1877 break;
1878 case MGSL_MODE_RAW:
1879 case MGSL_MODE_MONOSYNC:
1880 case MGSL_MODE_BISYNC:
1881 case MGSL_MODE_XSYNC:
1882 while(rx_get_buf(info));
1883 break;
1884 }
1885 /* restart receiver if rx DMA buffers exhausted */
1886 if (info->rx_restart)
1887 rx_start(info);
1888 break;
1889 case BH_TRANSMIT:
1890 bh_transmit(info);
1891 break;
1892 case BH_STATUS:
1893 DBGBH(("%s bh status\n", info->device_name));
1894 info->ri_chkcount = 0;
1895 info->dsr_chkcount = 0;
1896 info->dcd_chkcount = 0;
1897 info->cts_chkcount = 0;
1898 break;
1899 default:
1900 DBGBH(("%s unknown action\n", info->device_name));
1901 break;
1902 }
1903 }
1904 DBGBH(("%s bh_handler exit\n", info->device_name));
1905 }
1906
bh_transmit(struct slgt_info * info)1907 static void bh_transmit(struct slgt_info *info)
1908 {
1909 struct tty_struct *tty = info->port.tty;
1910
1911 DBGBH(("%s bh_transmit\n", info->device_name));
1912 if (tty)
1913 tty_wakeup(tty);
1914 }
1915
dsr_change(struct slgt_info * info,unsigned short status)1916 static void dsr_change(struct slgt_info *info, unsigned short status)
1917 {
1918 if (status & BIT3) {
1919 info->signals |= SerialSignal_DSR;
1920 info->input_signal_events.dsr_up++;
1921 } else {
1922 info->signals &= ~SerialSignal_DSR;
1923 info->input_signal_events.dsr_down++;
1924 }
1925 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1926 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1927 slgt_irq_off(info, IRQ_DSR);
1928 return;
1929 }
1930 info->icount.dsr++;
1931 wake_up_interruptible(&info->status_event_wait_q);
1932 wake_up_interruptible(&info->event_wait_q);
1933 info->pending_bh |= BH_STATUS;
1934 }
1935
cts_change(struct slgt_info * info,unsigned short status)1936 static void cts_change(struct slgt_info *info, unsigned short status)
1937 {
1938 if (status & BIT2) {
1939 info->signals |= SerialSignal_CTS;
1940 info->input_signal_events.cts_up++;
1941 } else {
1942 info->signals &= ~SerialSignal_CTS;
1943 info->input_signal_events.cts_down++;
1944 }
1945 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1946 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1947 slgt_irq_off(info, IRQ_CTS);
1948 return;
1949 }
1950 info->icount.cts++;
1951 wake_up_interruptible(&info->status_event_wait_q);
1952 wake_up_interruptible(&info->event_wait_q);
1953 info->pending_bh |= BH_STATUS;
1954
1955 if (tty_port_cts_enabled(&info->port)) {
1956 if (info->port.tty) {
1957 if (info->port.tty->hw_stopped) {
1958 if (info->signals & SerialSignal_CTS) {
1959 info->port.tty->hw_stopped = 0;
1960 info->pending_bh |= BH_TRANSMIT;
1961 return;
1962 }
1963 } else {
1964 if (!(info->signals & SerialSignal_CTS))
1965 info->port.tty->hw_stopped = 1;
1966 }
1967 }
1968 }
1969 }
1970
dcd_change(struct slgt_info * info,unsigned short status)1971 static void dcd_change(struct slgt_info *info, unsigned short status)
1972 {
1973 if (status & BIT1) {
1974 info->signals |= SerialSignal_DCD;
1975 info->input_signal_events.dcd_up++;
1976 } else {
1977 info->signals &= ~SerialSignal_DCD;
1978 info->input_signal_events.dcd_down++;
1979 }
1980 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1981 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1982 slgt_irq_off(info, IRQ_DCD);
1983 return;
1984 }
1985 info->icount.dcd++;
1986 #if SYNCLINK_GENERIC_HDLC
1987 if (info->netcount) {
1988 if (info->signals & SerialSignal_DCD)
1989 netif_carrier_on(info->netdev);
1990 else
1991 netif_carrier_off(info->netdev);
1992 }
1993 #endif
1994 wake_up_interruptible(&info->status_event_wait_q);
1995 wake_up_interruptible(&info->event_wait_q);
1996 info->pending_bh |= BH_STATUS;
1997
1998 if (tty_port_check_carrier(&info->port)) {
1999 if (info->signals & SerialSignal_DCD)
2000 wake_up_interruptible(&info->port.open_wait);
2001 else {
2002 if (info->port.tty)
2003 tty_hangup(info->port.tty);
2004 }
2005 }
2006 }
2007
ri_change(struct slgt_info * info,unsigned short status)2008 static void ri_change(struct slgt_info *info, unsigned short status)
2009 {
2010 if (status & BIT0) {
2011 info->signals |= SerialSignal_RI;
2012 info->input_signal_events.ri_up++;
2013 } else {
2014 info->signals &= ~SerialSignal_RI;
2015 info->input_signal_events.ri_down++;
2016 }
2017 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2018 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2019 slgt_irq_off(info, IRQ_RI);
2020 return;
2021 }
2022 info->icount.rng++;
2023 wake_up_interruptible(&info->status_event_wait_q);
2024 wake_up_interruptible(&info->event_wait_q);
2025 info->pending_bh |= BH_STATUS;
2026 }
2027
isr_rxdata(struct slgt_info * info)2028 static void isr_rxdata(struct slgt_info *info)
2029 {
2030 unsigned int count = info->rbuf_fill_count;
2031 unsigned int i = info->rbuf_fill_index;
2032 unsigned short reg;
2033
2034 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2035 reg = rd_reg16(info, RDR);
2036 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2037 if (desc_complete(info->rbufs[i])) {
2038 /* all buffers full */
2039 rx_stop(info);
2040 info->rx_restart = true;
2041 continue;
2042 }
2043 info->rbufs[i].buf[count++] = (unsigned char)reg;
2044 /* async mode saves status byte to buffer for each data byte */
2045 if (info->params.mode == MGSL_MODE_ASYNC)
2046 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2047 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2048 /* buffer full or end of frame */
2049 set_desc_count(info->rbufs[i], count);
2050 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2051 info->rbuf_fill_count = count = 0;
2052 if (++i == info->rbuf_count)
2053 i = 0;
2054 info->pending_bh |= BH_RECEIVE;
2055 }
2056 }
2057
2058 info->rbuf_fill_index = i;
2059 info->rbuf_fill_count = count;
2060 }
2061
isr_serial(struct slgt_info * info)2062 static void isr_serial(struct slgt_info *info)
2063 {
2064 unsigned short status = rd_reg16(info, SSR);
2065
2066 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2067
2068 wr_reg16(info, SSR, status); /* clear pending */
2069
2070 info->irq_occurred = true;
2071
2072 if (info->params.mode == MGSL_MODE_ASYNC) {
2073 if (status & IRQ_TXIDLE) {
2074 if (info->tx_active)
2075 isr_txeom(info, status);
2076 }
2077 if (info->rx_pio && (status & IRQ_RXDATA))
2078 isr_rxdata(info);
2079 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2080 info->icount.brk++;
2081 /* process break detection if tty control allows */
2082 if (info->port.tty) {
2083 if (!(status & info->ignore_status_mask)) {
2084 if (info->read_status_mask & MASK_BREAK) {
2085 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2086 if (info->port.flags & ASYNC_SAK)
2087 do_SAK(info->port.tty);
2088 }
2089 }
2090 }
2091 }
2092 } else {
2093 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2094 isr_txeom(info, status);
2095 if (info->rx_pio && (status & IRQ_RXDATA))
2096 isr_rxdata(info);
2097 if (status & IRQ_RXIDLE) {
2098 if (status & RXIDLE)
2099 info->icount.rxidle++;
2100 else
2101 info->icount.exithunt++;
2102 wake_up_interruptible(&info->event_wait_q);
2103 }
2104
2105 if (status & IRQ_RXOVER)
2106 rx_start(info);
2107 }
2108
2109 if (status & IRQ_DSR)
2110 dsr_change(info, status);
2111 if (status & IRQ_CTS)
2112 cts_change(info, status);
2113 if (status & IRQ_DCD)
2114 dcd_change(info, status);
2115 if (status & IRQ_RI)
2116 ri_change(info, status);
2117 }
2118
isr_rdma(struct slgt_info * info)2119 static void isr_rdma(struct slgt_info *info)
2120 {
2121 unsigned int status = rd_reg32(info, RDCSR);
2122
2123 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2124
2125 /* RDCSR (rx DMA control/status)
2126 *
2127 * 31..07 reserved
2128 * 06 save status byte to DMA buffer
2129 * 05 error
2130 * 04 eol (end of list)
2131 * 03 eob (end of buffer)
2132 * 02 IRQ enable
2133 * 01 reset
2134 * 00 enable
2135 */
2136 wr_reg32(info, RDCSR, status); /* clear pending */
2137
2138 if (status & (BIT5 + BIT4)) {
2139 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2140 info->rx_restart = true;
2141 }
2142 info->pending_bh |= BH_RECEIVE;
2143 }
2144
isr_tdma(struct slgt_info * info)2145 static void isr_tdma(struct slgt_info *info)
2146 {
2147 unsigned int status = rd_reg32(info, TDCSR);
2148
2149 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2150
2151 /* TDCSR (tx DMA control/status)
2152 *
2153 * 31..06 reserved
2154 * 05 error
2155 * 04 eol (end of list)
2156 * 03 eob (end of buffer)
2157 * 02 IRQ enable
2158 * 01 reset
2159 * 00 enable
2160 */
2161 wr_reg32(info, TDCSR, status); /* clear pending */
2162
2163 if (status & (BIT5 + BIT4 + BIT3)) {
2164 // another transmit buffer has completed
2165 // run bottom half to get more send data from user
2166 info->pending_bh |= BH_TRANSMIT;
2167 }
2168 }
2169
2170 /*
2171 * return true if there are unsent tx DMA buffers, otherwise false
2172 *
2173 * if there are unsent buffers then info->tbuf_start
2174 * is set to index of first unsent buffer
2175 */
unsent_tbufs(struct slgt_info * info)2176 static bool unsent_tbufs(struct slgt_info *info)
2177 {
2178 unsigned int i = info->tbuf_current;
2179 bool rc = false;
2180
2181 /*
2182 * search backwards from last loaded buffer (precedes tbuf_current)
2183 * for first unsent buffer (desc_count > 0)
2184 */
2185
2186 do {
2187 if (i)
2188 i--;
2189 else
2190 i = info->tbuf_count - 1;
2191 if (!desc_count(info->tbufs[i]))
2192 break;
2193 info->tbuf_start = i;
2194 rc = true;
2195 } while (i != info->tbuf_current);
2196
2197 return rc;
2198 }
2199
isr_txeom(struct slgt_info * info,unsigned short status)2200 static void isr_txeom(struct slgt_info *info, unsigned short status)
2201 {
2202 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2203
2204 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2205 tdma_reset(info);
2206 if (status & IRQ_TXUNDER) {
2207 unsigned short val = rd_reg16(info, TCR);
2208 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2209 wr_reg16(info, TCR, val); /* clear reset bit */
2210 }
2211
2212 if (info->tx_active) {
2213 if (info->params.mode != MGSL_MODE_ASYNC) {
2214 if (status & IRQ_TXUNDER)
2215 info->icount.txunder++;
2216 else if (status & IRQ_TXIDLE)
2217 info->icount.txok++;
2218 }
2219
2220 if (unsent_tbufs(info)) {
2221 tx_start(info);
2222 update_tx_timer(info);
2223 return;
2224 }
2225 info->tx_active = false;
2226
2227 del_timer(&info->tx_timer);
2228
2229 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2230 info->signals &= ~SerialSignal_RTS;
2231 info->drop_rts_on_tx_done = false;
2232 set_gtsignals(info);
2233 }
2234
2235 #if SYNCLINK_GENERIC_HDLC
2236 if (info->netcount)
2237 hdlcdev_tx_done(info);
2238 else
2239 #endif
2240 {
2241 if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
2242 tx_stop(info);
2243 return;
2244 }
2245 info->pending_bh |= BH_TRANSMIT;
2246 }
2247 }
2248 }
2249
isr_gpio(struct slgt_info * info,unsigned int changed,unsigned int state)2250 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2251 {
2252 struct cond_wait *w, *prev;
2253
2254 /* wake processes waiting for specific transitions */
2255 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2256 if (w->data & changed) {
2257 w->data = state;
2258 wake_up_interruptible(&w->q);
2259 if (prev != NULL)
2260 prev->next = w->next;
2261 else
2262 info->gpio_wait_q = w->next;
2263 } else
2264 prev = w;
2265 }
2266 }
2267
2268 /* interrupt service routine
2269 *
2270 * irq interrupt number
2271 * dev_id device ID supplied during interrupt registration
2272 */
slgt_interrupt(int dummy,void * dev_id)2273 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2274 {
2275 struct slgt_info *info = dev_id;
2276 unsigned int gsr;
2277 unsigned int i;
2278
2279 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2280
2281 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2282 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2283 info->irq_occurred = true;
2284 for(i=0; i < info->port_count ; i++) {
2285 if (info->port_array[i] == NULL)
2286 continue;
2287 spin_lock(&info->port_array[i]->lock);
2288 if (gsr & (BIT8 << i))
2289 isr_serial(info->port_array[i]);
2290 if (gsr & (BIT16 << (i*2)))
2291 isr_rdma(info->port_array[i]);
2292 if (gsr & (BIT17 << (i*2)))
2293 isr_tdma(info->port_array[i]);
2294 spin_unlock(&info->port_array[i]->lock);
2295 }
2296 }
2297
2298 if (info->gpio_present) {
2299 unsigned int state;
2300 unsigned int changed;
2301 spin_lock(&info->lock);
2302 while ((changed = rd_reg32(info, IOSR)) != 0) {
2303 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2304 /* read latched state of GPIO signals */
2305 state = rd_reg32(info, IOVR);
2306 /* clear pending GPIO interrupt bits */
2307 wr_reg32(info, IOSR, changed);
2308 for (i=0 ; i < info->port_count ; i++) {
2309 if (info->port_array[i] != NULL)
2310 isr_gpio(info->port_array[i], changed, state);
2311 }
2312 }
2313 spin_unlock(&info->lock);
2314 }
2315
2316 for(i=0; i < info->port_count ; i++) {
2317 struct slgt_info *port = info->port_array[i];
2318 if (port == NULL)
2319 continue;
2320 spin_lock(&port->lock);
2321 if ((port->port.count || port->netcount) &&
2322 port->pending_bh && !port->bh_running &&
2323 !port->bh_requested) {
2324 DBGISR(("%s bh queued\n", port->device_name));
2325 schedule_work(&port->task);
2326 port->bh_requested = true;
2327 }
2328 spin_unlock(&port->lock);
2329 }
2330
2331 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2332 return IRQ_HANDLED;
2333 }
2334
startup(struct slgt_info * info)2335 static int startup(struct slgt_info *info)
2336 {
2337 DBGINFO(("%s startup\n", info->device_name));
2338
2339 if (tty_port_initialized(&info->port))
2340 return 0;
2341
2342 if (!info->tx_buf) {
2343 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2344 if (!info->tx_buf) {
2345 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2346 return -ENOMEM;
2347 }
2348 }
2349
2350 info->pending_bh = 0;
2351
2352 memset(&info->icount, 0, sizeof(info->icount));
2353
2354 /* program hardware for current parameters */
2355 change_params(info);
2356
2357 if (info->port.tty)
2358 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2359
2360 tty_port_set_initialized(&info->port, 1);
2361
2362 return 0;
2363 }
2364
2365 /*
2366 * called by close() and hangup() to shutdown hardware
2367 */
shutdown(struct slgt_info * info)2368 static void shutdown(struct slgt_info *info)
2369 {
2370 unsigned long flags;
2371
2372 if (!tty_port_initialized(&info->port))
2373 return;
2374
2375 DBGINFO(("%s shutdown\n", info->device_name));
2376
2377 /* clear status wait queue because status changes */
2378 /* can't happen after shutting down the hardware */
2379 wake_up_interruptible(&info->status_event_wait_q);
2380 wake_up_interruptible(&info->event_wait_q);
2381
2382 del_timer_sync(&info->tx_timer);
2383 del_timer_sync(&info->rx_timer);
2384
2385 kfree(info->tx_buf);
2386 info->tx_buf = NULL;
2387
2388 spin_lock_irqsave(&info->lock,flags);
2389
2390 tx_stop(info);
2391 rx_stop(info);
2392
2393 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2394
2395 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2396 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2397 set_gtsignals(info);
2398 }
2399
2400 flush_cond_wait(&info->gpio_wait_q);
2401
2402 spin_unlock_irqrestore(&info->lock,flags);
2403
2404 if (info->port.tty)
2405 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2406
2407 tty_port_set_initialized(&info->port, 0);
2408 }
2409
program_hw(struct slgt_info * info)2410 static void program_hw(struct slgt_info *info)
2411 {
2412 unsigned long flags;
2413
2414 spin_lock_irqsave(&info->lock,flags);
2415
2416 rx_stop(info);
2417 tx_stop(info);
2418
2419 if (info->params.mode != MGSL_MODE_ASYNC ||
2420 info->netcount)
2421 sync_mode(info);
2422 else
2423 async_mode(info);
2424
2425 set_gtsignals(info);
2426
2427 info->dcd_chkcount = 0;
2428 info->cts_chkcount = 0;
2429 info->ri_chkcount = 0;
2430 info->dsr_chkcount = 0;
2431
2432 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2433 get_gtsignals(info);
2434
2435 if (info->netcount ||
2436 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2437 rx_start(info);
2438
2439 spin_unlock_irqrestore(&info->lock,flags);
2440 }
2441
2442 /*
2443 * reconfigure adapter based on new parameters
2444 */
change_params(struct slgt_info * info)2445 static void change_params(struct slgt_info *info)
2446 {
2447 unsigned cflag;
2448 int bits_per_char;
2449
2450 if (!info->port.tty)
2451 return;
2452 DBGINFO(("%s change_params\n", info->device_name));
2453
2454 cflag = info->port.tty->termios.c_cflag;
2455
2456 /* if B0 rate (hangup) specified then negate RTS and DTR */
2457 /* otherwise assert RTS and DTR */
2458 if (cflag & CBAUD)
2459 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2460 else
2461 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2462
2463 /* byte size and parity */
2464
2465 info->params.data_bits = tty_get_char_size(cflag);
2466 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2467
2468 if (cflag & PARENB)
2469 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2470 else
2471 info->params.parity = ASYNC_PARITY_NONE;
2472
2473 /* calculate number of jiffies to transmit a full
2474 * FIFO (32 bytes) at specified data rate
2475 */
2476 bits_per_char = info->params.data_bits +
2477 info->params.stop_bits + 1;
2478
2479 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2480
2481 if (info->params.data_rate) {
2482 info->timeout = (32*HZ*bits_per_char) /
2483 info->params.data_rate;
2484 }
2485 info->timeout += HZ/50; /* Add .02 seconds of slop */
2486
2487 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2488 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2489
2490 /* process tty input control flags */
2491
2492 info->read_status_mask = IRQ_RXOVER;
2493 if (I_INPCK(info->port.tty))
2494 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2495 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2496 info->read_status_mask |= MASK_BREAK;
2497 if (I_IGNPAR(info->port.tty))
2498 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2499 if (I_IGNBRK(info->port.tty)) {
2500 info->ignore_status_mask |= MASK_BREAK;
2501 /* If ignoring parity and break indicators, ignore
2502 * overruns too. (For real raw support).
2503 */
2504 if (I_IGNPAR(info->port.tty))
2505 info->ignore_status_mask |= MASK_OVERRUN;
2506 }
2507
2508 program_hw(info);
2509 }
2510
get_stats(struct slgt_info * info,struct mgsl_icount __user * user_icount)2511 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2512 {
2513 DBGINFO(("%s get_stats\n", info->device_name));
2514 if (!user_icount) {
2515 memset(&info->icount, 0, sizeof(info->icount));
2516 } else {
2517 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2518 return -EFAULT;
2519 }
2520 return 0;
2521 }
2522
get_params(struct slgt_info * info,MGSL_PARAMS __user * user_params)2523 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2524 {
2525 DBGINFO(("%s get_params\n", info->device_name));
2526 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2527 return -EFAULT;
2528 return 0;
2529 }
2530
set_params(struct slgt_info * info,MGSL_PARAMS __user * new_params)2531 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2532 {
2533 unsigned long flags;
2534 MGSL_PARAMS tmp_params;
2535
2536 DBGINFO(("%s set_params\n", info->device_name));
2537 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2538 return -EFAULT;
2539
2540 spin_lock_irqsave(&info->lock, flags);
2541 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2542 info->base_clock = tmp_params.clock_speed;
2543 else
2544 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2545 spin_unlock_irqrestore(&info->lock, flags);
2546
2547 program_hw(info);
2548
2549 return 0;
2550 }
2551
get_txidle(struct slgt_info * info,int __user * idle_mode)2552 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2553 {
2554 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2555 if (put_user(info->idle_mode, idle_mode))
2556 return -EFAULT;
2557 return 0;
2558 }
2559
set_txidle(struct slgt_info * info,int idle_mode)2560 static int set_txidle(struct slgt_info *info, int idle_mode)
2561 {
2562 unsigned long flags;
2563 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2564 spin_lock_irqsave(&info->lock,flags);
2565 info->idle_mode = idle_mode;
2566 if (info->params.mode != MGSL_MODE_ASYNC)
2567 tx_set_idle(info);
2568 spin_unlock_irqrestore(&info->lock,flags);
2569 return 0;
2570 }
2571
tx_enable(struct slgt_info * info,int enable)2572 static int tx_enable(struct slgt_info *info, int enable)
2573 {
2574 unsigned long flags;
2575 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2576 spin_lock_irqsave(&info->lock,flags);
2577 if (enable) {
2578 if (!info->tx_enabled)
2579 tx_start(info);
2580 } else {
2581 if (info->tx_enabled)
2582 tx_stop(info);
2583 }
2584 spin_unlock_irqrestore(&info->lock,flags);
2585 return 0;
2586 }
2587
2588 /*
2589 * abort transmit HDLC frame
2590 */
tx_abort(struct slgt_info * info)2591 static int tx_abort(struct slgt_info *info)
2592 {
2593 unsigned long flags;
2594 DBGINFO(("%s tx_abort\n", info->device_name));
2595 spin_lock_irqsave(&info->lock,flags);
2596 tdma_reset(info);
2597 spin_unlock_irqrestore(&info->lock,flags);
2598 return 0;
2599 }
2600
rx_enable(struct slgt_info * info,int enable)2601 static int rx_enable(struct slgt_info *info, int enable)
2602 {
2603 unsigned long flags;
2604 unsigned int rbuf_fill_level;
2605 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2606 spin_lock_irqsave(&info->lock,flags);
2607 /*
2608 * enable[31..16] = receive DMA buffer fill level
2609 * 0 = noop (leave fill level unchanged)
2610 * fill level must be multiple of 4 and <= buffer size
2611 */
2612 rbuf_fill_level = ((unsigned int)enable) >> 16;
2613 if (rbuf_fill_level) {
2614 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2615 spin_unlock_irqrestore(&info->lock, flags);
2616 return -EINVAL;
2617 }
2618 info->rbuf_fill_level = rbuf_fill_level;
2619 if (rbuf_fill_level < 128)
2620 info->rx_pio = 1; /* PIO mode */
2621 else
2622 info->rx_pio = 0; /* DMA mode */
2623 rx_stop(info); /* restart receiver to use new fill level */
2624 }
2625
2626 /*
2627 * enable[1..0] = receiver enable command
2628 * 0 = disable
2629 * 1 = enable
2630 * 2 = enable or force hunt mode if already enabled
2631 */
2632 enable &= 3;
2633 if (enable) {
2634 if (!info->rx_enabled)
2635 rx_start(info);
2636 else if (enable == 2) {
2637 /* force hunt mode (write 1 to RCR[3]) */
2638 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2639 }
2640 } else {
2641 if (info->rx_enabled)
2642 rx_stop(info);
2643 }
2644 spin_unlock_irqrestore(&info->lock,flags);
2645 return 0;
2646 }
2647
2648 /*
2649 * wait for specified event to occur
2650 */
wait_mgsl_event(struct slgt_info * info,int __user * mask_ptr)2651 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2652 {
2653 unsigned long flags;
2654 int s;
2655 int rc=0;
2656 struct mgsl_icount cprev, cnow;
2657 int events;
2658 int mask;
2659 struct _input_signal_events oldsigs, newsigs;
2660 DECLARE_WAITQUEUE(wait, current);
2661
2662 if (get_user(mask, mask_ptr))
2663 return -EFAULT;
2664
2665 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2666
2667 spin_lock_irqsave(&info->lock,flags);
2668
2669 /* return immediately if state matches requested events */
2670 get_gtsignals(info);
2671 s = info->signals;
2672
2673 events = mask &
2674 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2675 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2676 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2677 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2678 if (events) {
2679 spin_unlock_irqrestore(&info->lock,flags);
2680 goto exit;
2681 }
2682
2683 /* save current irq counts */
2684 cprev = info->icount;
2685 oldsigs = info->input_signal_events;
2686
2687 /* enable hunt and idle irqs if needed */
2688 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2689 unsigned short val = rd_reg16(info, SCR);
2690 if (!(val & IRQ_RXIDLE))
2691 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2692 }
2693
2694 set_current_state(TASK_INTERRUPTIBLE);
2695 add_wait_queue(&info->event_wait_q, &wait);
2696
2697 spin_unlock_irqrestore(&info->lock,flags);
2698
2699 for(;;) {
2700 schedule();
2701 if (signal_pending(current)) {
2702 rc = -ERESTARTSYS;
2703 break;
2704 }
2705
2706 /* get current irq counts */
2707 spin_lock_irqsave(&info->lock,flags);
2708 cnow = info->icount;
2709 newsigs = info->input_signal_events;
2710 set_current_state(TASK_INTERRUPTIBLE);
2711 spin_unlock_irqrestore(&info->lock,flags);
2712
2713 /* if no change, wait aborted for some reason */
2714 if (newsigs.dsr_up == oldsigs.dsr_up &&
2715 newsigs.dsr_down == oldsigs.dsr_down &&
2716 newsigs.dcd_up == oldsigs.dcd_up &&
2717 newsigs.dcd_down == oldsigs.dcd_down &&
2718 newsigs.cts_up == oldsigs.cts_up &&
2719 newsigs.cts_down == oldsigs.cts_down &&
2720 newsigs.ri_up == oldsigs.ri_up &&
2721 newsigs.ri_down == oldsigs.ri_down &&
2722 cnow.exithunt == cprev.exithunt &&
2723 cnow.rxidle == cprev.rxidle) {
2724 rc = -EIO;
2725 break;
2726 }
2727
2728 events = mask &
2729 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2730 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2731 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2732 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2733 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2734 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2735 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2736 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2737 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2738 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2739 if (events)
2740 break;
2741
2742 cprev = cnow;
2743 oldsigs = newsigs;
2744 }
2745
2746 remove_wait_queue(&info->event_wait_q, &wait);
2747 set_current_state(TASK_RUNNING);
2748
2749
2750 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2751 spin_lock_irqsave(&info->lock,flags);
2752 if (!waitqueue_active(&info->event_wait_q)) {
2753 /* disable enable exit hunt mode/idle rcvd IRQs */
2754 wr_reg16(info, SCR,
2755 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2756 }
2757 spin_unlock_irqrestore(&info->lock,flags);
2758 }
2759 exit:
2760 if (rc == 0)
2761 rc = put_user(events, mask_ptr);
2762 return rc;
2763 }
2764
get_interface(struct slgt_info * info,int __user * if_mode)2765 static int get_interface(struct slgt_info *info, int __user *if_mode)
2766 {
2767 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2768 if (put_user(info->if_mode, if_mode))
2769 return -EFAULT;
2770 return 0;
2771 }
2772
set_interface(struct slgt_info * info,int if_mode)2773 static int set_interface(struct slgt_info *info, int if_mode)
2774 {
2775 unsigned long flags;
2776 unsigned short val;
2777
2778 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2779 spin_lock_irqsave(&info->lock,flags);
2780 info->if_mode = if_mode;
2781
2782 msc_set_vcr(info);
2783
2784 /* TCR (tx control) 07 1=RTS driver control */
2785 val = rd_reg16(info, TCR);
2786 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2787 val |= BIT7;
2788 else
2789 val &= ~BIT7;
2790 wr_reg16(info, TCR, val);
2791
2792 spin_unlock_irqrestore(&info->lock,flags);
2793 return 0;
2794 }
2795
get_xsync(struct slgt_info * info,int __user * xsync)2796 static int get_xsync(struct slgt_info *info, int __user *xsync)
2797 {
2798 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2799 if (put_user(info->xsync, xsync))
2800 return -EFAULT;
2801 return 0;
2802 }
2803
2804 /*
2805 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2806 *
2807 * sync pattern is contained in least significant bytes of value
2808 * most significant byte of sync pattern is oldest (1st sent/detected)
2809 */
set_xsync(struct slgt_info * info,int xsync)2810 static int set_xsync(struct slgt_info *info, int xsync)
2811 {
2812 unsigned long flags;
2813
2814 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2815 spin_lock_irqsave(&info->lock, flags);
2816 info->xsync = xsync;
2817 wr_reg32(info, XSR, xsync);
2818 spin_unlock_irqrestore(&info->lock, flags);
2819 return 0;
2820 }
2821
get_xctrl(struct slgt_info * info,int __user * xctrl)2822 static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2823 {
2824 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2825 if (put_user(info->xctrl, xctrl))
2826 return -EFAULT;
2827 return 0;
2828 }
2829
2830 /*
2831 * set extended control options
2832 *
2833 * xctrl[31:19] reserved, must be zero
2834 * xctrl[18:17] extended sync pattern length in bytes
2835 * 00 = 1 byte in xsr[7:0]
2836 * 01 = 2 bytes in xsr[15:0]
2837 * 10 = 3 bytes in xsr[23:0]
2838 * 11 = 4 bytes in xsr[31:0]
2839 * xctrl[16] 1 = enable terminal count, 0=disabled
2840 * xctrl[15:0] receive terminal count for fixed length packets
2841 * value is count minus one (0 = 1 byte packet)
2842 * when terminal count is reached, receiver
2843 * automatically returns to hunt mode and receive
2844 * FIFO contents are flushed to DMA buffers with
2845 * end of frame (EOF) status
2846 */
set_xctrl(struct slgt_info * info,int xctrl)2847 static int set_xctrl(struct slgt_info *info, int xctrl)
2848 {
2849 unsigned long flags;
2850
2851 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2852 spin_lock_irqsave(&info->lock, flags);
2853 info->xctrl = xctrl;
2854 wr_reg32(info, XCR, xctrl);
2855 spin_unlock_irqrestore(&info->lock, flags);
2856 return 0;
2857 }
2858
2859 /*
2860 * set general purpose IO pin state and direction
2861 *
2862 * user_gpio fields:
2863 * state each bit indicates a pin state
2864 * smask set bit indicates pin state to set
2865 * dir each bit indicates a pin direction (0=input, 1=output)
2866 * dmask set bit indicates pin direction to set
2867 */
set_gpio(struct slgt_info * info,struct gpio_desc __user * user_gpio)2868 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2869 {
2870 unsigned long flags;
2871 struct gpio_desc gpio;
2872 __u32 data;
2873
2874 if (!info->gpio_present)
2875 return -EINVAL;
2876 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2877 return -EFAULT;
2878 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2879 info->device_name, gpio.state, gpio.smask,
2880 gpio.dir, gpio.dmask));
2881
2882 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2883 if (gpio.dmask) {
2884 data = rd_reg32(info, IODR);
2885 data |= gpio.dmask & gpio.dir;
2886 data &= ~(gpio.dmask & ~gpio.dir);
2887 wr_reg32(info, IODR, data);
2888 }
2889 if (gpio.smask) {
2890 data = rd_reg32(info, IOVR);
2891 data |= gpio.smask & gpio.state;
2892 data &= ~(gpio.smask & ~gpio.state);
2893 wr_reg32(info, IOVR, data);
2894 }
2895 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2896
2897 return 0;
2898 }
2899
2900 /*
2901 * get general purpose IO pin state and direction
2902 */
get_gpio(struct slgt_info * info,struct gpio_desc __user * user_gpio)2903 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2904 {
2905 struct gpio_desc gpio;
2906 if (!info->gpio_present)
2907 return -EINVAL;
2908 gpio.state = rd_reg32(info, IOVR);
2909 gpio.smask = 0xffffffff;
2910 gpio.dir = rd_reg32(info, IODR);
2911 gpio.dmask = 0xffffffff;
2912 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2913 return -EFAULT;
2914 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2915 info->device_name, gpio.state, gpio.dir));
2916 return 0;
2917 }
2918
2919 /*
2920 * conditional wait facility
2921 */
init_cond_wait(struct cond_wait * w,unsigned int data)2922 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2923 {
2924 init_waitqueue_head(&w->q);
2925 init_waitqueue_entry(&w->wait, current);
2926 w->data = data;
2927 }
2928
add_cond_wait(struct cond_wait ** head,struct cond_wait * w)2929 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2930 {
2931 set_current_state(TASK_INTERRUPTIBLE);
2932 add_wait_queue(&w->q, &w->wait);
2933 w->next = *head;
2934 *head = w;
2935 }
2936
remove_cond_wait(struct cond_wait ** head,struct cond_wait * cw)2937 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2938 {
2939 struct cond_wait *w, *prev;
2940 remove_wait_queue(&cw->q, &cw->wait);
2941 set_current_state(TASK_RUNNING);
2942 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2943 if (w == cw) {
2944 if (prev != NULL)
2945 prev->next = w->next;
2946 else
2947 *head = w->next;
2948 break;
2949 }
2950 }
2951 }
2952
flush_cond_wait(struct cond_wait ** head)2953 static void flush_cond_wait(struct cond_wait **head)
2954 {
2955 while (*head != NULL) {
2956 wake_up_interruptible(&(*head)->q);
2957 *head = (*head)->next;
2958 }
2959 }
2960
2961 /*
2962 * wait for general purpose I/O pin(s) to enter specified state
2963 *
2964 * user_gpio fields:
2965 * state - bit indicates target pin state
2966 * smask - set bit indicates watched pin
2967 *
2968 * The wait ends when at least one watched pin enters the specified
2969 * state. When 0 (no error) is returned, user_gpio->state is set to the
2970 * state of all GPIO pins when the wait ends.
2971 *
2972 * Note: Each pin may be a dedicated input, dedicated output, or
2973 * configurable input/output. The number and configuration of pins
2974 * varies with the specific adapter model. Only input pins (dedicated
2975 * or configured) can be monitored with this function.
2976 */
wait_gpio(struct slgt_info * info,struct gpio_desc __user * user_gpio)2977 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2978 {
2979 unsigned long flags;
2980 int rc = 0;
2981 struct gpio_desc gpio;
2982 struct cond_wait wait;
2983 u32 state;
2984
2985 if (!info->gpio_present)
2986 return -EINVAL;
2987 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2988 return -EFAULT;
2989 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2990 info->device_name, gpio.state, gpio.smask));
2991 /* ignore output pins identified by set IODR bit */
2992 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2993 return -EINVAL;
2994 init_cond_wait(&wait, gpio.smask);
2995
2996 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2997 /* enable interrupts for watched pins */
2998 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2999 /* get current pin states */
3000 state = rd_reg32(info, IOVR);
3001
3002 if (gpio.smask & ~(state ^ gpio.state)) {
3003 /* already in target state */
3004 gpio.state = state;
3005 } else {
3006 /* wait for target state */
3007 add_cond_wait(&info->gpio_wait_q, &wait);
3008 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3009 schedule();
3010 if (signal_pending(current))
3011 rc = -ERESTARTSYS;
3012 else
3013 gpio.state = wait.data;
3014 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3015 remove_cond_wait(&info->gpio_wait_q, &wait);
3016 }
3017
3018 /* disable all GPIO interrupts if no waiting processes */
3019 if (info->gpio_wait_q == NULL)
3020 wr_reg32(info, IOER, 0);
3021 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3022
3023 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3024 rc = -EFAULT;
3025 return rc;
3026 }
3027
modem_input_wait(struct slgt_info * info,int arg)3028 static int modem_input_wait(struct slgt_info *info,int arg)
3029 {
3030 unsigned long flags;
3031 int rc;
3032 struct mgsl_icount cprev, cnow;
3033 DECLARE_WAITQUEUE(wait, current);
3034
3035 /* save current irq counts */
3036 spin_lock_irqsave(&info->lock,flags);
3037 cprev = info->icount;
3038 add_wait_queue(&info->status_event_wait_q, &wait);
3039 set_current_state(TASK_INTERRUPTIBLE);
3040 spin_unlock_irqrestore(&info->lock,flags);
3041
3042 for(;;) {
3043 schedule();
3044 if (signal_pending(current)) {
3045 rc = -ERESTARTSYS;
3046 break;
3047 }
3048
3049 /* get new irq counts */
3050 spin_lock_irqsave(&info->lock,flags);
3051 cnow = info->icount;
3052 set_current_state(TASK_INTERRUPTIBLE);
3053 spin_unlock_irqrestore(&info->lock,flags);
3054
3055 /* if no change, wait aborted for some reason */
3056 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3057 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3058 rc = -EIO;
3059 break;
3060 }
3061
3062 /* check for change in caller specified modem input */
3063 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3064 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3065 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3066 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3067 rc = 0;
3068 break;
3069 }
3070
3071 cprev = cnow;
3072 }
3073 remove_wait_queue(&info->status_event_wait_q, &wait);
3074 set_current_state(TASK_RUNNING);
3075 return rc;
3076 }
3077
3078 /*
3079 * return state of serial control and status signals
3080 */
tiocmget(struct tty_struct * tty)3081 static int tiocmget(struct tty_struct *tty)
3082 {
3083 struct slgt_info *info = tty->driver_data;
3084 unsigned int result;
3085 unsigned long flags;
3086
3087 spin_lock_irqsave(&info->lock,flags);
3088 get_gtsignals(info);
3089 spin_unlock_irqrestore(&info->lock,flags);
3090
3091 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3092 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3093 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3094 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3095 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3096 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3097
3098 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3099 return result;
3100 }
3101
3102 /*
3103 * set modem control signals (DTR/RTS)
3104 *
3105 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3106 * TIOCMSET = set/clear signal values
3107 * value bit mask for command
3108 */
tiocmset(struct tty_struct * tty,unsigned int set,unsigned int clear)3109 static int tiocmset(struct tty_struct *tty,
3110 unsigned int set, unsigned int clear)
3111 {
3112 struct slgt_info *info = tty->driver_data;
3113 unsigned long flags;
3114
3115 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3116
3117 if (set & TIOCM_RTS)
3118 info->signals |= SerialSignal_RTS;
3119 if (set & TIOCM_DTR)
3120 info->signals |= SerialSignal_DTR;
3121 if (clear & TIOCM_RTS)
3122 info->signals &= ~SerialSignal_RTS;
3123 if (clear & TIOCM_DTR)
3124 info->signals &= ~SerialSignal_DTR;
3125
3126 spin_lock_irqsave(&info->lock,flags);
3127 set_gtsignals(info);
3128 spin_unlock_irqrestore(&info->lock,flags);
3129 return 0;
3130 }
3131
carrier_raised(struct tty_port * port)3132 static int carrier_raised(struct tty_port *port)
3133 {
3134 unsigned long flags;
3135 struct slgt_info *info = container_of(port, struct slgt_info, port);
3136
3137 spin_lock_irqsave(&info->lock,flags);
3138 get_gtsignals(info);
3139 spin_unlock_irqrestore(&info->lock,flags);
3140 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3141 }
3142
dtr_rts(struct tty_port * port,int on)3143 static void dtr_rts(struct tty_port *port, int on)
3144 {
3145 unsigned long flags;
3146 struct slgt_info *info = container_of(port, struct slgt_info, port);
3147
3148 spin_lock_irqsave(&info->lock,flags);
3149 if (on)
3150 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3151 else
3152 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3153 set_gtsignals(info);
3154 spin_unlock_irqrestore(&info->lock,flags);
3155 }
3156
3157
3158 /*
3159 * block current process until the device is ready to open
3160 */
block_til_ready(struct tty_struct * tty,struct file * filp,struct slgt_info * info)3161 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3162 struct slgt_info *info)
3163 {
3164 DECLARE_WAITQUEUE(wait, current);
3165 int retval;
3166 bool do_clocal = false;
3167 unsigned long flags;
3168 int cd;
3169 struct tty_port *port = &info->port;
3170
3171 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3172
3173 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3174 /* nonblock mode is set or port is not enabled */
3175 tty_port_set_active(port, 1);
3176 return 0;
3177 }
3178
3179 if (C_CLOCAL(tty))
3180 do_clocal = true;
3181
3182 /* Wait for carrier detect and the line to become
3183 * free (i.e., not in use by the callout). While we are in
3184 * this loop, port->count is dropped by one, so that
3185 * close() knows when to free things. We restore it upon
3186 * exit, either normal or abnormal.
3187 */
3188
3189 retval = 0;
3190 add_wait_queue(&port->open_wait, &wait);
3191
3192 spin_lock_irqsave(&info->lock, flags);
3193 port->count--;
3194 spin_unlock_irqrestore(&info->lock, flags);
3195 port->blocked_open++;
3196
3197 while (1) {
3198 if (C_BAUD(tty) && tty_port_initialized(port))
3199 tty_port_raise_dtr_rts(port);
3200
3201 set_current_state(TASK_INTERRUPTIBLE);
3202
3203 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3204 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3205 -EAGAIN : -ERESTARTSYS;
3206 break;
3207 }
3208
3209 cd = tty_port_carrier_raised(port);
3210 if (do_clocal || cd)
3211 break;
3212
3213 if (signal_pending(current)) {
3214 retval = -ERESTARTSYS;
3215 break;
3216 }
3217
3218 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3219 tty_unlock(tty);
3220 schedule();
3221 tty_lock(tty);
3222 }
3223
3224 set_current_state(TASK_RUNNING);
3225 remove_wait_queue(&port->open_wait, &wait);
3226
3227 if (!tty_hung_up_p(filp))
3228 port->count++;
3229 port->blocked_open--;
3230
3231 if (!retval)
3232 tty_port_set_active(port, 1);
3233
3234 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3235 return retval;
3236 }
3237
3238 /*
3239 * allocate buffers used for calling line discipline receive_buf
3240 * directly in synchronous mode
3241 * note: add 5 bytes to max frame size to allow appending
3242 * 32-bit CRC and status byte when configured to do so
3243 */
alloc_tmp_rbuf(struct slgt_info * info)3244 static int alloc_tmp_rbuf(struct slgt_info *info)
3245 {
3246 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3247 if (info->tmp_rbuf == NULL)
3248 return -ENOMEM;
3249 /* unused flag buffer to satisfy receive_buf calling interface */
3250 info->flag_buf = kzalloc(info->max_frame_size + 5, GFP_KERNEL);
3251 if (!info->flag_buf) {
3252 kfree(info->tmp_rbuf);
3253 info->tmp_rbuf = NULL;
3254 return -ENOMEM;
3255 }
3256 return 0;
3257 }
3258
free_tmp_rbuf(struct slgt_info * info)3259 static void free_tmp_rbuf(struct slgt_info *info)
3260 {
3261 kfree(info->tmp_rbuf);
3262 info->tmp_rbuf = NULL;
3263 kfree(info->flag_buf);
3264 info->flag_buf = NULL;
3265 }
3266
3267 /*
3268 * allocate DMA descriptor lists.
3269 */
alloc_desc(struct slgt_info * info)3270 static int alloc_desc(struct slgt_info *info)
3271 {
3272 unsigned int i;
3273 unsigned int pbufs;
3274
3275 /* allocate memory to hold descriptor lists */
3276 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3277 &info->bufs_dma_addr, GFP_KERNEL);
3278 if (info->bufs == NULL)
3279 return -ENOMEM;
3280
3281 info->rbufs = (struct slgt_desc*)info->bufs;
3282 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3283
3284 pbufs = (unsigned int)info->bufs_dma_addr;
3285
3286 /*
3287 * Build circular lists of descriptors
3288 */
3289
3290 for (i=0; i < info->rbuf_count; i++) {
3291 /* physical address of this descriptor */
3292 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3293
3294 /* physical address of next descriptor */
3295 if (i == info->rbuf_count - 1)
3296 info->rbufs[i].next = cpu_to_le32(pbufs);
3297 else
3298 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3299 set_desc_count(info->rbufs[i], DMABUFSIZE);
3300 }
3301
3302 for (i=0; i < info->tbuf_count; i++) {
3303 /* physical address of this descriptor */
3304 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3305
3306 /* physical address of next descriptor */
3307 if (i == info->tbuf_count - 1)
3308 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3309 else
3310 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3311 }
3312
3313 return 0;
3314 }
3315
free_desc(struct slgt_info * info)3316 static void free_desc(struct slgt_info *info)
3317 {
3318 if (info->bufs != NULL) {
3319 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3320 info->bufs, info->bufs_dma_addr);
3321 info->bufs = NULL;
3322 info->rbufs = NULL;
3323 info->tbufs = NULL;
3324 }
3325 }
3326
alloc_bufs(struct slgt_info * info,struct slgt_desc * bufs,int count)3327 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3328 {
3329 int i;
3330 for (i=0; i < count; i++) {
3331 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3332 &bufs[i].buf_dma_addr, GFP_KERNEL);
3333 if (!bufs[i].buf)
3334 return -ENOMEM;
3335 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3336 }
3337 return 0;
3338 }
3339
free_bufs(struct slgt_info * info,struct slgt_desc * bufs,int count)3340 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3341 {
3342 int i;
3343 for (i=0; i < count; i++) {
3344 if (bufs[i].buf == NULL)
3345 continue;
3346 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3347 bufs[i].buf_dma_addr);
3348 bufs[i].buf = NULL;
3349 }
3350 }
3351
alloc_dma_bufs(struct slgt_info * info)3352 static int alloc_dma_bufs(struct slgt_info *info)
3353 {
3354 info->rbuf_count = 32;
3355 info->tbuf_count = 32;
3356
3357 if (alloc_desc(info) < 0 ||
3358 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3359 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3360 alloc_tmp_rbuf(info) < 0) {
3361 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3362 return -ENOMEM;
3363 }
3364 reset_rbufs(info);
3365 return 0;
3366 }
3367
free_dma_bufs(struct slgt_info * info)3368 static void free_dma_bufs(struct slgt_info *info)
3369 {
3370 if (info->bufs) {
3371 free_bufs(info, info->rbufs, info->rbuf_count);
3372 free_bufs(info, info->tbufs, info->tbuf_count);
3373 free_desc(info);
3374 }
3375 free_tmp_rbuf(info);
3376 }
3377
claim_resources(struct slgt_info * info)3378 static int claim_resources(struct slgt_info *info)
3379 {
3380 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3381 DBGERR(("%s reg addr conflict, addr=%08X\n",
3382 info->device_name, info->phys_reg_addr));
3383 info->init_error = DiagStatus_AddressConflict;
3384 goto errout;
3385 }
3386 else
3387 info->reg_addr_requested = true;
3388
3389 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3390 if (!info->reg_addr) {
3391 DBGERR(("%s can't map device registers, addr=%08X\n",
3392 info->device_name, info->phys_reg_addr));
3393 info->init_error = DiagStatus_CantAssignPciResources;
3394 goto errout;
3395 }
3396 return 0;
3397
3398 errout:
3399 release_resources(info);
3400 return -ENODEV;
3401 }
3402
release_resources(struct slgt_info * info)3403 static void release_resources(struct slgt_info *info)
3404 {
3405 if (info->irq_requested) {
3406 free_irq(info->irq_level, info);
3407 info->irq_requested = false;
3408 }
3409
3410 if (info->reg_addr_requested) {
3411 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3412 info->reg_addr_requested = false;
3413 }
3414
3415 if (info->reg_addr) {
3416 iounmap(info->reg_addr);
3417 info->reg_addr = NULL;
3418 }
3419 }
3420
3421 /* Add the specified device instance data structure to the
3422 * global linked list of devices and increment the device count.
3423 */
add_device(struct slgt_info * info)3424 static void add_device(struct slgt_info *info)
3425 {
3426 char *devstr;
3427
3428 info->next_device = NULL;
3429 info->line = slgt_device_count;
3430 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3431
3432 if (info->line < MAX_DEVICES) {
3433 if (maxframe[info->line])
3434 info->max_frame_size = maxframe[info->line];
3435 }
3436
3437 slgt_device_count++;
3438
3439 if (!slgt_device_list)
3440 slgt_device_list = info;
3441 else {
3442 struct slgt_info *current_dev = slgt_device_list;
3443 while(current_dev->next_device)
3444 current_dev = current_dev->next_device;
3445 current_dev->next_device = info;
3446 }
3447
3448 if (info->max_frame_size < 4096)
3449 info->max_frame_size = 4096;
3450 else if (info->max_frame_size > 65535)
3451 info->max_frame_size = 65535;
3452
3453 switch(info->pdev->device) {
3454 case SYNCLINK_GT_DEVICE_ID:
3455 devstr = "GT";
3456 break;
3457 case SYNCLINK_GT2_DEVICE_ID:
3458 devstr = "GT2";
3459 break;
3460 case SYNCLINK_GT4_DEVICE_ID:
3461 devstr = "GT4";
3462 break;
3463 case SYNCLINK_AC_DEVICE_ID:
3464 devstr = "AC";
3465 info->params.mode = MGSL_MODE_ASYNC;
3466 break;
3467 default:
3468 devstr = "(unknown model)";
3469 }
3470 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3471 devstr, info->device_name, info->phys_reg_addr,
3472 info->irq_level, info->max_frame_size);
3473
3474 #if SYNCLINK_GENERIC_HDLC
3475 hdlcdev_init(info);
3476 #endif
3477 }
3478
3479 static const struct tty_port_operations slgt_port_ops = {
3480 .carrier_raised = carrier_raised,
3481 .dtr_rts = dtr_rts,
3482 };
3483
3484 /*
3485 * allocate device instance structure, return NULL on failure
3486 */
alloc_dev(int adapter_num,int port_num,struct pci_dev * pdev)3487 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3488 {
3489 struct slgt_info *info;
3490
3491 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3492
3493 if (!info) {
3494 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3495 driver_name, adapter_num, port_num));
3496 } else {
3497 tty_port_init(&info->port);
3498 info->port.ops = &slgt_port_ops;
3499 info->magic = MGSL_MAGIC;
3500 INIT_WORK(&info->task, bh_handler);
3501 info->max_frame_size = 4096;
3502 info->base_clock = 14745600;
3503 info->rbuf_fill_level = DMABUFSIZE;
3504 init_waitqueue_head(&info->status_event_wait_q);
3505 init_waitqueue_head(&info->event_wait_q);
3506 spin_lock_init(&info->netlock);
3507 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3508 info->idle_mode = HDLC_TXIDLE_FLAGS;
3509 info->adapter_num = adapter_num;
3510 info->port_num = port_num;
3511
3512 timer_setup(&info->tx_timer, tx_timeout, 0);
3513 timer_setup(&info->rx_timer, rx_timeout, 0);
3514
3515 /* Copy configuration info to device instance data */
3516 info->pdev = pdev;
3517 info->irq_level = pdev->irq;
3518 info->phys_reg_addr = pci_resource_start(pdev,0);
3519
3520 info->bus_type = MGSL_BUS_TYPE_PCI;
3521 info->irq_flags = IRQF_SHARED;
3522
3523 info->init_error = -1; /* assume error, set to 0 on successful init */
3524 }
3525
3526 return info;
3527 }
3528
device_init(int adapter_num,struct pci_dev * pdev)3529 static void device_init(int adapter_num, struct pci_dev *pdev)
3530 {
3531 struct slgt_info *port_array[SLGT_MAX_PORTS];
3532 int i;
3533 int port_count = 1;
3534
3535 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3536 port_count = 2;
3537 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3538 port_count = 4;
3539
3540 /* allocate device instances for all ports */
3541 for (i=0; i < port_count; ++i) {
3542 port_array[i] = alloc_dev(adapter_num, i, pdev);
3543 if (port_array[i] == NULL) {
3544 for (--i; i >= 0; --i) {
3545 tty_port_destroy(&port_array[i]->port);
3546 kfree(port_array[i]);
3547 }
3548 return;
3549 }
3550 }
3551
3552 /* give copy of port_array to all ports and add to device list */
3553 for (i=0; i < port_count; ++i) {
3554 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3555 add_device(port_array[i]);
3556 port_array[i]->port_count = port_count;
3557 spin_lock_init(&port_array[i]->lock);
3558 }
3559
3560 /* Allocate and claim adapter resources */
3561 if (!claim_resources(port_array[0])) {
3562
3563 alloc_dma_bufs(port_array[0]);
3564
3565 /* copy resource information from first port to others */
3566 for (i = 1; i < port_count; ++i) {
3567 port_array[i]->irq_level = port_array[0]->irq_level;
3568 port_array[i]->reg_addr = port_array[0]->reg_addr;
3569 alloc_dma_bufs(port_array[i]);
3570 }
3571
3572 if (request_irq(port_array[0]->irq_level,
3573 slgt_interrupt,
3574 port_array[0]->irq_flags,
3575 port_array[0]->device_name,
3576 port_array[0]) < 0) {
3577 DBGERR(("%s request_irq failed IRQ=%d\n",
3578 port_array[0]->device_name,
3579 port_array[0]->irq_level));
3580 } else {
3581 port_array[0]->irq_requested = true;
3582 adapter_test(port_array[0]);
3583 for (i=1 ; i < port_count ; i++) {
3584 port_array[i]->init_error = port_array[0]->init_error;
3585 port_array[i]->gpio_present = port_array[0]->gpio_present;
3586 }
3587 }
3588 }
3589
3590 for (i = 0; i < port_count; ++i) {
3591 struct slgt_info *info = port_array[i];
3592 tty_port_register_device(&info->port, serial_driver, info->line,
3593 &info->pdev->dev);
3594 }
3595 }
3596
init_one(struct pci_dev * dev,const struct pci_device_id * ent)3597 static int init_one(struct pci_dev *dev,
3598 const struct pci_device_id *ent)
3599 {
3600 if (pci_enable_device(dev)) {
3601 printk("error enabling pci device %p\n", dev);
3602 return -EIO;
3603 }
3604 pci_set_master(dev);
3605 device_init(slgt_device_count, dev);
3606 return 0;
3607 }
3608
remove_one(struct pci_dev * dev)3609 static void remove_one(struct pci_dev *dev)
3610 {
3611 }
3612
3613 static const struct tty_operations ops = {
3614 .open = open,
3615 .close = close,
3616 .write = write,
3617 .put_char = put_char,
3618 .flush_chars = flush_chars,
3619 .write_room = write_room,
3620 .chars_in_buffer = chars_in_buffer,
3621 .flush_buffer = flush_buffer,
3622 .ioctl = ioctl,
3623 .compat_ioctl = slgt_compat_ioctl,
3624 .throttle = throttle,
3625 .unthrottle = unthrottle,
3626 .send_xchar = send_xchar,
3627 .break_ctl = set_break,
3628 .wait_until_sent = wait_until_sent,
3629 .set_termios = set_termios,
3630 .stop = tx_hold,
3631 .start = tx_release,
3632 .hangup = hangup,
3633 .tiocmget = tiocmget,
3634 .tiocmset = tiocmset,
3635 .get_icount = get_icount,
3636 .proc_show = synclink_gt_proc_show,
3637 };
3638
slgt_cleanup(void)3639 static void slgt_cleanup(void)
3640 {
3641 struct slgt_info *info;
3642 struct slgt_info *tmp;
3643
3644 printk(KERN_INFO "unload %s\n", driver_name);
3645
3646 if (serial_driver) {
3647 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3648 tty_unregister_device(serial_driver, info->line);
3649 tty_unregister_driver(serial_driver);
3650 tty_driver_kref_put(serial_driver);
3651 }
3652
3653 /* reset devices */
3654 info = slgt_device_list;
3655 while(info) {
3656 reset_port(info);
3657 info = info->next_device;
3658 }
3659
3660 /* release devices */
3661 info = slgt_device_list;
3662 while(info) {
3663 #if SYNCLINK_GENERIC_HDLC
3664 hdlcdev_exit(info);
3665 #endif
3666 free_dma_bufs(info);
3667 free_tmp_rbuf(info);
3668 if (info->port_num == 0)
3669 release_resources(info);
3670 tmp = info;
3671 info = info->next_device;
3672 tty_port_destroy(&tmp->port);
3673 kfree(tmp);
3674 }
3675
3676 if (pci_registered)
3677 pci_unregister_driver(&pci_driver);
3678 }
3679
3680 /*
3681 * Driver initialization entry point.
3682 */
slgt_init(void)3683 static int __init slgt_init(void)
3684 {
3685 int rc;
3686
3687 printk(KERN_INFO "%s\n", driver_name);
3688
3689 serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW |
3690 TTY_DRIVER_DYNAMIC_DEV);
3691 if (IS_ERR(serial_driver)) {
3692 printk("%s can't allocate tty driver\n", driver_name);
3693 return PTR_ERR(serial_driver);
3694 }
3695
3696 /* Initialize the tty_driver structure */
3697
3698 serial_driver->driver_name = slgt_driver_name;
3699 serial_driver->name = tty_dev_prefix;
3700 serial_driver->major = ttymajor;
3701 serial_driver->minor_start = 64;
3702 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3703 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3704 serial_driver->init_termios = tty_std_termios;
3705 serial_driver->init_termios.c_cflag =
3706 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3707 serial_driver->init_termios.c_ispeed = 9600;
3708 serial_driver->init_termios.c_ospeed = 9600;
3709 tty_set_operations(serial_driver, &ops);
3710 if ((rc = tty_register_driver(serial_driver)) < 0) {
3711 DBGERR(("%s can't register serial driver\n", driver_name));
3712 tty_driver_kref_put(serial_driver);
3713 serial_driver = NULL;
3714 goto error;
3715 }
3716
3717 printk(KERN_INFO "%s, tty major#%d\n",
3718 driver_name, serial_driver->major);
3719
3720 slgt_device_count = 0;
3721 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3722 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3723 goto error;
3724 }
3725 pci_registered = true;
3726
3727 if (!slgt_device_list)
3728 printk("%s no devices found\n",driver_name);
3729
3730 return 0;
3731
3732 error:
3733 slgt_cleanup();
3734 return rc;
3735 }
3736
slgt_exit(void)3737 static void __exit slgt_exit(void)
3738 {
3739 slgt_cleanup();
3740 }
3741
3742 module_init(slgt_init);
3743 module_exit(slgt_exit);
3744
3745 /*
3746 * register access routines
3747 */
3748
3749 #define CALC_REGADDR() \
3750 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3751 if (addr >= 0x80) \
3752 reg_addr += (info->port_num) * 32; \
3753 else if (addr >= 0x40) \
3754 reg_addr += (info->port_num) * 16;
3755
rd_reg8(struct slgt_info * info,unsigned int addr)3756 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3757 {
3758 CALC_REGADDR();
3759 return readb((void __iomem *)reg_addr);
3760 }
3761
wr_reg8(struct slgt_info * info,unsigned int addr,__u8 value)3762 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3763 {
3764 CALC_REGADDR();
3765 writeb(value, (void __iomem *)reg_addr);
3766 }
3767
rd_reg16(struct slgt_info * info,unsigned int addr)3768 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3769 {
3770 CALC_REGADDR();
3771 return readw((void __iomem *)reg_addr);
3772 }
3773
wr_reg16(struct slgt_info * info,unsigned int addr,__u16 value)3774 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3775 {
3776 CALC_REGADDR();
3777 writew(value, (void __iomem *)reg_addr);
3778 }
3779
rd_reg32(struct slgt_info * info,unsigned int addr)3780 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3781 {
3782 CALC_REGADDR();
3783 return readl((void __iomem *)reg_addr);
3784 }
3785
wr_reg32(struct slgt_info * info,unsigned int addr,__u32 value)3786 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3787 {
3788 CALC_REGADDR();
3789 writel(value, (void __iomem *)reg_addr);
3790 }
3791
rdma_reset(struct slgt_info * info)3792 static void rdma_reset(struct slgt_info *info)
3793 {
3794 unsigned int i;
3795
3796 /* set reset bit */
3797 wr_reg32(info, RDCSR, BIT1);
3798
3799 /* wait for enable bit cleared */
3800 for(i=0 ; i < 1000 ; i++)
3801 if (!(rd_reg32(info, RDCSR) & BIT0))
3802 break;
3803 }
3804
tdma_reset(struct slgt_info * info)3805 static void tdma_reset(struct slgt_info *info)
3806 {
3807 unsigned int i;
3808
3809 /* set reset bit */
3810 wr_reg32(info, TDCSR, BIT1);
3811
3812 /* wait for enable bit cleared */
3813 for(i=0 ; i < 1000 ; i++)
3814 if (!(rd_reg32(info, TDCSR) & BIT0))
3815 break;
3816 }
3817
3818 /*
3819 * enable internal loopback
3820 * TxCLK and RxCLK are generated from BRG
3821 * and TxD is looped back to RxD internally.
3822 */
enable_loopback(struct slgt_info * info)3823 static void enable_loopback(struct slgt_info *info)
3824 {
3825 /* SCR (serial control) BIT2=loopback enable */
3826 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3827
3828 if (info->params.mode != MGSL_MODE_ASYNC) {
3829 /* CCR (clock control)
3830 * 07..05 tx clock source (010 = BRG)
3831 * 04..02 rx clock source (010 = BRG)
3832 * 01 auxclk enable (0 = disable)
3833 * 00 BRG enable (1 = enable)
3834 *
3835 * 0100 1001
3836 */
3837 wr_reg8(info, CCR, 0x49);
3838
3839 /* set speed if available, otherwise use default */
3840 if (info->params.clock_speed)
3841 set_rate(info, info->params.clock_speed);
3842 else
3843 set_rate(info, 3686400);
3844 }
3845 }
3846
3847 /*
3848 * set baud rate generator to specified rate
3849 */
set_rate(struct slgt_info * info,u32 rate)3850 static void set_rate(struct slgt_info *info, u32 rate)
3851 {
3852 unsigned int div;
3853 unsigned int osc = info->base_clock;
3854
3855 /* div = osc/rate - 1
3856 *
3857 * Round div up if osc/rate is not integer to
3858 * force to next slowest rate.
3859 */
3860
3861 if (rate) {
3862 div = osc/rate;
3863 if (!(osc % rate) && div)
3864 div--;
3865 wr_reg16(info, BDR, (unsigned short)div);
3866 }
3867 }
3868
rx_stop(struct slgt_info * info)3869 static void rx_stop(struct slgt_info *info)
3870 {
3871 unsigned short val;
3872
3873 /* disable and reset receiver */
3874 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3875 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3876 wr_reg16(info, RCR, val); /* clear reset bit */
3877
3878 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3879
3880 /* clear pending rx interrupts */
3881 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3882
3883 rdma_reset(info);
3884
3885 info->rx_enabled = false;
3886 info->rx_restart = false;
3887 }
3888
rx_start(struct slgt_info * info)3889 static void rx_start(struct slgt_info *info)
3890 {
3891 unsigned short val;
3892
3893 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3894
3895 /* clear pending rx overrun IRQ */
3896 wr_reg16(info, SSR, IRQ_RXOVER);
3897
3898 /* reset and disable receiver */
3899 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3900 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3901 wr_reg16(info, RCR, val); /* clear reset bit */
3902
3903 rdma_reset(info);
3904 reset_rbufs(info);
3905
3906 if (info->rx_pio) {
3907 /* rx request when rx FIFO not empty */
3908 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3909 slgt_irq_on(info, IRQ_RXDATA);
3910 if (info->params.mode == MGSL_MODE_ASYNC) {
3911 /* enable saving of rx status */
3912 wr_reg32(info, RDCSR, BIT6);
3913 }
3914 } else {
3915 /* rx request when rx FIFO half full */
3916 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3917 /* set 1st descriptor address */
3918 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3919
3920 if (info->params.mode != MGSL_MODE_ASYNC) {
3921 /* enable rx DMA and DMA interrupt */
3922 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3923 } else {
3924 /* enable saving of rx status, rx DMA and DMA interrupt */
3925 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3926 }
3927 }
3928
3929 slgt_irq_on(info, IRQ_RXOVER);
3930
3931 /* enable receiver */
3932 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3933
3934 info->rx_restart = false;
3935 info->rx_enabled = true;
3936 }
3937
tx_start(struct slgt_info * info)3938 static void tx_start(struct slgt_info *info)
3939 {
3940 if (!info->tx_enabled) {
3941 wr_reg16(info, TCR,
3942 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3943 info->tx_enabled = true;
3944 }
3945
3946 if (desc_count(info->tbufs[info->tbuf_start])) {
3947 info->drop_rts_on_tx_done = false;
3948
3949 if (info->params.mode != MGSL_MODE_ASYNC) {
3950 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3951 get_gtsignals(info);
3952 if (!(info->signals & SerialSignal_RTS)) {
3953 info->signals |= SerialSignal_RTS;
3954 set_gtsignals(info);
3955 info->drop_rts_on_tx_done = true;
3956 }
3957 }
3958
3959 slgt_irq_off(info, IRQ_TXDATA);
3960 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3961 /* clear tx idle and underrun status bits */
3962 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3963 } else {
3964 slgt_irq_off(info, IRQ_TXDATA);
3965 slgt_irq_on(info, IRQ_TXIDLE);
3966 /* clear tx idle status bit */
3967 wr_reg16(info, SSR, IRQ_TXIDLE);
3968 }
3969 /* set 1st descriptor address and start DMA */
3970 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3971 wr_reg32(info, TDCSR, BIT2 + BIT0);
3972 info->tx_active = true;
3973 }
3974 }
3975
tx_stop(struct slgt_info * info)3976 static void tx_stop(struct slgt_info *info)
3977 {
3978 unsigned short val;
3979
3980 del_timer(&info->tx_timer);
3981
3982 tdma_reset(info);
3983
3984 /* reset and disable transmitter */
3985 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3986 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3987
3988 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3989
3990 /* clear tx idle and underrun status bit */
3991 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3992
3993 reset_tbufs(info);
3994
3995 info->tx_enabled = false;
3996 info->tx_active = false;
3997 }
3998
reset_port(struct slgt_info * info)3999 static void reset_port(struct slgt_info *info)
4000 {
4001 if (!info->reg_addr)
4002 return;
4003
4004 tx_stop(info);
4005 rx_stop(info);
4006
4007 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4008 set_gtsignals(info);
4009
4010 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4011 }
4012
reset_adapter(struct slgt_info * info)4013 static void reset_adapter(struct slgt_info *info)
4014 {
4015 int i;
4016 for (i=0; i < info->port_count; ++i) {
4017 if (info->port_array[i])
4018 reset_port(info->port_array[i]);
4019 }
4020 }
4021
async_mode(struct slgt_info * info)4022 static void async_mode(struct slgt_info *info)
4023 {
4024 unsigned short val;
4025
4026 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4027 tx_stop(info);
4028 rx_stop(info);
4029
4030 /* TCR (tx control)
4031 *
4032 * 15..13 mode, 010=async
4033 * 12..10 encoding, 000=NRZ
4034 * 09 parity enable
4035 * 08 1=odd parity, 0=even parity
4036 * 07 1=RTS driver control
4037 * 06 1=break enable
4038 * 05..04 character length
4039 * 00=5 bits
4040 * 01=6 bits
4041 * 10=7 bits
4042 * 11=8 bits
4043 * 03 0=1 stop bit, 1=2 stop bits
4044 * 02 reset
4045 * 01 enable
4046 * 00 auto-CTS enable
4047 */
4048 val = 0x4000;
4049
4050 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4051 val |= BIT7;
4052
4053 if (info->params.parity != ASYNC_PARITY_NONE) {
4054 val |= BIT9;
4055 if (info->params.parity == ASYNC_PARITY_ODD)
4056 val |= BIT8;
4057 }
4058
4059 switch (info->params.data_bits)
4060 {
4061 case 6: val |= BIT4; break;
4062 case 7: val |= BIT5; break;
4063 case 8: val |= BIT5 + BIT4; break;
4064 }
4065
4066 if (info->params.stop_bits != 1)
4067 val |= BIT3;
4068
4069 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4070 val |= BIT0;
4071
4072 wr_reg16(info, TCR, val);
4073
4074 /* RCR (rx control)
4075 *
4076 * 15..13 mode, 010=async
4077 * 12..10 encoding, 000=NRZ
4078 * 09 parity enable
4079 * 08 1=odd parity, 0=even parity
4080 * 07..06 reserved, must be 0
4081 * 05..04 character length
4082 * 00=5 bits
4083 * 01=6 bits
4084 * 10=7 bits
4085 * 11=8 bits
4086 * 03 reserved, must be zero
4087 * 02 reset
4088 * 01 enable
4089 * 00 auto-DCD enable
4090 */
4091 val = 0x4000;
4092
4093 if (info->params.parity != ASYNC_PARITY_NONE) {
4094 val |= BIT9;
4095 if (info->params.parity == ASYNC_PARITY_ODD)
4096 val |= BIT8;
4097 }
4098
4099 switch (info->params.data_bits)
4100 {
4101 case 6: val |= BIT4; break;
4102 case 7: val |= BIT5; break;
4103 case 8: val |= BIT5 + BIT4; break;
4104 }
4105
4106 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4107 val |= BIT0;
4108
4109 wr_reg16(info, RCR, val);
4110
4111 /* CCR (clock control)
4112 *
4113 * 07..05 011 = tx clock source is BRG/16
4114 * 04..02 010 = rx clock source is BRG
4115 * 01 0 = auxclk disabled
4116 * 00 1 = BRG enabled
4117 *
4118 * 0110 1001
4119 */
4120 wr_reg8(info, CCR, 0x69);
4121
4122 msc_set_vcr(info);
4123
4124 /* SCR (serial control)
4125 *
4126 * 15 1=tx req on FIFO half empty
4127 * 14 1=rx req on FIFO half full
4128 * 13 tx data IRQ enable
4129 * 12 tx idle IRQ enable
4130 * 11 rx break on IRQ enable
4131 * 10 rx data IRQ enable
4132 * 09 rx break off IRQ enable
4133 * 08 overrun IRQ enable
4134 * 07 DSR IRQ enable
4135 * 06 CTS IRQ enable
4136 * 05 DCD IRQ enable
4137 * 04 RI IRQ enable
4138 * 03 0=16x sampling, 1=8x sampling
4139 * 02 1=txd->rxd internal loopback enable
4140 * 01 reserved, must be zero
4141 * 00 1=master IRQ enable
4142 */
4143 val = BIT15 + BIT14 + BIT0;
4144 /* JCR[8] : 1 = x8 async mode feature available */
4145 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4146 ((info->base_clock < (info->params.data_rate * 16)) ||
4147 (info->base_clock % (info->params.data_rate * 16)))) {
4148 /* use 8x sampling */
4149 val |= BIT3;
4150 set_rate(info, info->params.data_rate * 8);
4151 } else {
4152 /* use 16x sampling */
4153 set_rate(info, info->params.data_rate * 16);
4154 }
4155 wr_reg16(info, SCR, val);
4156
4157 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4158
4159 if (info->params.loopback)
4160 enable_loopback(info);
4161 }
4162
sync_mode(struct slgt_info * info)4163 static void sync_mode(struct slgt_info *info)
4164 {
4165 unsigned short val;
4166
4167 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4168 tx_stop(info);
4169 rx_stop(info);
4170
4171 /* TCR (tx control)
4172 *
4173 * 15..13 mode
4174 * 000=HDLC/SDLC
4175 * 001=raw bit synchronous
4176 * 010=asynchronous/isochronous
4177 * 011=monosync byte synchronous
4178 * 100=bisync byte synchronous
4179 * 101=xsync byte synchronous
4180 * 12..10 encoding
4181 * 09 CRC enable
4182 * 08 CRC32
4183 * 07 1=RTS driver control
4184 * 06 preamble enable
4185 * 05..04 preamble length
4186 * 03 share open/close flag
4187 * 02 reset
4188 * 01 enable
4189 * 00 auto-CTS enable
4190 */
4191 val = BIT2;
4192
4193 switch(info->params.mode) {
4194 case MGSL_MODE_XSYNC:
4195 val |= BIT15 + BIT13;
4196 break;
4197 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4198 case MGSL_MODE_BISYNC: val |= BIT15; break;
4199 case MGSL_MODE_RAW: val |= BIT13; break;
4200 }
4201 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4202 val |= BIT7;
4203
4204 switch(info->params.encoding)
4205 {
4206 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4207 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4208 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4209 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4210 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4211 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4212 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4213 }
4214
4215 switch (info->params.crc_type & HDLC_CRC_MASK)
4216 {
4217 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4218 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4219 }
4220
4221 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4222 val |= BIT6;
4223
4224 switch (info->params.preamble_length)
4225 {
4226 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4227 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4228 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4229 }
4230
4231 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4232 val |= BIT0;
4233
4234 wr_reg16(info, TCR, val);
4235
4236 /* TPR (transmit preamble) */
4237
4238 switch (info->params.preamble)
4239 {
4240 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4241 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4242 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4243 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4244 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4245 default: val = 0x7e; break;
4246 }
4247 wr_reg8(info, TPR, (unsigned char)val);
4248
4249 /* RCR (rx control)
4250 *
4251 * 15..13 mode
4252 * 000=HDLC/SDLC
4253 * 001=raw bit synchronous
4254 * 010=asynchronous/isochronous
4255 * 011=monosync byte synchronous
4256 * 100=bisync byte synchronous
4257 * 101=xsync byte synchronous
4258 * 12..10 encoding
4259 * 09 CRC enable
4260 * 08 CRC32
4261 * 07..03 reserved, must be 0
4262 * 02 reset
4263 * 01 enable
4264 * 00 auto-DCD enable
4265 */
4266 val = 0;
4267
4268 switch(info->params.mode) {
4269 case MGSL_MODE_XSYNC:
4270 val |= BIT15 + BIT13;
4271 break;
4272 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4273 case MGSL_MODE_BISYNC: val |= BIT15; break;
4274 case MGSL_MODE_RAW: val |= BIT13; break;
4275 }
4276
4277 switch(info->params.encoding)
4278 {
4279 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4280 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4281 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4282 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4283 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4284 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4285 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4286 }
4287
4288 switch (info->params.crc_type & HDLC_CRC_MASK)
4289 {
4290 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4291 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4292 }
4293
4294 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4295 val |= BIT0;
4296
4297 wr_reg16(info, RCR, val);
4298
4299 /* CCR (clock control)
4300 *
4301 * 07..05 tx clock source
4302 * 04..02 rx clock source
4303 * 01 auxclk enable
4304 * 00 BRG enable
4305 */
4306 val = 0;
4307
4308 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4309 {
4310 // when RxC source is DPLL, BRG generates 16X DPLL
4311 // reference clock, so take TxC from BRG/16 to get
4312 // transmit clock at actual data rate
4313 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4314 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4315 else
4316 val |= BIT6; /* 010, txclk = BRG */
4317 }
4318 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4319 val |= BIT7; /* 100, txclk = DPLL Input */
4320 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4321 val |= BIT5; /* 001, txclk = RXC Input */
4322
4323 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4324 val |= BIT3; /* 010, rxclk = BRG */
4325 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4326 val |= BIT4; /* 100, rxclk = DPLL */
4327 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4328 val |= BIT2; /* 001, rxclk = TXC Input */
4329
4330 if (info->params.clock_speed)
4331 val |= BIT1 + BIT0;
4332
4333 wr_reg8(info, CCR, (unsigned char)val);
4334
4335 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4336 {
4337 // program DPLL mode
4338 switch(info->params.encoding)
4339 {
4340 case HDLC_ENCODING_BIPHASE_MARK:
4341 case HDLC_ENCODING_BIPHASE_SPACE:
4342 val = BIT7; break;
4343 case HDLC_ENCODING_BIPHASE_LEVEL:
4344 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4345 val = BIT7 + BIT6; break;
4346 default: val = BIT6; // NRZ encodings
4347 }
4348 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4349
4350 // DPLL requires a 16X reference clock from BRG
4351 set_rate(info, info->params.clock_speed * 16);
4352 }
4353 else
4354 set_rate(info, info->params.clock_speed);
4355
4356 tx_set_idle(info);
4357
4358 msc_set_vcr(info);
4359
4360 /* SCR (serial control)
4361 *
4362 * 15 1=tx req on FIFO half empty
4363 * 14 1=rx req on FIFO half full
4364 * 13 tx data IRQ enable
4365 * 12 tx idle IRQ enable
4366 * 11 underrun IRQ enable
4367 * 10 rx data IRQ enable
4368 * 09 rx idle IRQ enable
4369 * 08 overrun IRQ enable
4370 * 07 DSR IRQ enable
4371 * 06 CTS IRQ enable
4372 * 05 DCD IRQ enable
4373 * 04 RI IRQ enable
4374 * 03 reserved, must be zero
4375 * 02 1=txd->rxd internal loopback enable
4376 * 01 reserved, must be zero
4377 * 00 1=master IRQ enable
4378 */
4379 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4380
4381 if (info->params.loopback)
4382 enable_loopback(info);
4383 }
4384
4385 /*
4386 * set transmit idle mode
4387 */
tx_set_idle(struct slgt_info * info)4388 static void tx_set_idle(struct slgt_info *info)
4389 {
4390 unsigned char val;
4391 unsigned short tcr;
4392
4393 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4394 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4395 */
4396 tcr = rd_reg16(info, TCR);
4397 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4398 /* disable preamble, set idle size to 16 bits */
4399 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4400 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4401 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4402 } else if (!(tcr & BIT6)) {
4403 /* preamble is disabled, set idle size to 8 bits */
4404 tcr &= ~(BIT5 + BIT4);
4405 }
4406 wr_reg16(info, TCR, tcr);
4407
4408 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4409 /* LSB of custom tx idle specified in tx idle register */
4410 val = (unsigned char)(info->idle_mode & 0xff);
4411 } else {
4412 /* standard 8 bit idle patterns */
4413 switch(info->idle_mode)
4414 {
4415 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4416 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4417 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4418 case HDLC_TXIDLE_ZEROS:
4419 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4420 default: val = 0xff;
4421 }
4422 }
4423
4424 wr_reg8(info, TIR, val);
4425 }
4426
4427 /*
4428 * get state of V24 status (input) signals
4429 */
get_gtsignals(struct slgt_info * info)4430 static void get_gtsignals(struct slgt_info *info)
4431 {
4432 unsigned short status = rd_reg16(info, SSR);
4433
4434 /* clear all serial signals except RTS and DTR */
4435 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4436
4437 if (status & BIT3)
4438 info->signals |= SerialSignal_DSR;
4439 if (status & BIT2)
4440 info->signals |= SerialSignal_CTS;
4441 if (status & BIT1)
4442 info->signals |= SerialSignal_DCD;
4443 if (status & BIT0)
4444 info->signals |= SerialSignal_RI;
4445 }
4446
4447 /*
4448 * set V.24 Control Register based on current configuration
4449 */
msc_set_vcr(struct slgt_info * info)4450 static void msc_set_vcr(struct slgt_info *info)
4451 {
4452 unsigned char val = 0;
4453
4454 /* VCR (V.24 control)
4455 *
4456 * 07..04 serial IF select
4457 * 03 DTR
4458 * 02 RTS
4459 * 01 LL
4460 * 00 RL
4461 */
4462
4463 switch(info->if_mode & MGSL_INTERFACE_MASK)
4464 {
4465 case MGSL_INTERFACE_RS232:
4466 val |= BIT5; /* 0010 */
4467 break;
4468 case MGSL_INTERFACE_V35:
4469 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4470 break;
4471 case MGSL_INTERFACE_RS422:
4472 val |= BIT6; /* 0100 */
4473 break;
4474 }
4475
4476 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4477 val |= BIT4;
4478 if (info->signals & SerialSignal_DTR)
4479 val |= BIT3;
4480 if (info->signals & SerialSignal_RTS)
4481 val |= BIT2;
4482 if (info->if_mode & MGSL_INTERFACE_LL)
4483 val |= BIT1;
4484 if (info->if_mode & MGSL_INTERFACE_RL)
4485 val |= BIT0;
4486 wr_reg8(info, VCR, val);
4487 }
4488
4489 /*
4490 * set state of V24 control (output) signals
4491 */
set_gtsignals(struct slgt_info * info)4492 static void set_gtsignals(struct slgt_info *info)
4493 {
4494 unsigned char val = rd_reg8(info, VCR);
4495 if (info->signals & SerialSignal_DTR)
4496 val |= BIT3;
4497 else
4498 val &= ~BIT3;
4499 if (info->signals & SerialSignal_RTS)
4500 val |= BIT2;
4501 else
4502 val &= ~BIT2;
4503 wr_reg8(info, VCR, val);
4504 }
4505
4506 /*
4507 * free range of receive DMA buffers (i to last)
4508 */
free_rbufs(struct slgt_info * info,unsigned int i,unsigned int last)4509 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4510 {
4511 int done = 0;
4512
4513 while(!done) {
4514 /* reset current buffer for reuse */
4515 info->rbufs[i].status = 0;
4516 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4517 if (i == last)
4518 done = 1;
4519 if (++i == info->rbuf_count)
4520 i = 0;
4521 }
4522 info->rbuf_current = i;
4523 }
4524
4525 /*
4526 * mark all receive DMA buffers as free
4527 */
reset_rbufs(struct slgt_info * info)4528 static void reset_rbufs(struct slgt_info *info)
4529 {
4530 free_rbufs(info, 0, info->rbuf_count - 1);
4531 info->rbuf_fill_index = 0;
4532 info->rbuf_fill_count = 0;
4533 }
4534
4535 /*
4536 * pass receive HDLC frame to upper layer
4537 *
4538 * return true if frame available, otherwise false
4539 */
rx_get_frame(struct slgt_info * info)4540 static bool rx_get_frame(struct slgt_info *info)
4541 {
4542 unsigned int start, end;
4543 unsigned short status;
4544 unsigned int framesize = 0;
4545 unsigned long flags;
4546 struct tty_struct *tty = info->port.tty;
4547 unsigned char addr_field = 0xff;
4548 unsigned int crc_size = 0;
4549
4550 switch (info->params.crc_type & HDLC_CRC_MASK) {
4551 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4552 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4553 }
4554
4555 check_again:
4556
4557 framesize = 0;
4558 addr_field = 0xff;
4559 start = end = info->rbuf_current;
4560
4561 for (;;) {
4562 if (!desc_complete(info->rbufs[end]))
4563 goto cleanup;
4564
4565 if (framesize == 0 && info->params.addr_filter != 0xff)
4566 addr_field = info->rbufs[end].buf[0];
4567
4568 framesize += desc_count(info->rbufs[end]);
4569
4570 if (desc_eof(info->rbufs[end]))
4571 break;
4572
4573 if (++end == info->rbuf_count)
4574 end = 0;
4575
4576 if (end == info->rbuf_current) {
4577 if (info->rx_enabled){
4578 spin_lock_irqsave(&info->lock,flags);
4579 rx_start(info);
4580 spin_unlock_irqrestore(&info->lock,flags);
4581 }
4582 goto cleanup;
4583 }
4584 }
4585
4586 /* status
4587 *
4588 * 15 buffer complete
4589 * 14..06 reserved
4590 * 05..04 residue
4591 * 02 eof (end of frame)
4592 * 01 CRC error
4593 * 00 abort
4594 */
4595 status = desc_status(info->rbufs[end]);
4596
4597 /* ignore CRC bit if not using CRC (bit is undefined) */
4598 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4599 status &= ~BIT1;
4600
4601 if (framesize == 0 ||
4602 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4603 free_rbufs(info, start, end);
4604 goto check_again;
4605 }
4606
4607 if (framesize < (2 + crc_size) || status & BIT0) {
4608 info->icount.rxshort++;
4609 framesize = 0;
4610 } else if (status & BIT1) {
4611 info->icount.rxcrc++;
4612 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4613 framesize = 0;
4614 }
4615
4616 #if SYNCLINK_GENERIC_HDLC
4617 if (framesize == 0) {
4618 info->netdev->stats.rx_errors++;
4619 info->netdev->stats.rx_frame_errors++;
4620 }
4621 #endif
4622
4623 DBGBH(("%s rx frame status=%04X size=%d\n",
4624 info->device_name, status, framesize));
4625 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4626
4627 if (framesize) {
4628 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4629 framesize -= crc_size;
4630 crc_size = 0;
4631 }
4632
4633 if (framesize > info->max_frame_size + crc_size)
4634 info->icount.rxlong++;
4635 else {
4636 /* copy dma buffer(s) to contiguous temp buffer */
4637 int copy_count = framesize;
4638 int i = start;
4639 unsigned char *p = info->tmp_rbuf;
4640 info->tmp_rbuf_count = framesize;
4641
4642 info->icount.rxok++;
4643
4644 while(copy_count) {
4645 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4646 memcpy(p, info->rbufs[i].buf, partial_count);
4647 p += partial_count;
4648 copy_count -= partial_count;
4649 if (++i == info->rbuf_count)
4650 i = 0;
4651 }
4652
4653 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4654 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4655 framesize++;
4656 }
4657
4658 #if SYNCLINK_GENERIC_HDLC
4659 if (info->netcount)
4660 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4661 else
4662 #endif
4663 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4664 }
4665 }
4666 free_rbufs(info, start, end);
4667 return true;
4668
4669 cleanup:
4670 return false;
4671 }
4672
4673 /*
4674 * pass receive buffer (RAW synchronous mode) to tty layer
4675 * return true if buffer available, otherwise false
4676 */
rx_get_buf(struct slgt_info * info)4677 static bool rx_get_buf(struct slgt_info *info)
4678 {
4679 unsigned int i = info->rbuf_current;
4680 unsigned int count;
4681
4682 if (!desc_complete(info->rbufs[i]))
4683 return false;
4684 count = desc_count(info->rbufs[i]);
4685 switch(info->params.mode) {
4686 case MGSL_MODE_MONOSYNC:
4687 case MGSL_MODE_BISYNC:
4688 case MGSL_MODE_XSYNC:
4689 /* ignore residue in byte synchronous modes */
4690 if (desc_residue(info->rbufs[i]))
4691 count--;
4692 break;
4693 }
4694 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4695 DBGINFO(("rx_get_buf size=%d\n", count));
4696 if (count)
4697 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4698 info->flag_buf, count);
4699 free_rbufs(info, i, i);
4700 return true;
4701 }
4702
reset_tbufs(struct slgt_info * info)4703 static void reset_tbufs(struct slgt_info *info)
4704 {
4705 unsigned int i;
4706 info->tbuf_current = 0;
4707 for (i=0 ; i < info->tbuf_count ; i++) {
4708 info->tbufs[i].status = 0;
4709 info->tbufs[i].count = 0;
4710 }
4711 }
4712
4713 /*
4714 * return number of free transmit DMA buffers
4715 */
free_tbuf_count(struct slgt_info * info)4716 static unsigned int free_tbuf_count(struct slgt_info *info)
4717 {
4718 unsigned int count = 0;
4719 unsigned int i = info->tbuf_current;
4720
4721 do
4722 {
4723 if (desc_count(info->tbufs[i]))
4724 break; /* buffer in use */
4725 ++count;
4726 if (++i == info->tbuf_count)
4727 i=0;
4728 } while (i != info->tbuf_current);
4729
4730 /* if tx DMA active, last zero count buffer is in use */
4731 if (count && (rd_reg32(info, TDCSR) & BIT0))
4732 --count;
4733
4734 return count;
4735 }
4736
4737 /*
4738 * return number of bytes in unsent transmit DMA buffers
4739 * and the serial controller tx FIFO
4740 */
tbuf_bytes(struct slgt_info * info)4741 static unsigned int tbuf_bytes(struct slgt_info *info)
4742 {
4743 unsigned int total_count = 0;
4744 unsigned int i = info->tbuf_current;
4745 unsigned int reg_value;
4746 unsigned int count;
4747 unsigned int active_buf_count = 0;
4748
4749 /*
4750 * Add descriptor counts for all tx DMA buffers.
4751 * If count is zero (cleared by DMA controller after read),
4752 * the buffer is complete or is actively being read from.
4753 *
4754 * Record buf_count of last buffer with zero count starting
4755 * from current ring position. buf_count is mirror
4756 * copy of count and is not cleared by serial controller.
4757 * If DMA controller is active, that buffer is actively
4758 * being read so add to total.
4759 */
4760 do {
4761 count = desc_count(info->tbufs[i]);
4762 if (count)
4763 total_count += count;
4764 else if (!total_count)
4765 active_buf_count = info->tbufs[i].buf_count;
4766 if (++i == info->tbuf_count)
4767 i = 0;
4768 } while (i != info->tbuf_current);
4769
4770 /* read tx DMA status register */
4771 reg_value = rd_reg32(info, TDCSR);
4772
4773 /* if tx DMA active, last zero count buffer is in use */
4774 if (reg_value & BIT0)
4775 total_count += active_buf_count;
4776
4777 /* add tx FIFO count = reg_value[15..8] */
4778 total_count += (reg_value >> 8) & 0xff;
4779
4780 /* if transmitter active add one byte for shift register */
4781 if (info->tx_active)
4782 total_count++;
4783
4784 return total_count;
4785 }
4786
4787 /*
4788 * load data into transmit DMA buffer ring and start transmitter if needed
4789 * return true if data accepted, otherwise false (buffers full)
4790 */
tx_load(struct slgt_info * info,const char * buf,unsigned int size)4791 static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4792 {
4793 unsigned short count;
4794 unsigned int i;
4795 struct slgt_desc *d;
4796
4797 /* check required buffer space */
4798 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4799 return false;
4800
4801 DBGDATA(info, buf, size, "tx");
4802
4803 /*
4804 * copy data to one or more DMA buffers in circular ring
4805 * tbuf_start = first buffer for this data
4806 * tbuf_current = next free buffer
4807 *
4808 * Copy all data before making data visible to DMA controller by
4809 * setting descriptor count of the first buffer.
4810 * This prevents an active DMA controller from reading the first DMA
4811 * buffers of a frame and stopping before the final buffers are filled.
4812 */
4813
4814 info->tbuf_start = i = info->tbuf_current;
4815
4816 while (size) {
4817 d = &info->tbufs[i];
4818
4819 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4820 memcpy(d->buf, buf, count);
4821
4822 size -= count;
4823 buf += count;
4824
4825 /*
4826 * set EOF bit for last buffer of HDLC frame or
4827 * for every buffer in raw mode
4828 */
4829 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4830 info->params.mode == MGSL_MODE_RAW)
4831 set_desc_eof(*d, 1);
4832 else
4833 set_desc_eof(*d, 0);
4834
4835 /* set descriptor count for all but first buffer */
4836 if (i != info->tbuf_start)
4837 set_desc_count(*d, count);
4838 d->buf_count = count;
4839
4840 if (++i == info->tbuf_count)
4841 i = 0;
4842 }
4843
4844 info->tbuf_current = i;
4845
4846 /* set first buffer count to make new data visible to DMA controller */
4847 d = &info->tbufs[info->tbuf_start];
4848 set_desc_count(*d, d->buf_count);
4849
4850 /* start transmitter if needed and update transmit timeout */
4851 if (!info->tx_active)
4852 tx_start(info);
4853 update_tx_timer(info);
4854
4855 return true;
4856 }
4857
register_test(struct slgt_info * info)4858 static int register_test(struct slgt_info *info)
4859 {
4860 static unsigned short patterns[] =
4861 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4862 static unsigned int count = ARRAY_SIZE(patterns);
4863 unsigned int i;
4864 int rc = 0;
4865
4866 for (i=0 ; i < count ; i++) {
4867 wr_reg16(info, TIR, patterns[i]);
4868 wr_reg16(info, BDR, patterns[(i+1)%count]);
4869 if ((rd_reg16(info, TIR) != patterns[i]) ||
4870 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4871 rc = -ENODEV;
4872 break;
4873 }
4874 }
4875 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4876 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4877 return rc;
4878 }
4879
irq_test(struct slgt_info * info)4880 static int irq_test(struct slgt_info *info)
4881 {
4882 unsigned long timeout;
4883 unsigned long flags;
4884 struct tty_struct *oldtty = info->port.tty;
4885 u32 speed = info->params.data_rate;
4886
4887 info->params.data_rate = 921600;
4888 info->port.tty = NULL;
4889
4890 spin_lock_irqsave(&info->lock, flags);
4891 async_mode(info);
4892 slgt_irq_on(info, IRQ_TXIDLE);
4893
4894 /* enable transmitter */
4895 wr_reg16(info, TCR,
4896 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4897
4898 /* write one byte and wait for tx idle */
4899 wr_reg16(info, TDR, 0);
4900
4901 /* assume failure */
4902 info->init_error = DiagStatus_IrqFailure;
4903 info->irq_occurred = false;
4904
4905 spin_unlock_irqrestore(&info->lock, flags);
4906
4907 timeout=100;
4908 while(timeout-- && !info->irq_occurred)
4909 msleep_interruptible(10);
4910
4911 spin_lock_irqsave(&info->lock,flags);
4912 reset_port(info);
4913 spin_unlock_irqrestore(&info->lock,flags);
4914
4915 info->params.data_rate = speed;
4916 info->port.tty = oldtty;
4917
4918 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4919 return info->irq_occurred ? 0 : -ENODEV;
4920 }
4921
loopback_test_rx(struct slgt_info * info)4922 static int loopback_test_rx(struct slgt_info *info)
4923 {
4924 unsigned char *src, *dest;
4925 int count;
4926
4927 if (desc_complete(info->rbufs[0])) {
4928 count = desc_count(info->rbufs[0]);
4929 src = info->rbufs[0].buf;
4930 dest = info->tmp_rbuf;
4931
4932 for( ; count ; count-=2, src+=2) {
4933 /* src=data byte (src+1)=status byte */
4934 if (!(*(src+1) & (BIT9 + BIT8))) {
4935 *dest = *src;
4936 dest++;
4937 info->tmp_rbuf_count++;
4938 }
4939 }
4940 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4941 return 1;
4942 }
4943 return 0;
4944 }
4945
loopback_test(struct slgt_info * info)4946 static int loopback_test(struct slgt_info *info)
4947 {
4948 #define TESTFRAMESIZE 20
4949
4950 unsigned long timeout;
4951 u16 count;
4952 unsigned char buf[TESTFRAMESIZE];
4953 int rc = -ENODEV;
4954 unsigned long flags;
4955
4956 struct tty_struct *oldtty = info->port.tty;
4957 MGSL_PARAMS params;
4958
4959 memcpy(¶ms, &info->params, sizeof(params));
4960
4961 info->params.mode = MGSL_MODE_ASYNC;
4962 info->params.data_rate = 921600;
4963 info->params.loopback = 1;
4964 info->port.tty = NULL;
4965
4966 /* build and send transmit frame */
4967 for (count = 0; count < TESTFRAMESIZE; ++count)
4968 buf[count] = (unsigned char)count;
4969
4970 info->tmp_rbuf_count = 0;
4971 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4972
4973 /* program hardware for HDLC and enabled receiver */
4974 spin_lock_irqsave(&info->lock,flags);
4975 async_mode(info);
4976 rx_start(info);
4977 tx_load(info, buf, count);
4978 spin_unlock_irqrestore(&info->lock, flags);
4979
4980 /* wait for receive complete */
4981 for (timeout = 100; timeout; --timeout) {
4982 msleep_interruptible(10);
4983 if (loopback_test_rx(info)) {
4984 rc = 0;
4985 break;
4986 }
4987 }
4988
4989 /* verify received frame length and contents */
4990 if (!rc && (info->tmp_rbuf_count != count ||
4991 memcmp(buf, info->tmp_rbuf, count))) {
4992 rc = -ENODEV;
4993 }
4994
4995 spin_lock_irqsave(&info->lock,flags);
4996 reset_adapter(info);
4997 spin_unlock_irqrestore(&info->lock,flags);
4998
4999 memcpy(&info->params, ¶ms, sizeof(info->params));
5000 info->port.tty = oldtty;
5001
5002 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5003 return rc;
5004 }
5005
adapter_test(struct slgt_info * info)5006 static int adapter_test(struct slgt_info *info)
5007 {
5008 DBGINFO(("testing %s\n", info->device_name));
5009 if (register_test(info) < 0) {
5010 printk("register test failure %s addr=%08X\n",
5011 info->device_name, info->phys_reg_addr);
5012 } else if (irq_test(info) < 0) {
5013 printk("IRQ test failure %s IRQ=%d\n",
5014 info->device_name, info->irq_level);
5015 } else if (loopback_test(info) < 0) {
5016 printk("loopback test failure %s\n", info->device_name);
5017 }
5018 return info->init_error;
5019 }
5020
5021 /*
5022 * transmit timeout handler
5023 */
tx_timeout(struct timer_list * t)5024 static void tx_timeout(struct timer_list *t)
5025 {
5026 struct slgt_info *info = from_timer(info, t, tx_timer);
5027 unsigned long flags;
5028
5029 DBGINFO(("%s tx_timeout\n", info->device_name));
5030 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5031 info->icount.txtimeout++;
5032 }
5033 spin_lock_irqsave(&info->lock,flags);
5034 tx_stop(info);
5035 spin_unlock_irqrestore(&info->lock,flags);
5036
5037 #if SYNCLINK_GENERIC_HDLC
5038 if (info->netcount)
5039 hdlcdev_tx_done(info);
5040 else
5041 #endif
5042 bh_transmit(info);
5043 }
5044
5045 /*
5046 * receive buffer polling timer
5047 */
rx_timeout(struct timer_list * t)5048 static void rx_timeout(struct timer_list *t)
5049 {
5050 struct slgt_info *info = from_timer(info, t, rx_timer);
5051 unsigned long flags;
5052
5053 DBGINFO(("%s rx_timeout\n", info->device_name));
5054 spin_lock_irqsave(&info->lock, flags);
5055 info->pending_bh |= BH_RECEIVE;
5056 spin_unlock_irqrestore(&info->lock, flags);
5057 bh_handler(&info->task);
5058 }
5059
5060