1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de>
4 * Copyright (C) 2015 Imagination Technologies
5 *
6 * Ingenic SoC UART support
7 */
8
9 #include <linux/clk.h>
10 #include <linux/console.h>
11 #include <linux/io.h>
12 #include <linux/libfdt.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_fdt.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/serial_8250.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial_reg.h>
21
22 #include "8250.h"
23
24 /** ingenic_uart_config: SOC specific config data. */
25 struct ingenic_uart_config {
26 int tx_loadsz;
27 int fifosize;
28 };
29
30 struct ingenic_uart_data {
31 struct clk *clk_module;
32 struct clk *clk_baud;
33 int line;
34 };
35
36 static const struct of_device_id of_match[];
37
38 #define UART_FCR_UME BIT(4)
39
40 #define UART_MCR_MDCE BIT(7)
41 #define UART_MCR_FCM BIT(6)
42
43 static struct earlycon_device *early_device;
44
early_in(struct uart_port * port,int offset)45 static uint8_t early_in(struct uart_port *port, int offset)
46 {
47 return readl(port->membase + (offset << 2));
48 }
49
early_out(struct uart_port * port,int offset,uint8_t value)50 static void early_out(struct uart_port *port, int offset, uint8_t value)
51 {
52 writel(value, port->membase + (offset << 2));
53 }
54
ingenic_early_console_putc(struct uart_port * port,int c)55 static void ingenic_early_console_putc(struct uart_port *port, int c)
56 {
57 uint8_t lsr;
58
59 do {
60 lsr = early_in(port, UART_LSR);
61 } while ((lsr & UART_LSR_TEMT) == 0);
62
63 early_out(port, UART_TX, c);
64 }
65
ingenic_early_console_write(struct console * console,const char * s,unsigned int count)66 static void ingenic_early_console_write(struct console *console,
67 const char *s, unsigned int count)
68 {
69 uart_console_write(&early_device->port, s, count,
70 ingenic_early_console_putc);
71 }
72
ingenic_early_console_setup_clock(struct earlycon_device * dev)73 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev)
74 {
75 void *fdt = initial_boot_params;
76 const __be32 *prop;
77 int offset;
78
79 offset = fdt_path_offset(fdt, "/ext");
80 if (offset < 0)
81 return;
82
83 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL);
84 if (!prop)
85 return;
86
87 dev->port.uartclk = be32_to_cpup(prop);
88 }
89
ingenic_early_console_setup(struct earlycon_device * dev,const char * opt)90 static int __init ingenic_early_console_setup(struct earlycon_device *dev,
91 const char *opt)
92 {
93 struct uart_port *port = &dev->port;
94 unsigned int divisor;
95 int baud = 115200;
96
97 if (!dev->port.membase)
98 return -ENODEV;
99
100 if (opt) {
101 unsigned int parity, bits, flow; /* unused for now */
102
103 uart_parse_options(opt, &baud, &parity, &bits, &flow);
104 }
105
106 ingenic_early_console_setup_clock(dev);
107
108 if (dev->baud)
109 baud = dev->baud;
110 divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud);
111
112 early_out(port, UART_IER, 0);
113 early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
114 early_out(port, UART_DLL, 0);
115 early_out(port, UART_DLM, 0);
116 early_out(port, UART_LCR, UART_LCR_WLEN8);
117 early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT |
118 UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO);
119 early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR);
120
121 early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8);
122 early_out(port, UART_DLL, divisor & 0xff);
123 early_out(port, UART_DLM, (divisor >> 8) & 0xff);
124 early_out(port, UART_LCR, UART_LCR_WLEN8);
125
126 early_device = dev;
127 dev->con->write = ingenic_early_console_write;
128
129 return 0;
130 }
131
132 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
133 ingenic_early_console_setup);
134
135 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
136 ingenic_early_console_setup);
137
138 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
139 ingenic_early_console_setup);
140
141 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
142 ingenic_early_console_setup);
143
144 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
145 ingenic_early_console_setup);
146
ingenic_uart_serial_out(struct uart_port * p,int offset,int value)147 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value)
148 {
149 int ier;
150
151 switch (offset) {
152 case UART_FCR:
153 /* UART module enable */
154 value |= UART_FCR_UME;
155 break;
156
157 case UART_IER:
158 /*
159 * Enable receive timeout interrupt with the receive line
160 * status interrupt.
161 */
162 value |= (value & 0x4) << 2;
163 break;
164
165 case UART_MCR:
166 /*
167 * If we have enabled modem status IRQs we should enable
168 * modem mode.
169 */
170 ier = p->serial_in(p, UART_IER);
171
172 if (ier & UART_IER_MSI)
173 value |= UART_MCR_MDCE | UART_MCR_FCM;
174 else
175 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
176 break;
177
178 default:
179 break;
180 }
181
182 writeb(value, p->membase + (offset << p->regshift));
183 }
184
ingenic_uart_serial_in(struct uart_port * p,int offset)185 static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset)
186 {
187 unsigned int value;
188
189 value = readb(p->membase + (offset << p->regshift));
190
191 /* Hide non-16550 compliant bits from higher levels */
192 switch (offset) {
193 case UART_FCR:
194 value &= ~UART_FCR_UME;
195 break;
196
197 case UART_MCR:
198 value &= ~(UART_MCR_MDCE | UART_MCR_FCM);
199 break;
200
201 default:
202 break;
203 }
204 return value;
205 }
206
ingenic_uart_probe(struct platform_device * pdev)207 static int ingenic_uart_probe(struct platform_device *pdev)
208 {
209 struct uart_8250_port uart = {};
210 struct ingenic_uart_data *data;
211 const struct ingenic_uart_config *cdata;
212 struct resource *regs;
213 int irq, err, line;
214
215 cdata = of_device_get_match_data(&pdev->dev);
216 if (!cdata) {
217 dev_err(&pdev->dev, "Error: No device match found\n");
218 return -ENODEV;
219 }
220
221 irq = platform_get_irq(pdev, 0);
222 if (irq < 0)
223 return irq;
224
225 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
226 if (!regs) {
227 dev_err(&pdev->dev, "no registers defined\n");
228 return -EINVAL;
229 }
230
231 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
232 if (!data)
233 return -ENOMEM;
234
235 spin_lock_init(&uart.port.lock);
236 uart.port.type = PORT_16550A;
237 uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
238 uart.port.iotype = UPIO_MEM;
239 uart.port.mapbase = regs->start;
240 uart.port.regshift = 2;
241 uart.port.serial_out = ingenic_uart_serial_out;
242 uart.port.serial_in = ingenic_uart_serial_in;
243 uart.port.irq = irq;
244 uart.port.dev = &pdev->dev;
245 uart.port.fifosize = cdata->fifosize;
246 uart.tx_loadsz = cdata->tx_loadsz;
247 uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
248
249 /* Check for a fixed line number */
250 line = of_alias_get_id(pdev->dev.of_node, "serial");
251 if (line >= 0)
252 uart.port.line = line;
253
254 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
255 resource_size(regs));
256 if (!uart.port.membase)
257 return -ENOMEM;
258
259 data->clk_module = devm_clk_get(&pdev->dev, "module");
260 if (IS_ERR(data->clk_module))
261 return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_module),
262 "unable to get module clock\n");
263
264 data->clk_baud = devm_clk_get(&pdev->dev, "baud");
265 if (IS_ERR(data->clk_baud))
266 return dev_err_probe(&pdev->dev, PTR_ERR(data->clk_baud),
267 "unable to get baud clock\n");
268
269 err = clk_prepare_enable(data->clk_module);
270 if (err) {
271 dev_err(&pdev->dev, "could not enable module clock: %d\n", err);
272 goto out;
273 }
274
275 err = clk_prepare_enable(data->clk_baud);
276 if (err) {
277 dev_err(&pdev->dev, "could not enable baud clock: %d\n", err);
278 goto out_disable_moduleclk;
279 }
280 uart.port.uartclk = clk_get_rate(data->clk_baud);
281
282 data->line = serial8250_register_8250_port(&uart);
283 if (data->line < 0) {
284 err = data->line;
285 goto out_disable_baudclk;
286 }
287
288 platform_set_drvdata(pdev, data);
289 return 0;
290
291 out_disable_baudclk:
292 clk_disable_unprepare(data->clk_baud);
293 out_disable_moduleclk:
294 clk_disable_unprepare(data->clk_module);
295 out:
296 return err;
297 }
298
ingenic_uart_remove(struct platform_device * pdev)299 static int ingenic_uart_remove(struct platform_device *pdev)
300 {
301 struct ingenic_uart_data *data = platform_get_drvdata(pdev);
302
303 serial8250_unregister_port(data->line);
304 clk_disable_unprepare(data->clk_module);
305 clk_disable_unprepare(data->clk_baud);
306 return 0;
307 }
308
309 static const struct ingenic_uart_config jz4740_uart_config = {
310 .tx_loadsz = 8,
311 .fifosize = 16,
312 };
313
314 static const struct ingenic_uart_config jz4760_uart_config = {
315 .tx_loadsz = 16,
316 .fifosize = 32,
317 };
318
319 static const struct ingenic_uart_config jz4780_uart_config = {
320 .tx_loadsz = 32,
321 .fifosize = 64,
322 };
323
324 static const struct ingenic_uart_config x1000_uart_config = {
325 .tx_loadsz = 32,
326 .fifosize = 64,
327 };
328
329 static const struct of_device_id of_match[] = {
330 { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
331 { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
332 { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
333 { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
334 { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
335 { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
336 { /* sentinel */ }
337 };
338 MODULE_DEVICE_TABLE(of, of_match);
339
340 static struct platform_driver ingenic_uart_platform_driver = {
341 .driver = {
342 .name = "ingenic-uart",
343 .of_match_table = of_match,
344 },
345 .probe = ingenic_uart_probe,
346 .remove = ingenic_uart_remove,
347 };
348
349 module_platform_driver(ingenic_uart_platform_driver);
350
351 MODULE_AUTHOR("Paul Burton");
352 MODULE_LICENSE("GPL");
353 MODULE_DESCRIPTION("Ingenic SoC UART driver");
354
