1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Addy Ke <addy.ke@rock-chips.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/dmaengine.h>
9 #include <linux/interrupt.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/pinctrl/consumer.h>
13 #include <linux/platform_device.h>
14 #include <linux/spi/spi.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/scatterlist.h>
17
18 #define DRIVER_NAME "rockchip-spi"
19
20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \
21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg)
22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \
23 writel_relaxed(readl_relaxed(reg) | (bits), reg)
24
25 /* SPI register offsets */
26 #define ROCKCHIP_SPI_CTRLR0 0x0000
27 #define ROCKCHIP_SPI_CTRLR1 0x0004
28 #define ROCKCHIP_SPI_SSIENR 0x0008
29 #define ROCKCHIP_SPI_SER 0x000c
30 #define ROCKCHIP_SPI_BAUDR 0x0010
31 #define ROCKCHIP_SPI_TXFTLR 0x0014
32 #define ROCKCHIP_SPI_RXFTLR 0x0018
33 #define ROCKCHIP_SPI_TXFLR 0x001c
34 #define ROCKCHIP_SPI_RXFLR 0x0020
35 #define ROCKCHIP_SPI_SR 0x0024
36 #define ROCKCHIP_SPI_IPR 0x0028
37 #define ROCKCHIP_SPI_IMR 0x002c
38 #define ROCKCHIP_SPI_ISR 0x0030
39 #define ROCKCHIP_SPI_RISR 0x0034
40 #define ROCKCHIP_SPI_ICR 0x0038
41 #define ROCKCHIP_SPI_DMACR 0x003c
42 #define ROCKCHIP_SPI_DMATDLR 0x0040
43 #define ROCKCHIP_SPI_DMARDLR 0x0044
44 #define ROCKCHIP_SPI_VERSION 0x0048
45 #define ROCKCHIP_SPI_TXDR 0x0400
46 #define ROCKCHIP_SPI_RXDR 0x0800
47
48 /* Bit fields in CTRLR0 */
49 #define CR0_DFS_OFFSET 0
50 #define CR0_DFS_4BIT 0x0
51 #define CR0_DFS_8BIT 0x1
52 #define CR0_DFS_16BIT 0x2
53
54 #define CR0_CFS_OFFSET 2
55
56 #define CR0_SCPH_OFFSET 6
57
58 #define CR0_SCPOL_OFFSET 7
59
60 #define CR0_CSM_OFFSET 8
61 #define CR0_CSM_KEEP 0x0
62 /* ss_n be high for half sclk_out cycles */
63 #define CR0_CSM_HALF 0X1
64 /* ss_n be high for one sclk_out cycle */
65 #define CR0_CSM_ONE 0x2
66
67 /* ss_n to sclk_out delay */
68 #define CR0_SSD_OFFSET 10
69 /*
70 * The period between ss_n active and
71 * sclk_out active is half sclk_out cycles
72 */
73 #define CR0_SSD_HALF 0x0
74 /*
75 * The period between ss_n active and
76 * sclk_out active is one sclk_out cycle
77 */
78 #define CR0_SSD_ONE 0x1
79
80 #define CR0_EM_OFFSET 11
81 #define CR0_EM_LITTLE 0x0
82 #define CR0_EM_BIG 0x1
83
84 #define CR0_FBM_OFFSET 12
85 #define CR0_FBM_MSB 0x0
86 #define CR0_FBM_LSB 0x1
87
88 #define CR0_BHT_OFFSET 13
89 #define CR0_BHT_16BIT 0x0
90 #define CR0_BHT_8BIT 0x1
91
92 #define CR0_RSD_OFFSET 14
93 #define CR0_RSD_MAX 0x3
94
95 #define CR0_FRF_OFFSET 16
96 #define CR0_FRF_SPI 0x0
97 #define CR0_FRF_SSP 0x1
98 #define CR0_FRF_MICROWIRE 0x2
99
100 #define CR0_XFM_OFFSET 18
101 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
102 #define CR0_XFM_TR 0x0
103 #define CR0_XFM_TO 0x1
104 #define CR0_XFM_RO 0x2
105
106 #define CR0_OPM_OFFSET 20
107 #define CR0_OPM_MASTER 0x0
108 #define CR0_OPM_SLAVE 0x1
109
110 #define CR0_SOI_OFFSET 23
111
112 #define CR0_MTM_OFFSET 0x21
113
114 /* Bit fields in SER, 2bit */
115 #define SER_MASK 0x3
116
117 /* Bit fields in BAUDR */
118 #define BAUDR_SCKDV_MIN 2
119 #define BAUDR_SCKDV_MAX 65534
120
121 /* Bit fields in SR, 6bit */
122 #define SR_MASK 0x3f
123 #define SR_BUSY (1 << 0)
124 #define SR_TF_FULL (1 << 1)
125 #define SR_TF_EMPTY (1 << 2)
126 #define SR_RF_EMPTY (1 << 3)
127 #define SR_RF_FULL (1 << 4)
128 #define SR_SLAVE_TX_BUSY (1 << 5)
129
130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
131 #define INT_MASK 0x1f
132 #define INT_TF_EMPTY (1 << 0)
133 #define INT_TF_OVERFLOW (1 << 1)
134 #define INT_RF_UNDERFLOW (1 << 2)
135 #define INT_RF_OVERFLOW (1 << 3)
136 #define INT_RF_FULL (1 << 4)
137
138 /* Bit fields in ICR, 4bit */
139 #define ICR_MASK 0x0f
140 #define ICR_ALL (1 << 0)
141 #define ICR_RF_UNDERFLOW (1 << 1)
142 #define ICR_RF_OVERFLOW (1 << 2)
143 #define ICR_TF_OVERFLOW (1 << 3)
144
145 /* Bit fields in DMACR */
146 #define RF_DMA_EN (1 << 0)
147 #define TF_DMA_EN (1 << 1)
148
149 /* Driver state flags */
150 #define RXDMA (1 << 0)
151 #define TXDMA (1 << 1)
152
153 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
154 #define MAX_SCLK_OUT 50000000U
155
156 /*
157 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
158 * the controller seems to hang when given 0x10000, so stick with this for now.
159 */
160 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff
161
162 /* 2 for native cs, 2 for cs-gpio */
163 #define ROCKCHIP_SPI_MAX_CS_NUM 4
164 #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002
165 #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002
166
167 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT 2000
168
169 struct rockchip_spi {
170 struct device *dev;
171
172 struct clk *spiclk;
173 struct clk *apb_pclk;
174
175 void __iomem *regs;
176 dma_addr_t dma_addr_rx;
177 dma_addr_t dma_addr_tx;
178
179 const void *tx;
180 void *rx;
181 unsigned int tx_left;
182 unsigned int rx_left;
183
184 atomic_t state;
185
186 /*depth of the FIFO buffer */
187 u32 fifo_len;
188 /* frequency of spiclk */
189 u32 freq;
190
191 u8 n_bytes;
192 u8 rsd;
193
194 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
195
196 bool slave_abort;
197 };
198
spi_enable_chip(struct rockchip_spi * rs,bool enable)199 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
200 {
201 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
202 }
203
wait_for_tx_idle(struct rockchip_spi * rs,bool slave_mode)204 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool slave_mode)
205 {
206 unsigned long timeout = jiffies + msecs_to_jiffies(5);
207
208 do {
209 if (slave_mode) {
210 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_SLAVE_TX_BUSY) &&
211 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)))
212 return;
213 } else {
214 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
215 return;
216 }
217 } while (!time_after(jiffies, timeout));
218
219 dev_warn(rs->dev, "spi controller is in busy state!\n");
220 }
221
get_fifo_len(struct rockchip_spi * rs)222 static u32 get_fifo_len(struct rockchip_spi *rs)
223 {
224 u32 ver;
225
226 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION);
227
228 switch (ver) {
229 case ROCKCHIP_SPI_VER2_TYPE1:
230 case ROCKCHIP_SPI_VER2_TYPE2:
231 return 64;
232 default:
233 return 32;
234 }
235 }
236
rockchip_spi_set_cs(struct spi_device * spi,bool enable)237 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
238 {
239 struct spi_controller *ctlr = spi->controller;
240 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
241 bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable;
242
243 /* Return immediately for no-op */
244 if (cs_asserted == rs->cs_asserted[spi->chip_select])
245 return;
246
247 if (cs_asserted) {
248 /* Keep things powered as long as CS is asserted */
249 pm_runtime_get_sync(rs->dev);
250
251 if (spi->cs_gpiod)
252 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
253 else
254 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
255 } else {
256 if (spi->cs_gpiod)
257 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1);
258 else
259 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, BIT(spi->chip_select));
260
261 /* Drop reference from when we first asserted CS */
262 pm_runtime_put(rs->dev);
263 }
264
265 rs->cs_asserted[spi->chip_select] = cs_asserted;
266 }
267
rockchip_spi_handle_err(struct spi_controller * ctlr,struct spi_message * msg)268 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
269 struct spi_message *msg)
270 {
271 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
272
273 /* stop running spi transfer
274 * this also flushes both rx and tx fifos
275 */
276 spi_enable_chip(rs, false);
277
278 /* make sure all interrupts are masked */
279 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
280
281 if (atomic_read(&rs->state) & TXDMA)
282 dmaengine_terminate_async(ctlr->dma_tx);
283
284 if (atomic_read(&rs->state) & RXDMA)
285 dmaengine_terminate_async(ctlr->dma_rx);
286 }
287
rockchip_spi_pio_writer(struct rockchip_spi * rs)288 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
289 {
290 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
291 u32 words = min(rs->tx_left, tx_free);
292
293 rs->tx_left -= words;
294 for (; words; words--) {
295 u32 txw;
296
297 if (rs->n_bytes == 1)
298 txw = *(u8 *)rs->tx;
299 else
300 txw = *(u16 *)rs->tx;
301
302 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
303 rs->tx += rs->n_bytes;
304 }
305 }
306
rockchip_spi_pio_reader(struct rockchip_spi * rs)307 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
308 {
309 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
310 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0;
311
312 /* the hardware doesn't allow us to change fifo threshold
313 * level while spi is enabled, so instead make sure to leave
314 * enough words in the rx fifo to get the last interrupt
315 * exactly when all words have been received
316 */
317 if (rx_left) {
318 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1;
319
320 if (rx_left < ftl) {
321 rx_left = ftl;
322 words = rs->rx_left - rx_left;
323 }
324 }
325
326 rs->rx_left = rx_left;
327 for (; words; words--) {
328 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
329
330 if (!rs->rx)
331 continue;
332
333 if (rs->n_bytes == 1)
334 *(u8 *)rs->rx = (u8)rxw;
335 else
336 *(u16 *)rs->rx = (u16)rxw;
337 rs->rx += rs->n_bytes;
338 }
339 }
340
rockchip_spi_isr(int irq,void * dev_id)341 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
342 {
343 struct spi_controller *ctlr = dev_id;
344 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
345
346 if (rs->tx_left)
347 rockchip_spi_pio_writer(rs);
348
349 rockchip_spi_pio_reader(rs);
350 if (!rs->rx_left) {
351 spi_enable_chip(rs, false);
352 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
353 spi_finalize_current_transfer(ctlr);
354 }
355
356 return IRQ_HANDLED;
357 }
358
rockchip_spi_prepare_irq(struct rockchip_spi * rs,struct spi_transfer * xfer)359 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs,
360 struct spi_transfer *xfer)
361 {
362 rs->tx = xfer->tx_buf;
363 rs->rx = xfer->rx_buf;
364 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
365 rs->rx_left = xfer->len / rs->n_bytes;
366
367 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR);
368 spi_enable_chip(rs, true);
369
370 if (rs->tx_left)
371 rockchip_spi_pio_writer(rs);
372
373 /* 1 means the transfer is in progress */
374 return 1;
375 }
376
rockchip_spi_dma_rxcb(void * data)377 static void rockchip_spi_dma_rxcb(void *data)
378 {
379 struct spi_controller *ctlr = data;
380 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
381 int state = atomic_fetch_andnot(RXDMA, &rs->state);
382
383 if (state & TXDMA && !rs->slave_abort)
384 return;
385
386 spi_enable_chip(rs, false);
387 spi_finalize_current_transfer(ctlr);
388 }
389
rockchip_spi_dma_txcb(void * data)390 static void rockchip_spi_dma_txcb(void *data)
391 {
392 struct spi_controller *ctlr = data;
393 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
394 int state = atomic_fetch_andnot(TXDMA, &rs->state);
395
396 if (state & RXDMA && !rs->slave_abort)
397 return;
398
399 /* Wait until the FIFO data completely. */
400 wait_for_tx_idle(rs, ctlr->slave);
401
402 spi_enable_chip(rs, false);
403 spi_finalize_current_transfer(ctlr);
404 }
405
rockchip_spi_calc_burst_size(u32 data_len)406 static u32 rockchip_spi_calc_burst_size(u32 data_len)
407 {
408 u32 i;
409
410 /* burst size: 1, 2, 4, 8 */
411 for (i = 1; i < 8; i <<= 1) {
412 if (data_len & i)
413 break;
414 }
415
416 return i;
417 }
418
rockchip_spi_prepare_dma(struct rockchip_spi * rs,struct spi_controller * ctlr,struct spi_transfer * xfer)419 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs,
420 struct spi_controller *ctlr, struct spi_transfer *xfer)
421 {
422 struct dma_async_tx_descriptor *rxdesc, *txdesc;
423
424 atomic_set(&rs->state, 0);
425
426 rxdesc = NULL;
427 if (xfer->rx_buf) {
428 struct dma_slave_config rxconf = {
429 .direction = DMA_DEV_TO_MEM,
430 .src_addr = rs->dma_addr_rx,
431 .src_addr_width = rs->n_bytes,
432 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len /
433 rs->n_bytes),
434 };
435
436 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
437
438 rxdesc = dmaengine_prep_slave_sg(
439 ctlr->dma_rx,
440 xfer->rx_sg.sgl, xfer->rx_sg.nents,
441 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
442 if (!rxdesc)
443 return -EINVAL;
444
445 rxdesc->callback = rockchip_spi_dma_rxcb;
446 rxdesc->callback_param = ctlr;
447 }
448
449 txdesc = NULL;
450 if (xfer->tx_buf) {
451 struct dma_slave_config txconf = {
452 .direction = DMA_MEM_TO_DEV,
453 .dst_addr = rs->dma_addr_tx,
454 .dst_addr_width = rs->n_bytes,
455 .dst_maxburst = rs->fifo_len / 4,
456 };
457
458 dmaengine_slave_config(ctlr->dma_tx, &txconf);
459
460 txdesc = dmaengine_prep_slave_sg(
461 ctlr->dma_tx,
462 xfer->tx_sg.sgl, xfer->tx_sg.nents,
463 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
464 if (!txdesc) {
465 if (rxdesc)
466 dmaengine_terminate_sync(ctlr->dma_rx);
467 return -EINVAL;
468 }
469
470 txdesc->callback = rockchip_spi_dma_txcb;
471 txdesc->callback_param = ctlr;
472 }
473
474 /* rx must be started before tx due to spi instinct */
475 if (rxdesc) {
476 atomic_or(RXDMA, &rs->state);
477 dmaengine_submit(rxdesc);
478 dma_async_issue_pending(ctlr->dma_rx);
479 }
480
481 spi_enable_chip(rs, true);
482
483 if (txdesc) {
484 atomic_or(TXDMA, &rs->state);
485 dmaengine_submit(txdesc);
486 dma_async_issue_pending(ctlr->dma_tx);
487 }
488
489 /* 1 means the transfer is in progress */
490 return 1;
491 }
492
rockchip_spi_config(struct rockchip_spi * rs,struct spi_device * spi,struct spi_transfer * xfer,bool use_dma,bool slave_mode)493 static int rockchip_spi_config(struct rockchip_spi *rs,
494 struct spi_device *spi, struct spi_transfer *xfer,
495 bool use_dma, bool slave_mode)
496 {
497 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET
498 | CR0_BHT_8BIT << CR0_BHT_OFFSET
499 | CR0_SSD_ONE << CR0_SSD_OFFSET
500 | CR0_EM_BIG << CR0_EM_OFFSET;
501 u32 cr1;
502 u32 dmacr = 0;
503
504 if (slave_mode)
505 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET;
506 rs->slave_abort = false;
507
508 cr0 |= rs->rsd << CR0_RSD_OFFSET;
509 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
510 if (spi->mode & SPI_LSB_FIRST)
511 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET;
512 if (spi->mode & SPI_CS_HIGH)
513 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;
514
515 if (xfer->rx_buf && xfer->tx_buf)
516 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET;
517 else if (xfer->rx_buf)
518 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET;
519 else if (use_dma)
520 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET;
521
522 switch (xfer->bits_per_word) {
523 case 4:
524 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET;
525 cr1 = xfer->len - 1;
526 break;
527 case 8:
528 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET;
529 cr1 = xfer->len - 1;
530 break;
531 case 16:
532 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET;
533 cr1 = xfer->len / 2 - 1;
534 break;
535 default:
536 /* we only whitelist 4, 8 and 16 bit words in
537 * ctlr->bits_per_word_mask, so this shouldn't
538 * happen
539 */
540 dev_err(rs->dev, "unknown bits per word: %d\n",
541 xfer->bits_per_word);
542 return -EINVAL;
543 }
544
545 if (use_dma) {
546 if (xfer->tx_buf)
547 dmacr |= TF_DMA_EN;
548 if (xfer->rx_buf)
549 dmacr |= RF_DMA_EN;
550 }
551
552 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
553 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1);
554
555 /* unfortunately setting the fifo threshold level to generate an
556 * interrupt exactly when the fifo is full doesn't seem to work,
557 * so we need the strict inequality here
558 */
559 if ((xfer->len / rs->n_bytes) < rs->fifo_len)
560 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
561 else
562 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
563
564 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR);
565 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1,
566 rs->regs + ROCKCHIP_SPI_DMARDLR);
567 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
568
569 /* the hardware only supports an even clock divisor, so
570 * round divisor = spiclk / speed up to nearest even number
571 * so that the resulting speed is <= the requested speed
572 */
573 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz),
574 rs->regs + ROCKCHIP_SPI_BAUDR);
575
576 return 0;
577 }
578
rockchip_spi_max_transfer_size(struct spi_device * spi)579 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
580 {
581 return ROCKCHIP_SPI_MAX_TRANLEN;
582 }
583
rockchip_spi_slave_abort(struct spi_controller * ctlr)584 static int rockchip_spi_slave_abort(struct spi_controller *ctlr)
585 {
586 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
587
588 rs->slave_abort = true;
589 spi_finalize_current_transfer(ctlr);
590
591 return 0;
592 }
593
rockchip_spi_transfer_one(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)594 static int rockchip_spi_transfer_one(
595 struct spi_controller *ctlr,
596 struct spi_device *spi,
597 struct spi_transfer *xfer)
598 {
599 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
600 int ret;
601 bool use_dma;
602
603 /* Zero length transfers won't trigger an interrupt on completion */
604 if (!xfer->len) {
605 spi_finalize_current_transfer(ctlr);
606 return 1;
607 }
608
609 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
610 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
611
612 if (!xfer->tx_buf && !xfer->rx_buf) {
613 dev_err(rs->dev, "No buffer for transfer\n");
614 return -EINVAL;
615 }
616
617 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
618 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
619 return -EINVAL;
620 }
621
622 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2;
623
624 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
625
626 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave);
627 if (ret)
628 return ret;
629
630 if (use_dma)
631 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
632
633 return rockchip_spi_prepare_irq(rs, xfer);
634 }
635
rockchip_spi_can_dma(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * xfer)636 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
637 struct spi_device *spi,
638 struct spi_transfer *xfer)
639 {
640 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
641 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2;
642
643 /* if the numbor of spi words to transfer is less than the fifo
644 * length we can just fill the fifo and wait for a single irq,
645 * so don't bother setting up dma
646 */
647 return xfer->len / bytes_per_word >= rs->fifo_len;
648 }
649
rockchip_spi_probe(struct platform_device * pdev)650 static int rockchip_spi_probe(struct platform_device *pdev)
651 {
652 int ret;
653 struct rockchip_spi *rs;
654 struct spi_controller *ctlr;
655 struct resource *mem;
656 struct device_node *np = pdev->dev.of_node;
657 u32 rsd_nsecs;
658 bool slave_mode;
659
660 slave_mode = of_property_read_bool(np, "spi-slave");
661
662 if (slave_mode)
663 ctlr = spi_alloc_slave(&pdev->dev,
664 sizeof(struct rockchip_spi));
665 else
666 ctlr = spi_alloc_master(&pdev->dev,
667 sizeof(struct rockchip_spi));
668
669 if (!ctlr)
670 return -ENOMEM;
671
672 platform_set_drvdata(pdev, ctlr);
673
674 rs = spi_controller_get_devdata(ctlr);
675 ctlr->slave = slave_mode;
676
677 /* Get basic io resource and map it */
678 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
679 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
680 if (IS_ERR(rs->regs)) {
681 ret = PTR_ERR(rs->regs);
682 goto err_put_ctlr;
683 }
684
685 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
686 if (IS_ERR(rs->apb_pclk)) {
687 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
688 ret = PTR_ERR(rs->apb_pclk);
689 goto err_put_ctlr;
690 }
691
692 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
693 if (IS_ERR(rs->spiclk)) {
694 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
695 ret = PTR_ERR(rs->spiclk);
696 goto err_put_ctlr;
697 }
698
699 ret = clk_prepare_enable(rs->apb_pclk);
700 if (ret < 0) {
701 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
702 goto err_put_ctlr;
703 }
704
705 ret = clk_prepare_enable(rs->spiclk);
706 if (ret < 0) {
707 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
708 goto err_disable_apbclk;
709 }
710
711 spi_enable_chip(rs, false);
712
713 ret = platform_get_irq(pdev, 0);
714 if (ret < 0)
715 goto err_disable_spiclk;
716
717 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL,
718 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
719 if (ret)
720 goto err_disable_spiclk;
721
722 rs->dev = &pdev->dev;
723 rs->freq = clk_get_rate(rs->spiclk);
724
725 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
726 &rsd_nsecs)) {
727 /* rx sample delay is expressed in parent clock cycles (max 3) */
728 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8),
729 1000000000 >> 8);
730 if (!rsd) {
731 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n",
732 rs->freq, rsd_nsecs);
733 } else if (rsd > CR0_RSD_MAX) {
734 rsd = CR0_RSD_MAX;
735 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n",
736 rs->freq, rsd_nsecs,
737 CR0_RSD_MAX * 1000000000U / rs->freq);
738 }
739 rs->rsd = rsd;
740 }
741
742 rs->fifo_len = get_fifo_len(rs);
743 if (!rs->fifo_len) {
744 dev_err(&pdev->dev, "Failed to get fifo length\n");
745 ret = -EINVAL;
746 goto err_disable_spiclk;
747 }
748
749 pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT);
750 pm_runtime_use_autosuspend(&pdev->dev);
751 pm_runtime_set_active(&pdev->dev);
752 pm_runtime_enable(&pdev->dev);
753
754 ctlr->auto_runtime_pm = true;
755 ctlr->bus_num = pdev->id;
756 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
757 if (slave_mode) {
758 ctlr->mode_bits |= SPI_NO_CS;
759 ctlr->slave_abort = rockchip_spi_slave_abort;
760 } else {
761 ctlr->flags = SPI_MASTER_GPIO_SS;
762 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
763 /*
764 * rk spi0 has two native cs, spi1..5 one cs only
765 * if num-cs is missing in the dts, default to 1
766 */
767 if (of_property_read_u16(np, "num-cs", &ctlr->num_chipselect))
768 ctlr->num_chipselect = 1;
769 ctlr->use_gpio_descriptors = true;
770 }
771 ctlr->dev.of_node = pdev->dev.of_node;
772 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
773 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
774 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
775
776 ctlr->set_cs = rockchip_spi_set_cs;
777 ctlr->transfer_one = rockchip_spi_transfer_one;
778 ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
779 ctlr->handle_err = rockchip_spi_handle_err;
780
781 ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
782 if (IS_ERR(ctlr->dma_tx)) {
783 /* Check tx to see if we need defer probing driver */
784 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
785 ret = -EPROBE_DEFER;
786 goto err_disable_pm_runtime;
787 }
788 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
789 ctlr->dma_tx = NULL;
790 }
791
792 ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
793 if (IS_ERR(ctlr->dma_rx)) {
794 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
795 ret = -EPROBE_DEFER;
796 goto err_free_dma_tx;
797 }
798 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
799 ctlr->dma_rx = NULL;
800 }
801
802 if (ctlr->dma_tx && ctlr->dma_rx) {
803 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
804 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
805 ctlr->can_dma = rockchip_spi_can_dma;
806 }
807
808 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
809 case ROCKCHIP_SPI_VER2_TYPE2:
810 ctlr->mode_bits |= SPI_CS_HIGH;
811 break;
812 default:
813 break;
814 }
815
816 ret = devm_spi_register_controller(&pdev->dev, ctlr);
817 if (ret < 0) {
818 dev_err(&pdev->dev, "Failed to register controller\n");
819 goto err_free_dma_rx;
820 }
821
822 return 0;
823
824 err_free_dma_rx:
825 if (ctlr->dma_rx)
826 dma_release_channel(ctlr->dma_rx);
827 err_free_dma_tx:
828 if (ctlr->dma_tx)
829 dma_release_channel(ctlr->dma_tx);
830 err_disable_pm_runtime:
831 pm_runtime_disable(&pdev->dev);
832 err_disable_spiclk:
833 clk_disable_unprepare(rs->spiclk);
834 err_disable_apbclk:
835 clk_disable_unprepare(rs->apb_pclk);
836 err_put_ctlr:
837 spi_controller_put(ctlr);
838
839 return ret;
840 }
841
rockchip_spi_remove(struct platform_device * pdev)842 static int rockchip_spi_remove(struct platform_device *pdev)
843 {
844 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
845 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
846
847 pm_runtime_get_sync(&pdev->dev);
848
849 clk_disable_unprepare(rs->spiclk);
850 clk_disable_unprepare(rs->apb_pclk);
851
852 pm_runtime_put_noidle(&pdev->dev);
853 pm_runtime_disable(&pdev->dev);
854 pm_runtime_set_suspended(&pdev->dev);
855
856 if (ctlr->dma_tx)
857 dma_release_channel(ctlr->dma_tx);
858 if (ctlr->dma_rx)
859 dma_release_channel(ctlr->dma_rx);
860
861 spi_controller_put(ctlr);
862
863 return 0;
864 }
865
866 #ifdef CONFIG_PM_SLEEP
rockchip_spi_suspend(struct device * dev)867 static int rockchip_spi_suspend(struct device *dev)
868 {
869 int ret;
870 struct spi_controller *ctlr = dev_get_drvdata(dev);
871
872 ret = spi_controller_suspend(ctlr);
873 if (ret < 0)
874 return ret;
875
876 ret = pm_runtime_force_suspend(dev);
877 if (ret < 0)
878 return ret;
879
880 pinctrl_pm_select_sleep_state(dev);
881
882 return 0;
883 }
884
rockchip_spi_resume(struct device * dev)885 static int rockchip_spi_resume(struct device *dev)
886 {
887 int ret;
888 struct spi_controller *ctlr = dev_get_drvdata(dev);
889 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
890
891 pinctrl_pm_select_default_state(dev);
892
893 ret = pm_runtime_force_resume(dev);
894 if (ret < 0)
895 return ret;
896
897 ret = spi_controller_resume(ctlr);
898 if (ret < 0) {
899 clk_disable_unprepare(rs->spiclk);
900 clk_disable_unprepare(rs->apb_pclk);
901 }
902
903 return 0;
904 }
905 #endif /* CONFIG_PM_SLEEP */
906
907 #ifdef CONFIG_PM
rockchip_spi_runtime_suspend(struct device * dev)908 static int rockchip_spi_runtime_suspend(struct device *dev)
909 {
910 struct spi_controller *ctlr = dev_get_drvdata(dev);
911 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
912
913 clk_disable_unprepare(rs->spiclk);
914 clk_disable_unprepare(rs->apb_pclk);
915
916 return 0;
917 }
918
rockchip_spi_runtime_resume(struct device * dev)919 static int rockchip_spi_runtime_resume(struct device *dev)
920 {
921 int ret;
922 struct spi_controller *ctlr = dev_get_drvdata(dev);
923 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
924
925 ret = clk_prepare_enable(rs->apb_pclk);
926 if (ret < 0)
927 return ret;
928
929 ret = clk_prepare_enable(rs->spiclk);
930 if (ret < 0)
931 clk_disable_unprepare(rs->apb_pclk);
932
933 return 0;
934 }
935 #endif /* CONFIG_PM */
936
937 static const struct dev_pm_ops rockchip_spi_pm = {
938 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
939 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
940 rockchip_spi_runtime_resume, NULL)
941 };
942
943 static const struct of_device_id rockchip_spi_dt_match[] = {
944 { .compatible = "rockchip,px30-spi", },
945 { .compatible = "rockchip,rk3036-spi", },
946 { .compatible = "rockchip,rk3066-spi", },
947 { .compatible = "rockchip,rk3188-spi", },
948 { .compatible = "rockchip,rk3228-spi", },
949 { .compatible = "rockchip,rk3288-spi", },
950 { .compatible = "rockchip,rk3308-spi", },
951 { .compatible = "rockchip,rk3328-spi", },
952 { .compatible = "rockchip,rk3368-spi", },
953 { .compatible = "rockchip,rk3399-spi", },
954 { .compatible = "rockchip,rv1108-spi", },
955 { .compatible = "rockchip,rv1126-spi", },
956 { },
957 };
958 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
959
960 static struct platform_driver rockchip_spi_driver = {
961 .driver = {
962 .name = DRIVER_NAME,
963 .pm = &rockchip_spi_pm,
964 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
965 },
966 .probe = rockchip_spi_probe,
967 .remove = rockchip_spi_remove,
968 };
969
970 module_platform_driver(rockchip_spi_driver);
971
972 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
973 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
974 MODULE_LICENSE("GPL v2");
975
