1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 #include <linux/pinctrl/pinctrl.h>
10 
11 #include "pinctrl-msm.h"
12 
13 static const char * const sm6115_tiles[] = {
14 	"south",
15 	"east",
16 	"west"
17 };
18 
19 enum {
20 	SOUTH,
21 	EAST,
22 	WEST
23 };
24 
25 #define FUNCTION(fname)					\
26 	[msm_mux_##fname] = {				\
27 		.name = #fname,				\
28 		.groups = fname##_groups,		\
29 		.ngroups = ARRAY_SIZE(fname##_groups),	\
30 	}
31 
32 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
33 	{						\
34 		.name = "gpio" #id,			\
35 		.pins = gpio##id##_pins,		\
36 		.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),	\
37 		.funcs = (int[]){			\
38 			msm_mux_gpio, /* gpio mode */	\
39 			msm_mux_##f1,			\
40 			msm_mux_##f2,			\
41 			msm_mux_##f3,			\
42 			msm_mux_##f4,			\
43 			msm_mux_##f5,			\
44 			msm_mux_##f6,			\
45 			msm_mux_##f7,			\
46 			msm_mux_##f8,			\
47 			msm_mux_##f9			\
48 		},					\
49 		.nfuncs = 10,				\
50 		.ctl_reg = 0x1000 * id,		\
51 		.io_reg = 0x4 + 0x1000 * id,		\
52 		.intr_cfg_reg = 0x8 + 0x1000 * id,	\
53 		.intr_status_reg = 0xc + 0x1000 * id,	\
54 		.intr_target_reg = 0x8 + 0x1000 * id,	\
55 		.tile = _tile,			\
56 		.mux_bit = 2,			\
57 		.pull_bit = 0,			\
58 		.drv_bit = 6,			\
59 		.oe_bit = 9,			\
60 		.in_bit = 0,			\
61 		.out_bit = 1,			\
62 		.intr_enable_bit = 0,		\
63 		.intr_status_bit = 0,		\
64 		.intr_target_bit = 5,		\
65 		.intr_target_kpss_val = 3,	\
66 		.intr_raw_status_bit = 4,	\
67 		.intr_polarity_bit = 1,		\
68 		.intr_detection_bit = 2,	\
69 		.intr_detection_width = 2,	\
70 	}
71 
72 #define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv)	\
73 	{						\
74 		.name = #pg_name,			\
75 		.pins = pg_name##_pins,			\
76 		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
77 		.ctl_reg = ctl,				\
78 		.io_reg = 0,				\
79 		.intr_cfg_reg = 0,			\
80 		.intr_status_reg = 0,			\
81 		.intr_target_reg = 0,			\
82 		.tile = _tile,				\
83 		.mux_bit = -1,				\
84 		.pull_bit = pull,			\
85 		.drv_bit = drv,				\
86 		.oe_bit = -1,				\
87 		.in_bit = -1,				\
88 		.out_bit = -1,				\
89 		.intr_enable_bit = -1,			\
90 		.intr_status_bit = -1,			\
91 		.intr_target_bit = -1,			\
92 		.intr_raw_status_bit = -1,		\
93 		.intr_polarity_bit = -1,		\
94 		.intr_detection_bit = -1,		\
95 		.intr_detection_width = -1,		\
96 	}
97 
98 #define UFS_RESET(pg_name, offset)			\
99 	{						\
100 		.name = #pg_name,			\
101 		.pins = pg_name##_pins,			\
102 		.npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),	\
103 		.ctl_reg = offset,			\
104 		.io_reg = offset + 0x4,			\
105 		.intr_cfg_reg = 0,			\
106 		.intr_status_reg = 0,			\
107 		.intr_target_reg = 0,			\
108 		.tile = WEST,				\
109 		.mux_bit = -1,				\
110 		.pull_bit = 3,				\
111 		.drv_bit = 0,				\
112 		.oe_bit = -1,				\
113 		.in_bit = -1,				\
114 		.out_bit = 0,				\
115 		.intr_enable_bit = -1,			\
116 		.intr_status_bit = -1,			\
117 		.intr_target_bit = -1,			\
118 		.intr_raw_status_bit = -1,		\
119 		.intr_polarity_bit = -1,		\
120 		.intr_detection_bit = -1,		\
121 		.intr_detection_width = -1,		\
122 	}
123 static const struct pinctrl_pin_desc sm6115_pins[] = {
124 	PINCTRL_PIN(0, "GPIO_0"),
125 	PINCTRL_PIN(1, "GPIO_1"),
126 	PINCTRL_PIN(2, "GPIO_2"),
127 	PINCTRL_PIN(3, "GPIO_3"),
128 	PINCTRL_PIN(4, "GPIO_4"),
129 	PINCTRL_PIN(5, "GPIO_5"),
130 	PINCTRL_PIN(6, "GPIO_6"),
131 	PINCTRL_PIN(7, "GPIO_7"),
132 	PINCTRL_PIN(8, "GPIO_8"),
133 	PINCTRL_PIN(9, "GPIO_9"),
134 	PINCTRL_PIN(10, "GPIO_10"),
135 	PINCTRL_PIN(11, "GPIO_11"),
136 	PINCTRL_PIN(12, "GPIO_12"),
137 	PINCTRL_PIN(13, "GPIO_13"),
138 	PINCTRL_PIN(14, "GPIO_14"),
139 	PINCTRL_PIN(15, "GPIO_15"),
140 	PINCTRL_PIN(16, "GPIO_16"),
141 	PINCTRL_PIN(17, "GPIO_17"),
142 	PINCTRL_PIN(18, "GPIO_18"),
143 	PINCTRL_PIN(19, "GPIO_19"),
144 	PINCTRL_PIN(20, "GPIO_20"),
145 	PINCTRL_PIN(21, "GPIO_21"),
146 	PINCTRL_PIN(22, "GPIO_22"),
147 	PINCTRL_PIN(23, "GPIO_23"),
148 	PINCTRL_PIN(24, "GPIO_24"),
149 	PINCTRL_PIN(25, "GPIO_25"),
150 	PINCTRL_PIN(26, "GPIO_26"),
151 	PINCTRL_PIN(27, "GPIO_27"),
152 	PINCTRL_PIN(28, "GPIO_28"),
153 	PINCTRL_PIN(29, "GPIO_29"),
154 	PINCTRL_PIN(30, "GPIO_30"),
155 	PINCTRL_PIN(31, "GPIO_31"),
156 	PINCTRL_PIN(32, "GPIO_32"),
157 	PINCTRL_PIN(33, "GPIO_33"),
158 	PINCTRL_PIN(34, "GPIO_34"),
159 	PINCTRL_PIN(35, "GPIO_35"),
160 	PINCTRL_PIN(36, "GPIO_36"),
161 	PINCTRL_PIN(37, "GPIO_37"),
162 	PINCTRL_PIN(38, "GPIO_38"),
163 	PINCTRL_PIN(39, "GPIO_39"),
164 	PINCTRL_PIN(40, "GPIO_40"),
165 	PINCTRL_PIN(41, "GPIO_41"),
166 	PINCTRL_PIN(42, "GPIO_42"),
167 	PINCTRL_PIN(43, "GPIO_43"),
168 	PINCTRL_PIN(44, "GPIO_44"),
169 	PINCTRL_PIN(45, "GPIO_45"),
170 	PINCTRL_PIN(46, "GPIO_46"),
171 	PINCTRL_PIN(47, "GPIO_47"),
172 	PINCTRL_PIN(48, "GPIO_48"),
173 	PINCTRL_PIN(49, "GPIO_49"),
174 	PINCTRL_PIN(50, "GPIO_50"),
175 	PINCTRL_PIN(51, "GPIO_51"),
176 	PINCTRL_PIN(52, "GPIO_52"),
177 	PINCTRL_PIN(53, "GPIO_53"),
178 	PINCTRL_PIN(54, "GPIO_54"),
179 	PINCTRL_PIN(55, "GPIO_55"),
180 	PINCTRL_PIN(56, "GPIO_56"),
181 	PINCTRL_PIN(57, "GPIO_57"),
182 	PINCTRL_PIN(58, "GPIO_58"),
183 	PINCTRL_PIN(59, "GPIO_59"),
184 	PINCTRL_PIN(60, "GPIO_60"),
185 	PINCTRL_PIN(61, "GPIO_61"),
186 	PINCTRL_PIN(62, "GPIO_62"),
187 	PINCTRL_PIN(63, "GPIO_63"),
188 	PINCTRL_PIN(64, "GPIO_64"),
189 	PINCTRL_PIN(65, "GPIO_65"),
190 	PINCTRL_PIN(66, "GPIO_66"),
191 	PINCTRL_PIN(67, "GPIO_67"),
192 	PINCTRL_PIN(68, "GPIO_68"),
193 	PINCTRL_PIN(69, "GPIO_69"),
194 	PINCTRL_PIN(70, "GPIO_70"),
195 	PINCTRL_PIN(71, "GPIO_71"),
196 	PINCTRL_PIN(72, "GPIO_72"),
197 	PINCTRL_PIN(73, "GPIO_73"),
198 	PINCTRL_PIN(74, "GPIO_74"),
199 	PINCTRL_PIN(75, "GPIO_75"),
200 	PINCTRL_PIN(76, "GPIO_76"),
201 	PINCTRL_PIN(77, "GPIO_77"),
202 	PINCTRL_PIN(78, "GPIO_78"),
203 	PINCTRL_PIN(79, "GPIO_79"),
204 	PINCTRL_PIN(80, "GPIO_80"),
205 	PINCTRL_PIN(81, "GPIO_81"),
206 	PINCTRL_PIN(82, "GPIO_82"),
207 	PINCTRL_PIN(83, "GPIO_83"),
208 	PINCTRL_PIN(84, "GPIO_84"),
209 	PINCTRL_PIN(85, "GPIO_85"),
210 	PINCTRL_PIN(86, "GPIO_86"),
211 	PINCTRL_PIN(87, "GPIO_87"),
212 	PINCTRL_PIN(88, "GPIO_88"),
213 	PINCTRL_PIN(89, "GPIO_89"),
214 	PINCTRL_PIN(90, "GPIO_90"),
215 	PINCTRL_PIN(91, "GPIO_91"),
216 	PINCTRL_PIN(92, "GPIO_92"),
217 	PINCTRL_PIN(93, "GPIO_93"),
218 	PINCTRL_PIN(94, "GPIO_94"),
219 	PINCTRL_PIN(95, "GPIO_95"),
220 	PINCTRL_PIN(96, "GPIO_96"),
221 	PINCTRL_PIN(97, "GPIO_97"),
222 	PINCTRL_PIN(98, "GPIO_98"),
223 	PINCTRL_PIN(99, "GPIO_99"),
224 	PINCTRL_PIN(100, "GPIO_100"),
225 	PINCTRL_PIN(101, "GPIO_101"),
226 	PINCTRL_PIN(102, "GPIO_102"),
227 	PINCTRL_PIN(103, "GPIO_103"),
228 	PINCTRL_PIN(104, "GPIO_104"),
229 	PINCTRL_PIN(105, "GPIO_105"),
230 	PINCTRL_PIN(106, "GPIO_106"),
231 	PINCTRL_PIN(107, "GPIO_107"),
232 	PINCTRL_PIN(108, "GPIO_108"),
233 	PINCTRL_PIN(109, "GPIO_109"),
234 	PINCTRL_PIN(110, "GPIO_110"),
235 	PINCTRL_PIN(111, "GPIO_111"),
236 	PINCTRL_PIN(112, "GPIO_112"),
237 	PINCTRL_PIN(113, "UFS_RESET"),
238 	PINCTRL_PIN(114, "SDC1_RCLK"),
239 	PINCTRL_PIN(115, "SDC1_CLK"),
240 	PINCTRL_PIN(116, "SDC1_CMD"),
241 	PINCTRL_PIN(117, "SDC1_DATA"),
242 	PINCTRL_PIN(118, "SDC2_CLK"),
243 	PINCTRL_PIN(119, "SDC2_CMD"),
244 	PINCTRL_PIN(120, "SDC2_DATA"),
245 };
246 
247 #define DECLARE_MSM_GPIO_PINS(pin) \
248 	static const unsigned int gpio##pin##_pins[] = { pin }
249 DECLARE_MSM_GPIO_PINS(0);
250 DECLARE_MSM_GPIO_PINS(1);
251 DECLARE_MSM_GPIO_PINS(2);
252 DECLARE_MSM_GPIO_PINS(3);
253 DECLARE_MSM_GPIO_PINS(4);
254 DECLARE_MSM_GPIO_PINS(5);
255 DECLARE_MSM_GPIO_PINS(6);
256 DECLARE_MSM_GPIO_PINS(7);
257 DECLARE_MSM_GPIO_PINS(8);
258 DECLARE_MSM_GPIO_PINS(9);
259 DECLARE_MSM_GPIO_PINS(10);
260 DECLARE_MSM_GPIO_PINS(11);
261 DECLARE_MSM_GPIO_PINS(12);
262 DECLARE_MSM_GPIO_PINS(13);
263 DECLARE_MSM_GPIO_PINS(14);
264 DECLARE_MSM_GPIO_PINS(15);
265 DECLARE_MSM_GPIO_PINS(16);
266 DECLARE_MSM_GPIO_PINS(17);
267 DECLARE_MSM_GPIO_PINS(18);
268 DECLARE_MSM_GPIO_PINS(19);
269 DECLARE_MSM_GPIO_PINS(20);
270 DECLARE_MSM_GPIO_PINS(21);
271 DECLARE_MSM_GPIO_PINS(22);
272 DECLARE_MSM_GPIO_PINS(23);
273 DECLARE_MSM_GPIO_PINS(24);
274 DECLARE_MSM_GPIO_PINS(25);
275 DECLARE_MSM_GPIO_PINS(26);
276 DECLARE_MSM_GPIO_PINS(27);
277 DECLARE_MSM_GPIO_PINS(28);
278 DECLARE_MSM_GPIO_PINS(29);
279 DECLARE_MSM_GPIO_PINS(30);
280 DECLARE_MSM_GPIO_PINS(31);
281 DECLARE_MSM_GPIO_PINS(32);
282 DECLARE_MSM_GPIO_PINS(33);
283 DECLARE_MSM_GPIO_PINS(34);
284 DECLARE_MSM_GPIO_PINS(35);
285 DECLARE_MSM_GPIO_PINS(36);
286 DECLARE_MSM_GPIO_PINS(37);
287 DECLARE_MSM_GPIO_PINS(38);
288 DECLARE_MSM_GPIO_PINS(39);
289 DECLARE_MSM_GPIO_PINS(40);
290 DECLARE_MSM_GPIO_PINS(41);
291 DECLARE_MSM_GPIO_PINS(42);
292 DECLARE_MSM_GPIO_PINS(43);
293 DECLARE_MSM_GPIO_PINS(44);
294 DECLARE_MSM_GPIO_PINS(45);
295 DECLARE_MSM_GPIO_PINS(46);
296 DECLARE_MSM_GPIO_PINS(47);
297 DECLARE_MSM_GPIO_PINS(48);
298 DECLARE_MSM_GPIO_PINS(49);
299 DECLARE_MSM_GPIO_PINS(50);
300 DECLARE_MSM_GPIO_PINS(51);
301 DECLARE_MSM_GPIO_PINS(52);
302 DECLARE_MSM_GPIO_PINS(53);
303 DECLARE_MSM_GPIO_PINS(54);
304 DECLARE_MSM_GPIO_PINS(55);
305 DECLARE_MSM_GPIO_PINS(56);
306 DECLARE_MSM_GPIO_PINS(57);
307 DECLARE_MSM_GPIO_PINS(58);
308 DECLARE_MSM_GPIO_PINS(59);
309 DECLARE_MSM_GPIO_PINS(60);
310 DECLARE_MSM_GPIO_PINS(61);
311 DECLARE_MSM_GPIO_PINS(62);
312 DECLARE_MSM_GPIO_PINS(63);
313 DECLARE_MSM_GPIO_PINS(64);
314 DECLARE_MSM_GPIO_PINS(65);
315 DECLARE_MSM_GPIO_PINS(66);
316 DECLARE_MSM_GPIO_PINS(67);
317 DECLARE_MSM_GPIO_PINS(68);
318 DECLARE_MSM_GPIO_PINS(69);
319 DECLARE_MSM_GPIO_PINS(70);
320 DECLARE_MSM_GPIO_PINS(71);
321 DECLARE_MSM_GPIO_PINS(72);
322 DECLARE_MSM_GPIO_PINS(73);
323 DECLARE_MSM_GPIO_PINS(74);
324 DECLARE_MSM_GPIO_PINS(75);
325 DECLARE_MSM_GPIO_PINS(76);
326 DECLARE_MSM_GPIO_PINS(77);
327 DECLARE_MSM_GPIO_PINS(78);
328 DECLARE_MSM_GPIO_PINS(79);
329 DECLARE_MSM_GPIO_PINS(80);
330 DECLARE_MSM_GPIO_PINS(81);
331 DECLARE_MSM_GPIO_PINS(82);
332 DECLARE_MSM_GPIO_PINS(83);
333 DECLARE_MSM_GPIO_PINS(84);
334 DECLARE_MSM_GPIO_PINS(85);
335 DECLARE_MSM_GPIO_PINS(86);
336 DECLARE_MSM_GPIO_PINS(87);
337 DECLARE_MSM_GPIO_PINS(88);
338 DECLARE_MSM_GPIO_PINS(89);
339 DECLARE_MSM_GPIO_PINS(90);
340 DECLARE_MSM_GPIO_PINS(91);
341 DECLARE_MSM_GPIO_PINS(92);
342 DECLARE_MSM_GPIO_PINS(93);
343 DECLARE_MSM_GPIO_PINS(94);
344 DECLARE_MSM_GPIO_PINS(95);
345 DECLARE_MSM_GPIO_PINS(96);
346 DECLARE_MSM_GPIO_PINS(97);
347 DECLARE_MSM_GPIO_PINS(98);
348 DECLARE_MSM_GPIO_PINS(99);
349 DECLARE_MSM_GPIO_PINS(100);
350 DECLARE_MSM_GPIO_PINS(101);
351 DECLARE_MSM_GPIO_PINS(102);
352 DECLARE_MSM_GPIO_PINS(103);
353 DECLARE_MSM_GPIO_PINS(104);
354 DECLARE_MSM_GPIO_PINS(105);
355 DECLARE_MSM_GPIO_PINS(106);
356 DECLARE_MSM_GPIO_PINS(107);
357 DECLARE_MSM_GPIO_PINS(108);
358 DECLARE_MSM_GPIO_PINS(109);
359 DECLARE_MSM_GPIO_PINS(110);
360 DECLARE_MSM_GPIO_PINS(111);
361 DECLARE_MSM_GPIO_PINS(112);
362 
363 static const unsigned int ufs_reset_pins[] = { 113 };
364 static const unsigned int sdc1_rclk_pins[] = { 114 };
365 static const unsigned int sdc1_clk_pins[] = { 115 };
366 static const unsigned int sdc1_cmd_pins[] = { 116 };
367 static const unsigned int sdc1_data_pins[] = { 117 };
368 static const unsigned int sdc2_clk_pins[] = { 118 };
369 static const unsigned int sdc2_cmd_pins[] = { 119 };
370 static const unsigned int sdc2_data_pins[] = { 120 };
371 
372 enum sm6115_functions {
373 	msm_mux_adsp_ext,
374 	msm_mux_agera_pll,
375 	msm_mux_atest,
376 	msm_mux_cam_mclk,
377 	msm_mux_cci_async,
378 	msm_mux_cci_i2c,
379 	msm_mux_cci_timer,
380 	msm_mux_cri_trng,
381 	msm_mux_dac_calib,
382 	msm_mux_dbg_out,
383 	msm_mux_ddr_bist,
384 	msm_mux_ddr_pxi0,
385 	msm_mux_ddr_pxi1,
386 	msm_mux_ddr_pxi2,
387 	msm_mux_ddr_pxi3,
388 	msm_mux_gcc_gp1,
389 	msm_mux_gcc_gp2,
390 	msm_mux_gcc_gp3,
391 	msm_mux_gpio,
392 	msm_mux_gp_pdm0,
393 	msm_mux_gp_pdm1,
394 	msm_mux_gp_pdm2,
395 	msm_mux_gsm0_tx,
396 	msm_mux_gsm1_tx,
397 	msm_mux_jitter_bist,
398 	msm_mux_mdp_vsync,
399 	msm_mux_mdp_vsync_out_0,
400 	msm_mux_mdp_vsync_out_1,
401 	msm_mux_mpm_pwr,
402 	msm_mux_mss_lte,
403 	msm_mux_m_voc,
404 	msm_mux_nav_gpio,
405 	msm_mux_pa_indicator,
406 	msm_mux_pbs,
407 	msm_mux_pbs_out,
408 	msm_mux_phase_flag,
409 	msm_mux_pll_bist,
410 	msm_mux_pll_bypassnl,
411 	msm_mux_pll_reset,
412 	msm_mux_prng_rosc,
413 	msm_mux_qdss_cti,
414 	msm_mux_qdss_gpio,
415 	msm_mux_qup0,
416 	msm_mux_qup1,
417 	msm_mux_qup2,
418 	msm_mux_qup3,
419 	msm_mux_qup4,
420 	msm_mux_qup5,
421 	msm_mux_sdc1_tb,
422 	msm_mux_sdc2_tb,
423 	msm_mux_sd_write,
424 	msm_mux_ssbi_wtr1,
425 	msm_mux_tgu,
426 	msm_mux_tsense_pwm,
427 	msm_mux_uim1_clk,
428 	msm_mux_uim1_data,
429 	msm_mux_uim1_present,
430 	msm_mux_uim1_reset,
431 	msm_mux_uim2_clk,
432 	msm_mux_uim2_data,
433 	msm_mux_uim2_present,
434 	msm_mux_uim2_reset,
435 	msm_mux_usb_phy,
436 	msm_mux_vfr_1,
437 	msm_mux_vsense_trigger,
438 	msm_mux_wlan1_adc0,
439 	msm_mux_wlan1_adc1,
440 	msm_mux__,
441 };
442 
443 static const char * const qup0_groups[] = {
444 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio82", "gpio86",
445 };
446 static const char * const gpio_groups[] = {
447 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
448 	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
449 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
450 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
451 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
452 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
453 	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
454 	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
455 	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
456 	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
457 	"gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
458 	"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
459 	"gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
460 	"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
461 	"gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
462 	"gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
463 	"gpio111", "gpio112",
464 };
465 static const char * const ddr_bist_groups[] = {
466 	"gpio0", "gpio1", "gpio2", "gpio3",
467 };
468 static const char * const phase_flag_groups[] = {
469 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
470 	"gpio14", "gpio15", "gpio16", "gpio17", "gpio22", "gpio23", "gpio24",
471 	"gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33",
472 	"gpio35", "gpio36", "gpio43", "gpio44", "gpio45", "gpio63", "gpio64",
473 	"gpio102", "gpio103", "gpio104", "gpio105",
474 };
475 static const char * const qdss_gpio_groups[] = {
476 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio8", "gpio9", "gpio10",
477 	"gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
478 	"gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
479 	"gpio47", "gpio48", "gpio69", "gpio70", "gpio87", "gpio90", "gpio91",
480 	"gpio94", "gpio95", "gpio104", "gpio105", "gpio106", "gpio107",
481 	"gpio109", "gpio110",
482 };
483 static const char * const atest_groups[] = {
484 	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
485 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30",
486 	"gpio31", "gpio32", "gpio33", "gpio86", "gpio87", "gpio88", "gpio89",
487 	"gpio100", "gpio101",
488 };
489 static const char * const mpm_pwr_groups[] = {
490 	"gpio1",
491 };
492 static const char * const m_voc_groups[] = {
493 	"gpio0",
494 };
495 static const char * const dac_calib_groups[] = {
496 	"gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio14", "gpio15",
497 	"gpio16", "gpio17", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
498 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio80", "gpio81",
499 	"gpio82", "gpio102", "gpio103", "gpio104", "gpio105"
500 };
501 static const char * const qup1_groups[] = {
502 	"gpio4", "gpio5", "gpio69", "gpio70",
503 };
504 static const char * const cri_trng_groups[] = {
505 	"gpio4", "gpio5", "gpio18",
506 };
507 static const char * const qup2_groups[] = {
508 	"gpio6", "gpio7", "gpio71", "gpio80",
509 };
510 static const char * const qup3_groups[] = {
511 	"gpio8", "gpio9", "gpio10", "gpio11",
512 };
513 static const char * const pbs_out_groups[] = {
514 	"gpio8", "gpio9", "gpio52",
515 };
516 static const char * const pll_bist_groups[] = {
517 	"gpio8", "gpio9",
518 };
519 static const char * const tsense_pwm_groups[] = {
520 	"gpio8",
521 };
522 static const char * const agera_pll_groups[] = {
523 	"gpio10", "gpio11",
524 };
525 static const char * const pbs_groups[] = {
526 	"gpio10", "gpio11", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
527 	"gpio23", "gpio24", "gpio25", "gpio26", "gpio47", "gpio48", "gpio87",
528 	"gpio90", "gpio91",
529 };
530 static const char * const qup4_groups[] = {
531 	"gpio12", "gpio13", "gpio96", "gpio97",
532 };
533 static const char * const tgu_groups[] = {
534 	"gpio12", "gpio13", "gpio14", "gpio15",
535 };
536 static const char * const qup5_groups[] = {
537 	"gpio14", "gpio15", "gpio16", "gpio17",
538 };
539 static const char * const sdc2_tb_groups[] = {
540 	"gpio18",
541 };
542 static const char * const sdc1_tb_groups[] = {
543 	"gpio19",
544 };
545 static const char * const cam_mclk_groups[] = {
546 	"gpio20", "gpio21", "gpio27", "gpio28",
547 };
548 static const char * const adsp_ext_groups[] = {
549 	"gpio21",
550 };
551 static const char * const cci_i2c_groups[] = {
552 	"gpio22", "gpio23", "gpio29", "gpio30",
553 };
554 static const char * const prng_rosc_groups[] = {
555 	"gpio22", "gpio23",
556 };
557 static const char * const cci_timer_groups[] = {
558 	"gpio24", "gpio25", "gpio28", "gpio32",
559 };
560 static const char * const gcc_gp1_groups[] = {
561 	"gpio24", "gpio86",
562 };
563 static const char * const cci_async_groups[] = {
564 	"gpio25",
565 };
566 static const char * const vsense_trigger_groups[] = {
567 	"gpio26",
568 };
569 static const char * const qdss_cti_groups[] = {
570 	"gpio27", "gpio28", "gpio72", "gpio73", "gpio96", "gpio97",
571 };
572 static const char * const gp_pdm0_groups[] = {
573 	"gpio31", "gpio95",
574 };
575 static const char * const gp_pdm1_groups[] = {
576 	"gpio32", "gpio96",
577 };
578 static const char * const gp_pdm2_groups[] = {
579 	"gpio33", "gpio97",
580 };
581 static const char * const nav_gpio_groups[] = {
582 	"gpio42", "gpio47", "gpio52", "gpio95", "gpio96", "gpio97", "gpio106",
583 	"gpio107", "gpio108",
584 };
585 static const char * const vfr_1_groups[] = {
586 	"gpio48",
587 };
588 static const char * const pa_indicator_groups[] = {
589 	"gpio49",
590 };
591 static const char * const gsm1_tx_groups[] = {
592 	"gpio53",
593 };
594 static const char * const ssbi_wtr1_groups[] = {
595 	"gpio59", "gpio60",
596 };
597 static const char * const pll_bypassnl_groups[] = {
598 	"gpio62",
599 };
600 static const char * const pll_reset_groups[] = {
601 	"gpio63",
602 };
603 static const char * const ddr_pxi0_groups[] = {
604 	"gpio63", "gpio64",
605 };
606 static const char * const gsm0_tx_groups[] = {
607 	"gpio64",
608 };
609 static const char * const gcc_gp2_groups[] = {
610 	"gpio69", "gpio107",
611 };
612 static const char * const ddr_pxi1_groups[] = {
613 	"gpio69", "gpio70",
614 };
615 static const char * const gcc_gp3_groups[] = {
616 	"gpio70", "gpio106",
617 };
618 static const char * const dbg_out_groups[] = {
619 	"gpio71",
620 };
621 static const char * const uim2_data_groups[] = {
622 	"gpio72",
623 };
624 static const char * const uim2_clk_groups[] = {
625 	"gpio73",
626 };
627 static const char * const uim2_reset_groups[] = {
628 	"gpio74",
629 };
630 static const char * const uim2_present_groups[] = {
631 	"gpio75",
632 };
633 static const char * const uim1_data_groups[] = {
634 	"gpio76",
635 };
636 static const char * const uim1_clk_groups[] = {
637 	"gpio77",
638 };
639 static const char * const uim1_reset_groups[] = {
640 	"gpio78",
641 };
642 static const char * const uim1_present_groups[] = {
643 	"gpio79",
644 };
645 static const char * const mdp_vsync_groups[] = {
646 	"gpio81", "gpio96", "gpio97",
647 };
648 static const char * const mdp_vsync_out_0_groups[] = {
649 	"gpio81",
650 };
651 static const char * const mdp_vsync_out_1_groups[] = {
652 	"gpio81",
653 };
654 static const char * const usb_phy_groups[] = {
655 	"gpio89",
656 };
657 static const char * const mss_lte_groups[] = {
658 	"gpio90", "gpio91",
659 };
660 static const char * const wlan1_adc0_groups[] = {
661 	"gpio94",
662 };
663 static const char * const wlan1_adc1_groups[] = {
664 	"gpio95",
665 };
666 static const char * const sd_write_groups[] = {
667 	"gpio96",
668 };
669 static const char * const jitter_bist_groups[] = {
670 	"gpio96", "gpio97",
671 };
672 static const char * const ddr_pxi2_groups[] = {
673 	"gpio102", "gpio103",
674 };
675 static const char * const ddr_pxi3_groups[] = {
676 	"gpio104", "gpio105",
677 };
678 
679 static const struct msm_function sm6115_functions[] = {
680 	FUNCTION(adsp_ext),
681 	FUNCTION(agera_pll),
682 	FUNCTION(atest),
683 	FUNCTION(cam_mclk),
684 	FUNCTION(cci_async),
685 	FUNCTION(cci_i2c),
686 	FUNCTION(cci_timer),
687 	FUNCTION(cri_trng),
688 	FUNCTION(dac_calib),
689 	FUNCTION(dbg_out),
690 	FUNCTION(ddr_bist),
691 	FUNCTION(ddr_pxi0),
692 	FUNCTION(ddr_pxi1),
693 	FUNCTION(ddr_pxi2),
694 	FUNCTION(ddr_pxi3),
695 	FUNCTION(gcc_gp1),
696 	FUNCTION(gcc_gp2),
697 	FUNCTION(gcc_gp3),
698 	FUNCTION(gpio),
699 	FUNCTION(gp_pdm0),
700 	FUNCTION(gp_pdm1),
701 	FUNCTION(gp_pdm2),
702 	FUNCTION(gsm0_tx),
703 	FUNCTION(gsm1_tx),
704 	FUNCTION(jitter_bist),
705 	FUNCTION(mdp_vsync),
706 	FUNCTION(mdp_vsync_out_0),
707 	FUNCTION(mdp_vsync_out_1),
708 	FUNCTION(mpm_pwr),
709 	FUNCTION(mss_lte),
710 	FUNCTION(m_voc),
711 	FUNCTION(nav_gpio),
712 	FUNCTION(pa_indicator),
713 	FUNCTION(pbs),
714 	FUNCTION(pbs_out),
715 	FUNCTION(phase_flag),
716 	FUNCTION(pll_bist),
717 	FUNCTION(pll_bypassnl),
718 	FUNCTION(pll_reset),
719 	FUNCTION(prng_rosc),
720 	FUNCTION(qdss_cti),
721 	FUNCTION(qdss_gpio),
722 	FUNCTION(qup0),
723 	FUNCTION(qup1),
724 	FUNCTION(qup2),
725 	FUNCTION(qup3),
726 	FUNCTION(qup4),
727 	FUNCTION(qup5),
728 	FUNCTION(sdc1_tb),
729 	FUNCTION(sdc2_tb),
730 	FUNCTION(sd_write),
731 	FUNCTION(ssbi_wtr1),
732 	FUNCTION(tgu),
733 	FUNCTION(tsense_pwm),
734 	FUNCTION(uim1_clk),
735 	FUNCTION(uim1_data),
736 	FUNCTION(uim1_present),
737 	FUNCTION(uim1_reset),
738 	FUNCTION(uim2_clk),
739 	FUNCTION(uim2_data),
740 	FUNCTION(uim2_present),
741 	FUNCTION(uim2_reset),
742 	FUNCTION(usb_phy),
743 	FUNCTION(vfr_1),
744 	FUNCTION(vsense_trigger),
745 	FUNCTION(wlan1_adc0),
746 	FUNCTION(wlan1_adc1),
747 };
748 
749 /* Every pin is maintained as a single group, and missing or non-existing pin
750  * would be maintained as dummy group to synchronize pin group index with
751  * pin descriptor registered with pinctrl core.
752  * Clients would not be able to request these dummy pin groups.
753  */
754 static const struct msm_pingroup sm6115_groups[] = {
755 	[0] = PINGROUP(0, WEST, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
756 	[1] = PINGROUP(1, WEST, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
757 	[2] = PINGROUP(2, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _),
758 	[3] = PINGROUP(3, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _),
759 	[4] = PINGROUP(4, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _),
760 	[5] = PINGROUP(5, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _),
761 	[6] = PINGROUP(6, WEST, qup2, _, phase_flag, dac_calib, atest, _, _, _, _),
762 	[7] = PINGROUP(7, WEST, qup2, _, _, _, _, _, _, _, _),
763 	[8] = PINGROUP(8, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _),
764 	[9] = PINGROUP(9, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _),
765 	[10] = PINGROUP(10, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _),
766 	[11] = PINGROUP(11, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _),
767 	[12] = PINGROUP(12, WEST, qup4, tgu, _, _, _, _, _, _, _),
768 	[13] = PINGROUP(13, WEST, qup4, tgu, _, _, _, _, _, _, _),
769 	[14] = PINGROUP(14, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _),
770 	[15] = PINGROUP(15, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _),
771 	[16] = PINGROUP(16, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _),
772 	[17] = PINGROUP(17, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _),
773 	[18] = PINGROUP(18, EAST, sdc2_tb, cri_trng, pbs, qdss_gpio, _, _, _, _, _),
774 	[19] = PINGROUP(19, EAST, sdc1_tb, pbs, qdss_gpio, _, _, _, _, _, _),
775 	[20] = PINGROUP(20, EAST, cam_mclk, pbs, qdss_gpio, _, _, _, _, _, _),
776 	[21] = PINGROUP(21, EAST, cam_mclk, adsp_ext, pbs, qdss_gpio, _, _, _, _, _),
777 	[22] = PINGROUP(22, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
778 	[23] = PINGROUP(23, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
779 	[24] = PINGROUP(24, EAST, cci_timer, gcc_gp1, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
780 	[25] = PINGROUP(25, EAST, cci_async, cci_timer, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
781 	[26] = PINGROUP(26, EAST, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _),
782 	[27] = PINGROUP(27, EAST, cam_mclk, qdss_cti, _, _, _, _, _, _, _),
783 	[28] = PINGROUP(28, EAST, cam_mclk, cci_timer, qdss_cti, _, _, _, _, _, _),
784 	[29] = PINGROUP(29, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _),
785 	[30] = PINGROUP(30, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _),
786 	[31] = PINGROUP(31, EAST, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _),
787 	[32] = PINGROUP(32, EAST, cci_timer, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _),
788 	[33] = PINGROUP(33, EAST, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _),
789 	[34] = PINGROUP(34, EAST, _, _, _, _, _, _, _, _, _),
790 	[35] = PINGROUP(35, EAST, _, phase_flag, _, _, _, _, _, _, _),
791 	[36] = PINGROUP(36, EAST, _, phase_flag, _, _, _, _, _, _, _),
792 	[37] = PINGROUP(37, EAST, _, _, _, _, _, _, _, _, _),
793 	[38] = PINGROUP(38, EAST, _, _, _, _, _, _, _, _, _),
794 	[39] = PINGROUP(39, EAST, _, _, _, _, _, _, _, _, _),
795 	[40] = PINGROUP(40, EAST, _, _, _, _, _, _, _, _, _),
796 	[41] = PINGROUP(41, EAST, _, _, _, _, _, _, _, _, _),
797 	[42] = PINGROUP(42, EAST, _, nav_gpio, _, _, _, _, _, _, _),
798 	[43] = PINGROUP(43, EAST, _, _, phase_flag, _, _, _, _, _, _),
799 	[44] = PINGROUP(44, EAST, _, _, phase_flag, _, _, _, _, _, _),
800 	[45] = PINGROUP(45, EAST, _, _, phase_flag, _, _, _, _, _, _),
801 	[46] = PINGROUP(46, EAST, _, _, _, _, _, _, _, _, _),
802 	[47] = PINGROUP(47, EAST, _, nav_gpio, pbs, qdss_gpio, _, _, _, _, _),
803 	[48] = PINGROUP(48, EAST, _, vfr_1, _, pbs, qdss_gpio, _, _, _, _),
804 	[49] = PINGROUP(49, EAST, _, pa_indicator, _, _, _, _, _, _, _),
805 	[50] = PINGROUP(50, EAST, _, _, _, _, _, _, _, _, _),
806 	[51] = PINGROUP(51, EAST, _, _, _, _, _, _, _, _, _),
807 	[52] = PINGROUP(52, EAST, _, nav_gpio, pbs_out, _, _, _, _, _, _),
808 	[53] = PINGROUP(53, EAST, _, gsm1_tx, _, _, _, _, _, _, _),
809 	[54] = PINGROUP(54, EAST, _, _, _, _, _, _, _, _, _),
810 	[55] = PINGROUP(55, EAST, _, _, _, _, _, _, _, _, _),
811 	[56] = PINGROUP(56, EAST, _, _, _, _, _, _, _, _, _),
812 	[57] = PINGROUP(57, EAST, _, _, _, _, _, _, _, _, _),
813 	[58] = PINGROUP(58, EAST, _, _, _, _, _, _, _, _, _),
814 	[59] = PINGROUP(59, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _),
815 	[60] = PINGROUP(60, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _),
816 	[61] = PINGROUP(61, EAST, _, _, _, _, _, _, _, _, _),
817 	[62] = PINGROUP(62, EAST, _, pll_bypassnl, _, _, _, _, _, _, _),
818 	[63] = PINGROUP(63, EAST, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _),
819 	[64] = PINGROUP(64, EAST, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _),
820 	[65] = PINGROUP(65, WEST, _, _, _, _, _, _, _, _, _),
821 	[66] = PINGROUP(66, WEST, _, _, _, _, _, _, _, _, _),
822 	[67] = PINGROUP(67, WEST, _, _, _, _, _, _, _, _, _),
823 	[68] = PINGROUP(68, WEST, _, _, _, _, _, _, _, _, _),
824 	[69] = PINGROUP(69, WEST, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _),
825 	[70] = PINGROUP(70, WEST, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _),
826 	[71] = PINGROUP(71, WEST, qup2, dbg_out, _, _, _, _, _, _, _),
827 	[72] = PINGROUP(72, SOUTH, uim2_data, qdss_cti, _, _, _, _, _, _, _),
828 	[73] = PINGROUP(73, SOUTH, uim2_clk, _, qdss_cti, _, _, _, _, _, _),
829 	[74] = PINGROUP(74, SOUTH, uim2_reset, _, _, _, _, _, _, _, _),
830 	[75] = PINGROUP(75, SOUTH, uim2_present, _, _, _, _, _, _, _, _),
831 	[76] = PINGROUP(76, SOUTH, uim1_data, _, _, _, _, _, _, _, _),
832 	[77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _),
833 	[78] = PINGROUP(78, SOUTH, uim1_reset, _, _, _, _, _, _, _, _),
834 	[79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _),
835 	[80] = PINGROUP(80, WEST, qup2, dac_calib, _, _, _, _, _, _, _),
836 	[81] = PINGROUP(81, WEST, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _),
837 	[82] = PINGROUP(82, WEST, qup0, dac_calib, _, _, _, _, _, _, _),
838 	[83] = PINGROUP(83, WEST, _, _, _, _, _, _, _, _, _),
839 	[84] = PINGROUP(84, WEST, _, _, _, _, _, _, _, _, _),
840 	[85] = PINGROUP(85, WEST, _, _, _, _, _, _, _, _, _),
841 	[86] = PINGROUP(86, WEST, qup0, gcc_gp1, atest, _, _, _, _, _, _),
842 	[87] = PINGROUP(87, EAST, pbs, qdss_gpio, _, _, _, _, _, _, _),
843 	[88] = PINGROUP(88, EAST, _, _, _, _, _, _, _, _, _),
844 	[89] = PINGROUP(89, WEST, usb_phy, atest, _, _, _, _, _, _, _),
845 	[90] = PINGROUP(90, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _),
846 	[91] = PINGROUP(91, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _),
847 	[92] = PINGROUP(92, WEST, _, _, _, _, _, _, _, _, _),
848 	[93] = PINGROUP(93, WEST, _, _, _, _, _, _, _, _, _),
849 	[94] = PINGROUP(94, WEST, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _),
850 	[95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _),
851 	[96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _),
852 	[97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _),
853 	[98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, _),
854 	[99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _),
855 	[100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, _),
856 	[101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, _),
857 	[102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
858 	[103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
859 	[104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),
860 	[105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),
861 	[106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
862 	[107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
863 	[108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, _),
864 	[109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _),
865 	[110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _),
866 	[111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _),
867 	[112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _),
868 	[113] = UFS_RESET(ufs_reset, 0x78000),
869 	[114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0),
870 	[115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6),
871 	[116] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x75000, 11, 3),
872 	[117] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x75000, 9, 0),
873 	[118] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x73000, 14, 6),
874 	[119] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x73000, 11, 3),
875 	[120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0),
876 };
877 
878 static const struct msm_pinctrl_soc_data sm6115_tlmm = {
879 	.pins = sm6115_pins,
880 	.npins = ARRAY_SIZE(sm6115_pins),
881 	.functions = sm6115_functions,
882 	.nfunctions = ARRAY_SIZE(sm6115_functions),
883 	.groups = sm6115_groups,
884 	.ngroups = ARRAY_SIZE(sm6115_groups),
885 	.ngpios = 114,
886 	.tiles = sm6115_tiles,
887 	.ntiles = ARRAY_SIZE(sm6115_tiles),
888 };
889 
sm6115_tlmm_probe(struct platform_device * pdev)890 static int sm6115_tlmm_probe(struct platform_device *pdev)
891 {
892 	return msm_pinctrl_probe(pdev, &sm6115_tlmm);
893 }
894 
895 static const struct of_device_id sm6115_tlmm_of_match[] = {
896 	{ .compatible = "qcom,sm6115-tlmm", },
897 	{ }
898 };
899 
900 static struct platform_driver sm6115_tlmm_driver = {
901 	.driver = {
902 		.name = "sm6115-tlmm",
903 		.of_match_table = sm6115_tlmm_of_match,
904 	},
905 	.probe = sm6115_tlmm_probe,
906 	.remove = msm_pinctrl_remove,
907 };
908 
sm6115_tlmm_init(void)909 static int __init sm6115_tlmm_init(void)
910 {
911 	return platform_driver_register(&sm6115_tlmm_driver);
912 }
913 arch_initcall(sm6115_tlmm_init);
914 
sm6115_tlmm_exit(void)915 static void __exit sm6115_tlmm_exit(void)
916 {
917 	platform_driver_unregister(&sm6115_tlmm_driver);
918 }
919 module_exit(sm6115_tlmm_exit);
920 
921 MODULE_DESCRIPTION("QTI sm6115 tlmm driver");
922 MODULE_LICENSE("GPL v2");
923 MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match);
924