1 // SPDX-License-Identifier: GPL-2.0
2
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2021 Linaro Ltd.
5 */
6
7 #include <linux/types.h>
8 #include <linux/atomic.h>
9 #include <linux/bitfield.h>
10 #include <linux/device.h>
11 #include <linux/bug.h>
12 #include <linux/io.h>
13 #include <linux/firmware.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/of_address.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/qcom_scm.h>
20 #include <linux/soc/qcom/mdt_loader.h>
21
22 #include "ipa.h"
23 #include "ipa_power.h"
24 #include "ipa_data.h"
25 #include "ipa_endpoint.h"
26 #include "ipa_resource.h"
27 #include "ipa_cmd.h"
28 #include "ipa_reg.h"
29 #include "ipa_mem.h"
30 #include "ipa_table.h"
31 #include "ipa_modem.h"
32 #include "ipa_uc.h"
33 #include "ipa_interrupt.h"
34 #include "gsi_trans.h"
35 #include "ipa_sysfs.h"
36
37 /**
38 * DOC: The IP Accelerator
39 *
40 * This driver supports the Qualcomm IP Accelerator (IPA), which is a
41 * networking component found in many Qualcomm SoCs. The IPA is connected
42 * to the application processor (AP), but is also connected (and partially
43 * controlled by) other "execution environments" (EEs), such as a modem.
44 *
45 * The IPA is the conduit between the AP and the modem that carries network
46 * traffic. This driver presents a network interface representing the
47 * connection of the modem to external (e.g. LTE) networks.
48 *
49 * The IPA provides protocol checksum calculation, offloading this work
50 * from the AP. The IPA offers additional functionality, including routing,
51 * filtering, and NAT support, but that more advanced functionality is not
52 * currently supported. Despite that, some resources--including routing
53 * tables and filter tables--are defined in this driver because they must
54 * be initialized even when the advanced hardware features are not used.
55 *
56 * There are two distinct layers that implement the IPA hardware, and this
57 * is reflected in the organization of the driver. The generic software
58 * interface (GSI) is an integral component of the IPA, providing a
59 * well-defined communication layer between the AP subsystem and the IPA
60 * core. The GSI implements a set of "channels" used for communication
61 * between the AP and the IPA.
62 *
63 * The IPA layer uses GSI channels to implement its "endpoints". And while
64 * a GSI channel carries data between the AP and the IPA, a pair of IPA
65 * endpoints is used to carry traffic between two EEs. Specifically, the main
66 * modem network interface is implemented by two pairs of endpoints: a TX
67 * endpoint on the AP coupled with an RX endpoint on the modem; and another
68 * RX endpoint on the AP receiving data from a TX endpoint on the modem.
69 */
70
71 /* The name of the GSI firmware file relative to /lib/firmware */
72 #define IPA_FW_PATH_DEFAULT "ipa_fws.mdt"
73 #define IPA_PAS_ID 15
74
75 /* Shift of 19.2 MHz timestamp to achieve lower resolution timestamps */
76 #define DPL_TIMESTAMP_SHIFT 14 /* ~1.172 kHz, ~853 usec per tick */
77 #define TAG_TIMESTAMP_SHIFT 14
78 #define NAT_TIMESTAMP_SHIFT 24 /* ~1.144 Hz, ~874 msec per tick */
79
80 /* Divider for 19.2 MHz crystal oscillator clock to get common timer clock */
81 #define IPA_XO_CLOCK_DIVIDER 192 /* 1 is subtracted where used */
82
83 /**
84 * ipa_setup() - Set up IPA hardware
85 * @ipa: IPA pointer
86 *
87 * Perform initialization that requires issuing immediate commands on
88 * the command TX endpoint. If the modem is doing GSI firmware load
89 * and initialization, this function will be called when an SMP2P
90 * interrupt has been signaled by the modem. Otherwise it will be
91 * called from ipa_probe() after GSI firmware has been successfully
92 * loaded, authenticated, and started by Trust Zone.
93 */
ipa_setup(struct ipa * ipa)94 int ipa_setup(struct ipa *ipa)
95 {
96 struct ipa_endpoint *exception_endpoint;
97 struct ipa_endpoint *command_endpoint;
98 struct device *dev = &ipa->pdev->dev;
99 int ret;
100
101 ret = gsi_setup(&ipa->gsi);
102 if (ret)
103 return ret;
104
105 ret = ipa_power_setup(ipa);
106 if (ret)
107 goto err_gsi_teardown;
108
109 ipa_endpoint_setup(ipa);
110
111 /* We need to use the AP command TX endpoint to perform other
112 * initialization, so we enable first.
113 */
114 command_endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX];
115 ret = ipa_endpoint_enable_one(command_endpoint);
116 if (ret)
117 goto err_endpoint_teardown;
118
119 ret = ipa_mem_setup(ipa); /* No matching teardown required */
120 if (ret)
121 goto err_command_disable;
122
123 ret = ipa_table_setup(ipa); /* No matching teardown required */
124 if (ret)
125 goto err_command_disable;
126
127 /* Enable the exception handling endpoint, and tell the hardware
128 * to use it by default.
129 */
130 exception_endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX];
131 ret = ipa_endpoint_enable_one(exception_endpoint);
132 if (ret)
133 goto err_command_disable;
134
135 ipa_endpoint_default_route_set(ipa, exception_endpoint->endpoint_id);
136
137 /* We're all set. Now prepare for communication with the modem */
138 ret = ipa_qmi_setup(ipa);
139 if (ret)
140 goto err_default_route_clear;
141
142 ipa->setup_complete = true;
143
144 dev_info(dev, "IPA driver setup completed successfully\n");
145
146 return 0;
147
148 err_default_route_clear:
149 ipa_endpoint_default_route_clear(ipa);
150 ipa_endpoint_disable_one(exception_endpoint);
151 err_command_disable:
152 ipa_endpoint_disable_one(command_endpoint);
153 err_endpoint_teardown:
154 ipa_endpoint_teardown(ipa);
155 ipa_power_teardown(ipa);
156 err_gsi_teardown:
157 gsi_teardown(&ipa->gsi);
158
159 return ret;
160 }
161
162 /**
163 * ipa_teardown() - Inverse of ipa_setup()
164 * @ipa: IPA pointer
165 */
ipa_teardown(struct ipa * ipa)166 static void ipa_teardown(struct ipa *ipa)
167 {
168 struct ipa_endpoint *exception_endpoint;
169 struct ipa_endpoint *command_endpoint;
170
171 /* We're going to tear everything down, as if setup never completed */
172 ipa->setup_complete = false;
173
174 ipa_qmi_teardown(ipa);
175 ipa_endpoint_default_route_clear(ipa);
176 exception_endpoint = ipa->name_map[IPA_ENDPOINT_AP_LAN_RX];
177 ipa_endpoint_disable_one(exception_endpoint);
178 command_endpoint = ipa->name_map[IPA_ENDPOINT_AP_COMMAND_TX];
179 ipa_endpoint_disable_one(command_endpoint);
180 ipa_endpoint_teardown(ipa);
181 ipa_power_teardown(ipa);
182 gsi_teardown(&ipa->gsi);
183 }
184
185 /* Configure bus access behavior for IPA components */
ipa_hardware_config_comp(struct ipa * ipa)186 static void ipa_hardware_config_comp(struct ipa *ipa)
187 {
188 u32 val;
189
190 /* Nothing to configure prior to IPA v4.0 */
191 if (ipa->version < IPA_VERSION_4_0)
192 return;
193
194 val = ioread32(ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET);
195
196 if (ipa->version == IPA_VERSION_4_0) {
197 val &= ~IPA_QMB_SELECT_CONS_EN_FMASK;
198 val &= ~IPA_QMB_SELECT_PROD_EN_FMASK;
199 val &= ~IPA_QMB_SELECT_GLOBAL_EN_FMASK;
200 } else if (ipa->version < IPA_VERSION_4_5) {
201 val |= GSI_MULTI_AXI_MASTERS_DIS_FMASK;
202 } else {
203 /* For IPA v4.5 IPA_FULL_FLUSH_WAIT_RSC_CLOSE_EN is 0 */
204 }
205
206 val |= GSI_MULTI_INORDER_RD_DIS_FMASK;
207 val |= GSI_MULTI_INORDER_WR_DIS_FMASK;
208
209 iowrite32(val, ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET);
210 }
211
212 /* Configure DDR and (possibly) PCIe max read/write QSB values */
213 static void
ipa_hardware_config_qsb(struct ipa * ipa,const struct ipa_data * data)214 ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data)
215 {
216 const struct ipa_qsb_data *data0;
217 const struct ipa_qsb_data *data1;
218 u32 val;
219
220 /* QMB 0 represents DDR; QMB 1 (if present) represents PCIe */
221 data0 = &data->qsb_data[IPA_QSB_MASTER_DDR];
222 if (data->qsb_count > 1)
223 data1 = &data->qsb_data[IPA_QSB_MASTER_PCIE];
224
225 /* Max outstanding write accesses for QSB masters */
226 val = u32_encode_bits(data0->max_writes, GEN_QMB_0_MAX_WRITES_FMASK);
227 if (data->qsb_count > 1)
228 val |= u32_encode_bits(data1->max_writes,
229 GEN_QMB_1_MAX_WRITES_FMASK);
230 iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_WRITES_OFFSET);
231
232 /* Max outstanding read accesses for QSB masters */
233 val = u32_encode_bits(data0->max_reads, GEN_QMB_0_MAX_READS_FMASK);
234 if (ipa->version >= IPA_VERSION_4_0)
235 val |= u32_encode_bits(data0->max_reads_beats,
236 GEN_QMB_0_MAX_READS_BEATS_FMASK);
237 if (data->qsb_count > 1) {
238 val |= u32_encode_bits(data1->max_reads,
239 GEN_QMB_1_MAX_READS_FMASK);
240 if (ipa->version >= IPA_VERSION_4_0)
241 val |= u32_encode_bits(data1->max_reads_beats,
242 GEN_QMB_1_MAX_READS_BEATS_FMASK);
243 }
244 iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_READS_OFFSET);
245 }
246
247 /* The internal inactivity timer clock is used for the aggregation timer */
248 #define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */
249
250 /* Compute the value to use in the COUNTER_CFG register AGGR_GRANULARITY
251 * field to represent the given number of microseconds. The value is one
252 * less than the number of timer ticks in the requested period. 0 is not
253 * a valid granularity value (so for example @usec must be at least 16 for
254 * a TIMER_FREQUENCY of 32000).
255 */
ipa_aggr_granularity_val(u32 usec)256 static __always_inline u32 ipa_aggr_granularity_val(u32 usec)
257 {
258 return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1;
259 }
260
261 /* IPA uses unified Qtime starting at IPA v4.5, implementing various
262 * timestamps and timers independent of the IPA core clock rate. The
263 * Qtimer is based on a 56-bit timestamp incremented at each tick of
264 * a 19.2 MHz SoC crystal oscillator (XO clock).
265 *
266 * For IPA timestamps (tag, NAT, data path logging) a lower resolution
267 * timestamp is achieved by shifting the Qtimer timestamp value right
268 * some number of bits to produce the low-order bits of the coarser
269 * granularity timestamp.
270 *
271 * For timers, a common timer clock is derived from the XO clock using
272 * a divider (we use 192, to produce a 100kHz timer clock). From
273 * this common clock, three "pulse generators" are used to produce
274 * timer ticks at a configurable frequency. IPA timers (such as
275 * those used for aggregation or head-of-line block handling) now
276 * define their period based on one of these pulse generators.
277 */
ipa_qtime_config(struct ipa * ipa)278 static void ipa_qtime_config(struct ipa *ipa)
279 {
280 u32 val;
281
282 /* Timer clock divider must be disabled when we change the rate */
283 iowrite32(0, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET);
284
285 /* Set DPL time stamp resolution to use Qtime (instead of 1 msec) */
286 val = u32_encode_bits(DPL_TIMESTAMP_SHIFT, DPL_TIMESTAMP_LSB_FMASK);
287 val |= u32_encode_bits(1, DPL_TIMESTAMP_SEL_FMASK);
288 /* Configure tag and NAT Qtime timestamp resolution as well */
289 val |= u32_encode_bits(TAG_TIMESTAMP_SHIFT, TAG_TIMESTAMP_LSB_FMASK);
290 val |= u32_encode_bits(NAT_TIMESTAMP_SHIFT, NAT_TIMESTAMP_LSB_FMASK);
291 iowrite32(val, ipa->reg_virt + IPA_REG_QTIME_TIMESTAMP_CFG_OFFSET);
292
293 /* Set granularity of pulse generators used for other timers */
294 val = u32_encode_bits(IPA_GRAN_100_US, GRAN_0_FMASK);
295 val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_1_FMASK);
296 val |= u32_encode_bits(IPA_GRAN_1_MS, GRAN_2_FMASK);
297 iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_PULSE_GRAN_CFG_OFFSET);
298
299 /* Actual divider is 1 more than value supplied here */
300 val = u32_encode_bits(IPA_XO_CLOCK_DIVIDER - 1, DIV_VALUE_FMASK);
301 iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET);
302
303 /* Divider value is set; re-enable the common timer clock divider */
304 val |= u32_encode_bits(1, DIV_ENABLE_FMASK);
305 iowrite32(val, ipa->reg_virt + IPA_REG_TIMERS_XO_CLK_DIV_CFG_OFFSET);
306 }
307
ipa_idle_indication_cfg(struct ipa * ipa,u32 enter_idle_debounce_thresh,bool const_non_idle_enable)308 static void ipa_idle_indication_cfg(struct ipa *ipa,
309 u32 enter_idle_debounce_thresh,
310 bool const_non_idle_enable)
311 {
312 u32 offset;
313 u32 val;
314
315 val = u32_encode_bits(enter_idle_debounce_thresh,
316 ENTER_IDLE_DEBOUNCE_THRESH_FMASK);
317 if (const_non_idle_enable)
318 val |= CONST_NON_IDLE_ENABLE_FMASK;
319
320 offset = ipa_reg_idle_indication_cfg_offset(ipa->version);
321 iowrite32(val, ipa->reg_virt + offset);
322 }
323
324 /**
325 * ipa_hardware_dcd_config() - Enable dynamic clock division on IPA
326 * @ipa: IPA pointer
327 *
328 * Configures when the IPA signals it is idle to the global clock
329 * controller, which can respond by scaling down the clock to save
330 * power.
331 */
ipa_hardware_dcd_config(struct ipa * ipa)332 static void ipa_hardware_dcd_config(struct ipa *ipa)
333 {
334 /* Recommended values for IPA 3.5 and later according to IPA HPG */
335 ipa_idle_indication_cfg(ipa, 256, false);
336 }
337
ipa_hardware_dcd_deconfig(struct ipa * ipa)338 static void ipa_hardware_dcd_deconfig(struct ipa *ipa)
339 {
340 /* Power-on reset values */
341 ipa_idle_indication_cfg(ipa, 0, true);
342 }
343
344 /**
345 * ipa_hardware_config() - Primitive hardware initialization
346 * @ipa: IPA pointer
347 * @data: IPA configuration data
348 */
ipa_hardware_config(struct ipa * ipa,const struct ipa_data * data)349 static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data)
350 {
351 enum ipa_version version = ipa->version;
352 u32 granularity;
353 u32 val;
354
355 /* IPA v4.5+ has no backward compatibility register */
356 if (version < IPA_VERSION_4_5) {
357 val = data->backward_compat;
358 iowrite32(val, ipa->reg_virt + IPA_REG_BCR_OFFSET);
359 }
360
361 /* Implement some hardware workarounds */
362 if (version >= IPA_VERSION_4_0 && version < IPA_VERSION_4_5) {
363 /* Disable PA mask to allow HOLB drop */
364 val = ioread32(ipa->reg_virt + IPA_REG_TX_CFG_OFFSET);
365 val &= ~PA_MASK_EN_FMASK;
366 iowrite32(val, ipa->reg_virt + IPA_REG_TX_CFG_OFFSET);
367
368 /* Enable open global clocks in the CLKON configuration */
369 val = GLOBAL_FMASK | GLOBAL_2X_CLK_FMASK;
370 } else if (version == IPA_VERSION_3_1) {
371 val = MISC_FMASK; /* Disable MISC clock gating */
372 } else {
373 val = 0; /* No CLKON configuration needed */
374 }
375 if (val)
376 iowrite32(val, ipa->reg_virt + IPA_REG_CLKON_CFG_OFFSET);
377
378 ipa_hardware_config_comp(ipa);
379
380 /* Configure system bus limits */
381 ipa_hardware_config_qsb(ipa, data);
382
383 if (version < IPA_VERSION_4_5) {
384 /* Configure aggregation timer granularity */
385 granularity = ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY);
386 val = u32_encode_bits(granularity, AGGR_GRANULARITY_FMASK);
387 iowrite32(val, ipa->reg_virt + IPA_REG_COUNTER_CFG_OFFSET);
388 } else {
389 ipa_qtime_config(ipa);
390 }
391
392 /* IPA v4.2 does not support hashed tables, so disable them */
393 if (version == IPA_VERSION_4_2) {
394 u32 offset = ipa_reg_filt_rout_hash_en_offset(version);
395
396 iowrite32(0, ipa->reg_virt + offset);
397 }
398
399 /* Enable dynamic clock division */
400 ipa_hardware_dcd_config(ipa);
401 }
402
403 /**
404 * ipa_hardware_deconfig() - Inverse of ipa_hardware_config()
405 * @ipa: IPA pointer
406 *
407 * This restores the power-on reset values (even if they aren't different)
408 */
ipa_hardware_deconfig(struct ipa * ipa)409 static void ipa_hardware_deconfig(struct ipa *ipa)
410 {
411 /* Mostly we just leave things as we set them. */
412 ipa_hardware_dcd_deconfig(ipa);
413 }
414
415 /**
416 * ipa_config() - Configure IPA hardware
417 * @ipa: IPA pointer
418 * @data: IPA configuration data
419 *
420 * Perform initialization requiring IPA power to be enabled.
421 */
ipa_config(struct ipa * ipa,const struct ipa_data * data)422 static int ipa_config(struct ipa *ipa, const struct ipa_data *data)
423 {
424 int ret;
425
426 ipa_hardware_config(ipa, data);
427
428 ret = ipa_mem_config(ipa);
429 if (ret)
430 goto err_hardware_deconfig;
431
432 ipa->interrupt = ipa_interrupt_config(ipa);
433 if (IS_ERR(ipa->interrupt)) {
434 ret = PTR_ERR(ipa->interrupt);
435 ipa->interrupt = NULL;
436 goto err_mem_deconfig;
437 }
438
439 ipa_uc_config(ipa);
440
441 ret = ipa_endpoint_config(ipa);
442 if (ret)
443 goto err_uc_deconfig;
444
445 ipa_table_config(ipa); /* No deconfig required */
446
447 /* Assign resource limitation to each group; no deconfig required */
448 ret = ipa_resource_config(ipa, data->resource_data);
449 if (ret)
450 goto err_endpoint_deconfig;
451
452 ret = ipa_modem_config(ipa);
453 if (ret)
454 goto err_endpoint_deconfig;
455
456 return 0;
457
458 err_endpoint_deconfig:
459 ipa_endpoint_deconfig(ipa);
460 err_uc_deconfig:
461 ipa_uc_deconfig(ipa);
462 ipa_interrupt_deconfig(ipa->interrupt);
463 ipa->interrupt = NULL;
464 err_mem_deconfig:
465 ipa_mem_deconfig(ipa);
466 err_hardware_deconfig:
467 ipa_hardware_deconfig(ipa);
468
469 return ret;
470 }
471
472 /**
473 * ipa_deconfig() - Inverse of ipa_config()
474 * @ipa: IPA pointer
475 */
ipa_deconfig(struct ipa * ipa)476 static void ipa_deconfig(struct ipa *ipa)
477 {
478 ipa_modem_deconfig(ipa);
479 ipa_endpoint_deconfig(ipa);
480 ipa_uc_deconfig(ipa);
481 ipa_interrupt_deconfig(ipa->interrupt);
482 ipa->interrupt = NULL;
483 ipa_mem_deconfig(ipa);
484 ipa_hardware_deconfig(ipa);
485 }
486
ipa_firmware_load(struct device * dev)487 static int ipa_firmware_load(struct device *dev)
488 {
489 const struct firmware *fw;
490 struct device_node *node;
491 struct resource res;
492 phys_addr_t phys;
493 const char *path;
494 ssize_t size;
495 void *virt;
496 int ret;
497
498 node = of_parse_phandle(dev->of_node, "memory-region", 0);
499 if (!node) {
500 dev_err(dev, "DT error getting \"memory-region\" property\n");
501 return -EINVAL;
502 }
503
504 ret = of_address_to_resource(node, 0, &res);
505 of_node_put(node);
506 if (ret) {
507 dev_err(dev, "error %d getting \"memory-region\" resource\n",
508 ret);
509 return ret;
510 }
511
512 /* Use name from DTB if specified; use default for *any* error */
513 ret = of_property_read_string(dev->of_node, "firmware-name", &path);
514 if (ret) {
515 dev_dbg(dev, "error %d getting \"firmware-name\" resource\n",
516 ret);
517 path = IPA_FW_PATH_DEFAULT;
518 }
519
520 ret = request_firmware(&fw, path, dev);
521 if (ret) {
522 dev_err(dev, "error %d requesting \"%s\"\n", ret, path);
523 return ret;
524 }
525
526 phys = res.start;
527 size = (size_t)resource_size(&res);
528 virt = memremap(phys, size, MEMREMAP_WC);
529 if (!virt) {
530 dev_err(dev, "unable to remap firmware memory\n");
531 ret = -ENOMEM;
532 goto out_release_firmware;
533 }
534
535 ret = qcom_mdt_load(dev, fw, path, IPA_PAS_ID, virt, phys, size, NULL);
536 if (ret)
537 dev_err(dev, "error %d loading \"%s\"\n", ret, path);
538 else if ((ret = qcom_scm_pas_auth_and_reset(IPA_PAS_ID)))
539 dev_err(dev, "error %d authenticating \"%s\"\n", ret, path);
540
541 memunmap(virt);
542 out_release_firmware:
543 release_firmware(fw);
544
545 return ret;
546 }
547
548 static const struct of_device_id ipa_match[] = {
549 {
550 .compatible = "qcom,msm8998-ipa",
551 .data = &ipa_data_v3_1,
552 },
553 {
554 .compatible = "qcom,sdm845-ipa",
555 .data = &ipa_data_v3_5_1,
556 },
557 {
558 .compatible = "qcom,sc7180-ipa",
559 .data = &ipa_data_v4_2,
560 },
561 {
562 .compatible = "qcom,sdx55-ipa",
563 .data = &ipa_data_v4_5,
564 },
565 {
566 .compatible = "qcom,sm8350-ipa",
567 .data = &ipa_data_v4_9,
568 },
569 {
570 .compatible = "qcom,sc7280-ipa",
571 .data = &ipa_data_v4_11,
572 },
573 { },
574 };
575 MODULE_DEVICE_TABLE(of, ipa_match);
576
577 /* Check things that can be validated at build time. This just
578 * groups these things BUILD_BUG_ON() calls don't clutter the rest
579 * of the code.
580 * */
ipa_validate_build(void)581 static void ipa_validate_build(void)
582 {
583 /* At one time we assumed a 64-bit build, allowing some do_div()
584 * calls to be replaced by simple division or modulo operations.
585 * We currently only perform divide and modulo operations on u32,
586 * u16, or size_t objects, and of those only size_t has any chance
587 * of being a 64-bit value. (It should be guaranteed 32 bits wide
588 * on a 32-bit build, but there is no harm in verifying that.)
589 */
590 BUILD_BUG_ON(!IS_ENABLED(CONFIG_64BIT) && sizeof(size_t) != 4);
591
592 /* Code assumes the EE ID for the AP is 0 (zeroed structure field) */
593 BUILD_BUG_ON(GSI_EE_AP != 0);
594
595 /* There's no point if we have no channels or event rings */
596 BUILD_BUG_ON(!GSI_CHANNEL_COUNT_MAX);
597 BUILD_BUG_ON(!GSI_EVT_RING_COUNT_MAX);
598
599 /* GSI hardware design limits */
600 BUILD_BUG_ON(GSI_CHANNEL_COUNT_MAX > 32);
601 BUILD_BUG_ON(GSI_EVT_RING_COUNT_MAX > 31);
602
603 /* The number of TREs in a transaction is limited by the channel's
604 * TLV FIFO size. A transaction structure uses 8-bit fields
605 * to represents the number of TREs it has allocated and used.
606 */
607 BUILD_BUG_ON(GSI_TLV_MAX > U8_MAX);
608
609 /* This is used as a divisor */
610 BUILD_BUG_ON(!IPA_AGGR_GRANULARITY);
611
612 /* Aggregation granularity value can't be 0, and must fit */
613 BUILD_BUG_ON(!ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY));
614 BUILD_BUG_ON(ipa_aggr_granularity_val(IPA_AGGR_GRANULARITY) >
615 field_max(AGGR_GRANULARITY_FMASK));
616 }
617
ipa_version_valid(enum ipa_version version)618 static bool ipa_version_valid(enum ipa_version version)
619 {
620 switch (version) {
621 case IPA_VERSION_3_0:
622 case IPA_VERSION_3_1:
623 case IPA_VERSION_3_5:
624 case IPA_VERSION_3_5_1:
625 case IPA_VERSION_4_0:
626 case IPA_VERSION_4_1:
627 case IPA_VERSION_4_2:
628 case IPA_VERSION_4_5:
629 case IPA_VERSION_4_7:
630 case IPA_VERSION_4_9:
631 case IPA_VERSION_4_11:
632 return true;
633
634 default:
635 return false;
636 }
637 }
638
639 /**
640 * ipa_probe() - IPA platform driver probe function
641 * @pdev: Platform device pointer
642 *
643 * Return: 0 if successful, or a negative error code (possibly
644 * EPROBE_DEFER)
645 *
646 * This is the main entry point for the IPA driver. Initialization proceeds
647 * in several stages:
648 * - The "init" stage involves activities that can be initialized without
649 * access to the IPA hardware.
650 * - The "config" stage requires IPA power to be active so IPA registers
651 * can be accessed, but does not require the use of IPA immediate commands.
652 * - The "setup" stage uses IPA immediate commands, and so requires the GSI
653 * layer to be initialized.
654 *
655 * A Boolean Device Tree "modem-init" property determines whether GSI
656 * initialization will be performed by the AP (Trust Zone) or the modem.
657 * If the AP does GSI initialization, the setup phase is entered after
658 * this has completed successfully. Otherwise the modem initializes
659 * the GSI layer and signals it has finished by sending an SMP2P interrupt
660 * to the AP; this triggers the start if IPA setup.
661 */
ipa_probe(struct platform_device * pdev)662 static int ipa_probe(struct platform_device *pdev)
663 {
664 struct device *dev = &pdev->dev;
665 const struct ipa_data *data;
666 struct ipa_power *power;
667 bool modem_init;
668 struct ipa *ipa;
669 int ret;
670
671 ipa_validate_build();
672
673 /* Get configuration data early; needed for power initialization */
674 data = of_device_get_match_data(dev);
675 if (!data) {
676 dev_err(dev, "matched hardware not supported\n");
677 return -ENODEV;
678 }
679
680 if (!ipa_version_valid(data->version)) {
681 dev_err(dev, "invalid IPA version\n");
682 return -EINVAL;
683 }
684
685 /* If we need Trust Zone, make sure it's available */
686 modem_init = of_property_read_bool(dev->of_node, "modem-init");
687 if (!modem_init)
688 if (!qcom_scm_is_available())
689 return -EPROBE_DEFER;
690
691 /* The clock and interconnects might not be ready when we're
692 * probed, so might return -EPROBE_DEFER.
693 */
694 power = ipa_power_init(dev, data->power_data);
695 if (IS_ERR(power))
696 return PTR_ERR(power);
697
698 /* No more EPROBE_DEFER. Allocate and initialize the IPA structure */
699 ipa = kzalloc(sizeof(*ipa), GFP_KERNEL);
700 if (!ipa) {
701 ret = -ENOMEM;
702 goto err_power_exit;
703 }
704
705 ipa->pdev = pdev;
706 dev_set_drvdata(dev, ipa);
707 ipa->power = power;
708 ipa->version = data->version;
709 init_completion(&ipa->completion);
710
711 ret = ipa_reg_init(ipa);
712 if (ret)
713 goto err_kfree_ipa;
714
715 ret = ipa_mem_init(ipa, data->mem_data);
716 if (ret)
717 goto err_reg_exit;
718
719 ret = gsi_init(&ipa->gsi, pdev, ipa->version, data->endpoint_count,
720 data->endpoint_data);
721 if (ret)
722 goto err_mem_exit;
723
724 /* Result is a non-zero mask of endpoints that support filtering */
725 ipa->filter_map = ipa_endpoint_init(ipa, data->endpoint_count,
726 data->endpoint_data);
727 if (!ipa->filter_map) {
728 ret = -EINVAL;
729 goto err_gsi_exit;
730 }
731
732 ret = ipa_table_init(ipa);
733 if (ret)
734 goto err_endpoint_exit;
735
736 ret = ipa_modem_init(ipa, modem_init);
737 if (ret)
738 goto err_table_exit;
739
740 /* Power needs to be active for config and setup */
741 ret = pm_runtime_get_sync(dev);
742 if (WARN_ON(ret < 0))
743 goto err_power_put;
744
745 ret = ipa_config(ipa, data);
746 if (ret)
747 goto err_power_put;
748
749 dev_info(dev, "IPA driver initialized");
750
751 /* If the modem is doing early initialization, it will trigger a
752 * call to ipa_setup() when it has finished. In that case we're
753 * done here.
754 */
755 if (modem_init)
756 goto done;
757
758 /* Otherwise we need to load the firmware and have Trust Zone validate
759 * and install it. If that succeeds we can proceed with setup.
760 */
761 ret = ipa_firmware_load(dev);
762 if (ret)
763 goto err_deconfig;
764
765 ret = ipa_setup(ipa);
766 if (ret)
767 goto err_deconfig;
768 done:
769 pm_runtime_mark_last_busy(dev);
770 (void)pm_runtime_put_autosuspend(dev);
771
772 return 0;
773
774 err_deconfig:
775 ipa_deconfig(ipa);
776 err_power_put:
777 pm_runtime_put_noidle(dev);
778 ipa_modem_exit(ipa);
779 err_table_exit:
780 ipa_table_exit(ipa);
781 err_endpoint_exit:
782 ipa_endpoint_exit(ipa);
783 err_gsi_exit:
784 gsi_exit(&ipa->gsi);
785 err_mem_exit:
786 ipa_mem_exit(ipa);
787 err_reg_exit:
788 ipa_reg_exit(ipa);
789 err_kfree_ipa:
790 kfree(ipa);
791 err_power_exit:
792 ipa_power_exit(power);
793
794 return ret;
795 }
796
ipa_remove(struct platform_device * pdev)797 static int ipa_remove(struct platform_device *pdev)
798 {
799 struct ipa *ipa = dev_get_drvdata(&pdev->dev);
800 struct ipa_power *power = ipa->power;
801 struct device *dev = &pdev->dev;
802 int ret;
803
804 ret = pm_runtime_get_sync(dev);
805 if (WARN_ON(ret < 0))
806 goto out_power_put;
807
808 if (ipa->setup_complete) {
809 ret = ipa_modem_stop(ipa);
810 /* If starting or stopping is in progress, try once more */
811 if (ret == -EBUSY) {
812 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
813 ret = ipa_modem_stop(ipa);
814 }
815 if (ret)
816 return ret;
817
818 ipa_teardown(ipa);
819 }
820
821 ipa_deconfig(ipa);
822 out_power_put:
823 pm_runtime_put_noidle(dev);
824 ipa_modem_exit(ipa);
825 ipa_table_exit(ipa);
826 ipa_endpoint_exit(ipa);
827 gsi_exit(&ipa->gsi);
828 ipa_mem_exit(ipa);
829 ipa_reg_exit(ipa);
830 kfree(ipa);
831 ipa_power_exit(power);
832
833 return 0;
834 }
835
ipa_shutdown(struct platform_device * pdev)836 static void ipa_shutdown(struct platform_device *pdev)
837 {
838 int ret;
839
840 ret = ipa_remove(pdev);
841 if (ret)
842 dev_err(&pdev->dev, "shutdown: remove returned %d\n", ret);
843 }
844
845 static const struct attribute_group *ipa_attribute_groups[] = {
846 &ipa_attribute_group,
847 &ipa_feature_attribute_group,
848 &ipa_modem_attribute_group,
849 NULL,
850 };
851
852 static struct platform_driver ipa_driver = {
853 .probe = ipa_probe,
854 .remove = ipa_remove,
855 .shutdown = ipa_shutdown,
856 .driver = {
857 .name = "ipa",
858 .pm = &ipa_pm_ops,
859 .of_match_table = ipa_match,
860 .dev_groups = ipa_attribute_groups,
861 },
862 };
863
864 module_platform_driver(ipa_driver);
865
866 MODULE_LICENSE("GPL v2");
867 MODULE_DESCRIPTION("Qualcomm IP Accelerator device driver");
868
