1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
3
4 #ifndef _IGC_H_
5 #define _IGC_H_
6
7 #include <linux/kobject.h>
8 #include <linux/pci.h>
9 #include <linux/netdevice.h>
10 #include <linux/vmalloc.h>
11 #include <linux/ethtool.h>
12 #include <linux/sctp.h>
13 #include <linux/ptp_clock_kernel.h>
14 #include <linux/timecounter.h>
15 #include <linux/net_tstamp.h>
16
17 #include "igc_hw.h"
18
19 void igc_ethtool_set_ops(struct net_device *);
20
21 /* Transmit and receive queues */
22 #define IGC_MAX_RX_QUEUES 4
23 #define IGC_MAX_TX_QUEUES 4
24
25 #define MAX_Q_VECTORS 8
26 #define MAX_STD_JUMBO_FRAME_SIZE 9216
27
28 #define MAX_ETYPE_FILTER 8
29 #define IGC_RETA_SIZE 128
30
31 /* SDP support */
32 #define IGC_N_EXTTS 2
33 #define IGC_N_PEROUT 2
34 #define IGC_N_SDP 4
35
36 #define MAX_FLEX_FILTER 32
37
38 enum igc_mac_filter_type {
39 IGC_MAC_FILTER_TYPE_DST = 0,
40 IGC_MAC_FILTER_TYPE_SRC
41 };
42
43 struct igc_tx_queue_stats {
44 u64 packets;
45 u64 bytes;
46 u64 restart_queue;
47 u64 restart_queue2;
48 };
49
50 struct igc_rx_queue_stats {
51 u64 packets;
52 u64 bytes;
53 u64 drops;
54 u64 csum_err;
55 u64 alloc_failed;
56 };
57
58 struct igc_rx_packet_stats {
59 u64 ipv4_packets; /* IPv4 headers processed */
60 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
61 u64 ipv6_packets; /* IPv6 headers processed */
62 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
63 u64 tcp_packets; /* TCP headers processed */
64 u64 udp_packets; /* UDP headers processed */
65 u64 sctp_packets; /* SCTP headers processed */
66 u64 nfs_packets; /* NFS headers processe */
67 u64 other_packets;
68 };
69
70 struct igc_ring_container {
71 struct igc_ring *ring; /* pointer to linked list of rings */
72 unsigned int total_bytes; /* total bytes processed this int */
73 unsigned int total_packets; /* total packets processed this int */
74 u16 work_limit; /* total work allowed per interrupt */
75 u8 count; /* total number of rings in vector */
76 u8 itr; /* current ITR setting for ring */
77 };
78
79 struct igc_ring {
80 struct igc_q_vector *q_vector; /* backlink to q_vector */
81 struct net_device *netdev; /* back pointer to net_device */
82 struct device *dev; /* device for dma mapping */
83 union { /* array of buffer info structs */
84 struct igc_tx_buffer *tx_buffer_info;
85 struct igc_rx_buffer *rx_buffer_info;
86 };
87 void *desc; /* descriptor ring memory */
88 unsigned long flags; /* ring specific flags */
89 void __iomem *tail; /* pointer to ring tail register */
90 dma_addr_t dma; /* phys address of the ring */
91 unsigned int size; /* length of desc. ring in bytes */
92
93 u16 count; /* number of desc. in the ring */
94 u8 queue_index; /* logical index of the ring*/
95 u8 reg_idx; /* physical index of the ring */
96 bool launchtime_enable; /* true if LaunchTime is enabled */
97
98 u32 start_time;
99 u32 end_time;
100
101 /* CBS parameters */
102 bool cbs_enable; /* indicates if CBS is enabled */
103 s32 idleslope; /* idleSlope in kbps */
104 s32 sendslope; /* sendSlope in kbps */
105 s32 hicredit; /* hiCredit in bytes */
106 s32 locredit; /* loCredit in bytes */
107
108 /* everything past this point are written often */
109 u16 next_to_clean;
110 u16 next_to_use;
111 u16 next_to_alloc;
112
113 union {
114 /* TX */
115 struct {
116 struct igc_tx_queue_stats tx_stats;
117 struct u64_stats_sync tx_syncp;
118 struct u64_stats_sync tx_syncp2;
119 };
120 /* RX */
121 struct {
122 struct igc_rx_queue_stats rx_stats;
123 struct igc_rx_packet_stats pkt_stats;
124 struct u64_stats_sync rx_syncp;
125 struct sk_buff *skb;
126 };
127 };
128
129 struct xdp_rxq_info xdp_rxq;
130 struct xsk_buff_pool *xsk_pool;
131 } ____cacheline_internodealigned_in_smp;
132
133 /* Board specific private data structure */
134 struct igc_adapter {
135 struct net_device *netdev;
136
137 struct ethtool_eee eee;
138 u16 eee_advert;
139
140 unsigned long state;
141 unsigned int flags;
142 unsigned int num_q_vectors;
143
144 struct msix_entry *msix_entries;
145
146 /* TX */
147 u16 tx_work_limit;
148 u32 tx_timeout_count;
149 int num_tx_queues;
150 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
151
152 /* RX */
153 int num_rx_queues;
154 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
155
156 struct timer_list watchdog_timer;
157 struct timer_list dma_err_timer;
158 struct timer_list phy_info_timer;
159
160 u32 wol;
161 u32 en_mng_pt;
162 u16 link_speed;
163 u16 link_duplex;
164
165 u8 port_num;
166
167 u8 __iomem *io_addr;
168 /* Interrupt Throttle Rate */
169 u32 rx_itr_setting;
170 u32 tx_itr_setting;
171
172 struct work_struct reset_task;
173 struct work_struct watchdog_task;
174 struct work_struct dma_err_task;
175 bool fc_autoneg;
176
177 u8 tx_timeout_factor;
178
179 int msg_enable;
180 u32 max_frame_size;
181 u32 min_frame_size;
182
183 ktime_t base_time;
184 ktime_t cycle_time;
185
186 /* OS defined structs */
187 struct pci_dev *pdev;
188 /* lock for statistics */
189 spinlock_t stats64_lock;
190 struct rtnl_link_stats64 stats64;
191
192 /* structs defined in igc_hw.h */
193 struct igc_hw hw;
194 struct igc_hw_stats stats;
195
196 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
197 u32 eims_enable_mask;
198 u32 eims_other;
199
200 u16 tx_ring_count;
201 u16 rx_ring_count;
202
203 u32 tx_hwtstamp_timeouts;
204 u32 tx_hwtstamp_skipped;
205 u32 rx_hwtstamp_cleared;
206
207 u32 rss_queues;
208 u32 rss_indir_tbl_init;
209
210 /* Any access to elements in nfc_rule_list is protected by the
211 * nfc_rule_lock.
212 */
213 struct mutex nfc_rule_lock;
214 struct list_head nfc_rule_list;
215 unsigned int nfc_rule_count;
216
217 u8 rss_indir_tbl[IGC_RETA_SIZE];
218
219 unsigned long link_check_timeout;
220 struct igc_info ei;
221
222 u32 test_icr;
223
224 struct ptp_clock *ptp_clock;
225 struct ptp_clock_info ptp_caps;
226 struct work_struct ptp_tx_work;
227 struct sk_buff *ptp_tx_skb;
228 struct hwtstamp_config tstamp_config;
229 unsigned long ptp_tx_start;
230 unsigned int ptp_flags;
231 /* System time value lock */
232 spinlock_t tmreg_lock;
233 struct cyclecounter cc;
234 struct timecounter tc;
235 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
236 ktime_t ptp_reset_start; /* Reset time in clock mono */
237 struct system_time_snapshot snapshot;
238
239 char fw_version[32];
240
241 struct bpf_prog *xdp_prog;
242
243 bool pps_sys_wrap_on;
244
245 struct ptp_pin_desc sdp_config[IGC_N_SDP];
246 struct {
247 struct timespec64 start;
248 struct timespec64 period;
249 } perout[IGC_N_PEROUT];
250 };
251
252 void igc_up(struct igc_adapter *adapter);
253 void igc_down(struct igc_adapter *adapter);
254 int igc_open(struct net_device *netdev);
255 int igc_close(struct net_device *netdev);
256 int igc_setup_tx_resources(struct igc_ring *ring);
257 int igc_setup_rx_resources(struct igc_ring *ring);
258 void igc_free_tx_resources(struct igc_ring *ring);
259 void igc_free_rx_resources(struct igc_ring *ring);
260 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
261 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
262 const u32 max_rss_queues);
263 int igc_reinit_queues(struct igc_adapter *adapter);
264 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
265 bool igc_has_link(struct igc_adapter *adapter);
266 void igc_reset(struct igc_adapter *adapter);
267 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);
268 void igc_update_stats(struct igc_adapter *adapter);
269 void igc_disable_rx_ring(struct igc_ring *ring);
270 void igc_enable_rx_ring(struct igc_ring *ring);
271 void igc_disable_tx_ring(struct igc_ring *ring);
272 void igc_enable_tx_ring(struct igc_ring *ring);
273 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
274
275 /* igc_dump declarations */
276 void igc_rings_dump(struct igc_adapter *adapter);
277 void igc_regs_dump(struct igc_adapter *adapter);
278
279 extern char igc_driver_name[];
280
281 #define IGC_REGS_LEN 740
282
283 /* flags controlling PTP/1588 function */
284 #define IGC_PTP_ENABLED BIT(0)
285
286 /* Flags definitions */
287 #define IGC_FLAG_HAS_MSI BIT(0)
288 #define IGC_FLAG_QUEUE_PAIRS BIT(3)
289 #define IGC_FLAG_DMAC BIT(4)
290 #define IGC_FLAG_PTP BIT(8)
291 #define IGC_FLAG_WOL_SUPPORTED BIT(8)
292 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
293 #define IGC_FLAG_MEDIA_RESET BIT(10)
294 #define IGC_FLAG_MAS_ENABLE BIT(12)
295 #define IGC_FLAG_HAS_MSIX BIT(13)
296 #define IGC_FLAG_EEE BIT(14)
297 #define IGC_FLAG_VLAN_PROMISC BIT(15)
298 #define IGC_FLAG_RX_LEGACY BIT(16)
299 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
300 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18)
301
302 #define IGC_FLAG_TSN_ANY_ENABLED \
303 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED)
304
305 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
306 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
307
308 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
309 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
310 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
311
312 /* Interrupt defines */
313 #define IGC_START_ITR 648 /* ~6000 ints/sec */
314 #define IGC_4K_ITR 980
315 #define IGC_20K_ITR 196
316 #define IGC_70K_ITR 56
317
318 #define IGC_DEFAULT_ITR 3 /* dynamic */
319 #define IGC_MAX_ITR_USECS 10000
320 #define IGC_MIN_ITR_USECS 10
321 #define NON_Q_VECTORS 1
322 #define MAX_MSIX_ENTRIES 10
323
324 /* TX/RX descriptor defines */
325 #define IGC_DEFAULT_TXD 256
326 #define IGC_DEFAULT_TX_WORK 128
327 #define IGC_MIN_TXD 80
328 #define IGC_MAX_TXD 4096
329
330 #define IGC_DEFAULT_RXD 256
331 #define IGC_MIN_RXD 80
332 #define IGC_MAX_RXD 4096
333
334 /* Supported Rx Buffer Sizes */
335 #define IGC_RXBUFFER_256 256
336 #define IGC_RXBUFFER_2048 2048
337 #define IGC_RXBUFFER_3072 3072
338
339 #define AUTO_ALL_MODES 0
340 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256
341
342 /* Transmit and receive latency (for PTP timestamps) */
343 #define IGC_I225_TX_LATENCY_10 240
344 #define IGC_I225_TX_LATENCY_100 58
345 #define IGC_I225_TX_LATENCY_1000 80
346 #define IGC_I225_TX_LATENCY_2500 1325
347 #define IGC_I225_RX_LATENCY_10 6450
348 #define IGC_I225_RX_LATENCY_100 185
349 #define IGC_I225_RX_LATENCY_1000 300
350 #define IGC_I225_RX_LATENCY_2500 1485
351
352 /* RX and TX descriptor control thresholds.
353 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
354 * descriptors available in its onboard memory.
355 * Setting this to 0 disables RX descriptor prefetch.
356 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
357 * available in host memory.
358 * If PTHRESH is 0, this should also be 0.
359 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
360 * descriptors until either it has this many to write back, or the
361 * ITR timer expires.
362 */
363 #define IGC_RX_PTHRESH 8
364 #define IGC_RX_HTHRESH 8
365 #define IGC_TX_PTHRESH 8
366 #define IGC_TX_HTHRESH 1
367 #define IGC_RX_WTHRESH 4
368 #define IGC_TX_WTHRESH 16
369
370 #define IGC_RX_DMA_ATTR \
371 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
372
373 #define IGC_TS_HDR_LEN 16
374
375 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
376
377 #if (PAGE_SIZE < 8192)
378 #define IGC_MAX_FRAME_BUILD_SKB \
379 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
380 #else
381 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
382 #endif
383
384 /* How many Rx Buffers do we bundle into one write to the hardware ? */
385 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
386
387 /* VLAN info */
388 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
389 #define IGC_TX_FLAGS_VLAN_SHIFT 16
390
391 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
igc_test_staterr(union igc_adv_rx_desc * rx_desc,const u32 stat_err_bits)392 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
393 const u32 stat_err_bits)
394 {
395 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
396 }
397
398 enum igc_state_t {
399 __IGC_TESTING,
400 __IGC_RESETTING,
401 __IGC_DOWN,
402 __IGC_PTP_TX_IN_PROGRESS,
403 };
404
405 enum igc_tx_flags {
406 /* cmd_type flags */
407 IGC_TX_FLAGS_VLAN = 0x01,
408 IGC_TX_FLAGS_TSO = 0x02,
409 IGC_TX_FLAGS_TSTAMP = 0x04,
410
411 /* olinfo flags */
412 IGC_TX_FLAGS_IPV4 = 0x10,
413 IGC_TX_FLAGS_CSUM = 0x20,
414 };
415
416 enum igc_boards {
417 board_base,
418 };
419
420 /* The largest size we can write to the descriptor is 65535. In order to
421 * maintain a power of two alignment we have to limit ourselves to 32K.
422 */
423 #define IGC_MAX_TXD_PWR 15
424 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
425
426 /* Tx Descriptors needed, worst case */
427 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
428 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
429
430 enum igc_tx_buffer_type {
431 IGC_TX_BUFFER_TYPE_SKB,
432 IGC_TX_BUFFER_TYPE_XDP,
433 IGC_TX_BUFFER_TYPE_XSK,
434 };
435
436 /* wrapper around a pointer to a socket buffer,
437 * so a DMA handle can be stored along with the buffer
438 */
439 struct igc_tx_buffer {
440 union igc_adv_tx_desc *next_to_watch;
441 unsigned long time_stamp;
442 enum igc_tx_buffer_type type;
443 union {
444 struct sk_buff *skb;
445 struct xdp_frame *xdpf;
446 };
447 unsigned int bytecount;
448 u16 gso_segs;
449 __be16 protocol;
450
451 DEFINE_DMA_UNMAP_ADDR(dma);
452 DEFINE_DMA_UNMAP_LEN(len);
453 u32 tx_flags;
454 };
455
456 struct igc_rx_buffer {
457 union {
458 struct {
459 dma_addr_t dma;
460 struct page *page;
461 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
462 __u32 page_offset;
463 #else
464 __u16 page_offset;
465 #endif
466 __u16 pagecnt_bias;
467 };
468 struct xdp_buff *xdp;
469 };
470 };
471
472 struct igc_q_vector {
473 struct igc_adapter *adapter; /* backlink */
474 void __iomem *itr_register;
475 u32 eims_value; /* EIMS mask value */
476
477 u16 itr_val;
478 u8 set_itr;
479
480 struct igc_ring_container rx, tx;
481
482 struct napi_struct napi;
483
484 struct rcu_head rcu; /* to avoid race with update stats on free */
485 char name[IFNAMSIZ + 9];
486 struct net_device poll_dev;
487
488 /* for dynamic allocation of rings associated with this q_vector */
489 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
490 };
491
492 enum igc_filter_match_flags {
493 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),
494 IGC_FILTER_FLAG_VLAN_TCI = BIT(1),
495 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),
496 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),
497 IGC_FILTER_FLAG_USER_DATA = BIT(4),
498 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),
499 };
500
501 struct igc_nfc_filter {
502 u8 match_flags;
503 u16 etype;
504 __be16 vlan_etype;
505 u16 vlan_tci;
506 u8 src_addr[ETH_ALEN];
507 u8 dst_addr[ETH_ALEN];
508 u8 user_data[8];
509 u8 user_mask[8];
510 u8 flex_index;
511 u8 rx_queue;
512 u8 prio;
513 u8 immediate_irq;
514 u8 drop;
515 };
516
517 struct igc_nfc_rule {
518 struct list_head list;
519 struct igc_nfc_filter filter;
520 u32 location;
521 u16 action;
522 bool flex;
523 };
524
525 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
526 * based, 8 ethertype based and 32 Flex filter based rules.
527 */
528 #define IGC_MAX_RXNFC_RULES 64
529
530 struct igc_flex_filter {
531 u8 index;
532 u8 data[128];
533 u8 mask[16];
534 u8 length;
535 u8 rx_queue;
536 u8 prio;
537 u8 immediate_irq;
538 u8 drop;
539 };
540
541 /* igc_desc_unused - calculate if we have unused descriptors */
igc_desc_unused(const struct igc_ring * ring)542 static inline u16 igc_desc_unused(const struct igc_ring *ring)
543 {
544 u16 ntc = ring->next_to_clean;
545 u16 ntu = ring->next_to_use;
546
547 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
548 }
549
igc_get_phy_info(struct igc_hw * hw)550 static inline s32 igc_get_phy_info(struct igc_hw *hw)
551 {
552 if (hw->phy.ops.get_phy_info)
553 return hw->phy.ops.get_phy_info(hw);
554
555 return 0;
556 }
557
igc_reset_phy(struct igc_hw * hw)558 static inline s32 igc_reset_phy(struct igc_hw *hw)
559 {
560 if (hw->phy.ops.reset)
561 return hw->phy.ops.reset(hw);
562
563 return 0;
564 }
565
txring_txq(const struct igc_ring * tx_ring)566 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
567 {
568 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
569 }
570
571 enum igc_ring_flags_t {
572 IGC_RING_FLAG_RX_3K_BUFFER,
573 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
574 IGC_RING_FLAG_RX_SCTP_CSUM,
575 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
576 IGC_RING_FLAG_TX_CTX_IDX,
577 IGC_RING_FLAG_TX_DETECT_HANG,
578 IGC_RING_FLAG_AF_XDP_ZC,
579 };
580
581 #define ring_uses_large_buffer(ring) \
582 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
583 #define set_ring_uses_large_buffer(ring) \
584 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
585 #define clear_ring_uses_large_buffer(ring) \
586 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
587
588 #define ring_uses_build_skb(ring) \
589 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
590
igc_rx_bufsz(struct igc_ring * ring)591 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
592 {
593 #if (PAGE_SIZE < 8192)
594 if (ring_uses_large_buffer(ring))
595 return IGC_RXBUFFER_3072;
596
597 if (ring_uses_build_skb(ring))
598 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
599 #endif
600 return IGC_RXBUFFER_2048;
601 }
602
igc_rx_pg_order(struct igc_ring * ring)603 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
604 {
605 #if (PAGE_SIZE < 8192)
606 if (ring_uses_large_buffer(ring))
607 return 1;
608 #endif
609 return 0;
610 }
611
igc_read_phy_reg(struct igc_hw * hw,u32 offset,u16 * data)612 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
613 {
614 if (hw->phy.ops.read_reg)
615 return hw->phy.ops.read_reg(hw, offset, data);
616
617 return -EOPNOTSUPP;
618 }
619
620 void igc_reinit_locked(struct igc_adapter *);
621 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
622 u32 location);
623 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
624 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
625
626 void igc_ptp_init(struct igc_adapter *adapter);
627 void igc_ptp_reset(struct igc_adapter *adapter);
628 void igc_ptp_suspend(struct igc_adapter *adapter);
629 void igc_ptp_stop(struct igc_adapter *adapter);
630 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
631 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
632 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
633 void igc_ptp_tx_hang(struct igc_adapter *adapter);
634 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
635
636 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
637
638 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
639
640 #define IGC_RX_DESC(R, i) \
641 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
642 #define IGC_TX_DESC(R, i) \
643 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
644 #define IGC_TX_CTXTDESC(R, i) \
645 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
646
647 #endif /* _IGC_H_ */
648
