1 /*
2  * CAN bus driver for Bosch C_CAN controller
3  *
4  * Copyright (C) 2010 ST Microelectronics
5  * Bhupesh Sharma <bhupesh.sharma@st.com>
6  *
7  * Borrowed heavily from the C_CAN driver originally written by:
8  * Copyright (C) 2007
9  * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10  * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
11  *
12  * TX and RX NAPI implementation has been borrowed from at91 CAN driver
13  * written by:
14  * Copyright
15  * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16  * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
17  *
18  * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19  * Bosch C_CAN user manual can be obtained from:
20  * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21  * users_manual_c_can.pdf
22  *
23  * This file is licensed under the terms of the GNU General Public
24  * License version 2. This program is licensed "as is" without any
25  * warranty of any kind, whether express or implied.
26  */
27 
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/netdevice.h>
33 #include <linux/if_arp.h>
34 #include <linux/if_ether.h>
35 #include <linux/list.h>
36 #include <linux/io.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/pinctrl/consumer.h>
39 
40 #include <linux/can.h>
41 #include <linux/can/dev.h>
42 #include <linux/can/error.h>
43 #include <linux/can/led.h>
44 
45 #include "c_can.h"
46 
47 /* Number of interface registers */
48 #define IF_ENUM_REG_LEN		11
49 #define C_CAN_IFACE(reg, iface)	(C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN)
50 
51 /* control extension register D_CAN specific */
52 #define CONTROL_EX_PDR		BIT(8)
53 
54 /* control register */
55 #define CONTROL_SWR		BIT(15)
56 #define CONTROL_TEST		BIT(7)
57 #define CONTROL_CCE		BIT(6)
58 #define CONTROL_DISABLE_AR	BIT(5)
59 #define CONTROL_ENABLE_AR	(0 << 5)
60 #define CONTROL_EIE		BIT(3)
61 #define CONTROL_SIE		BIT(2)
62 #define CONTROL_IE		BIT(1)
63 #define CONTROL_INIT		BIT(0)
64 
65 #define CONTROL_IRQMSK		(CONTROL_EIE | CONTROL_IE | CONTROL_SIE)
66 
67 /* test register */
68 #define TEST_RX			BIT(7)
69 #define TEST_TX1		BIT(6)
70 #define TEST_TX2		BIT(5)
71 #define TEST_LBACK		BIT(4)
72 #define TEST_SILENT		BIT(3)
73 #define TEST_BASIC		BIT(2)
74 
75 /* status register */
76 #define STATUS_PDA		BIT(10)
77 #define STATUS_BOFF		BIT(7)
78 #define STATUS_EWARN		BIT(6)
79 #define STATUS_EPASS		BIT(5)
80 #define STATUS_RXOK		BIT(4)
81 #define STATUS_TXOK		BIT(3)
82 
83 /* error counter register */
84 #define ERR_CNT_TEC_MASK	0xff
85 #define ERR_CNT_TEC_SHIFT	0
86 #define ERR_CNT_REC_SHIFT	8
87 #define ERR_CNT_REC_MASK	(0x7f << ERR_CNT_REC_SHIFT)
88 #define ERR_CNT_RP_SHIFT	15
89 #define ERR_CNT_RP_MASK		(0x1 << ERR_CNT_RP_SHIFT)
90 
91 /* bit-timing register */
92 #define BTR_BRP_MASK		0x3f
93 #define BTR_BRP_SHIFT		0
94 #define BTR_SJW_SHIFT		6
95 #define BTR_SJW_MASK		(0x3 << BTR_SJW_SHIFT)
96 #define BTR_TSEG1_SHIFT		8
97 #define BTR_TSEG1_MASK		(0xf << BTR_TSEG1_SHIFT)
98 #define BTR_TSEG2_SHIFT		12
99 #define BTR_TSEG2_MASK		(0x7 << BTR_TSEG2_SHIFT)
100 
101 /* interrupt register */
102 #define INT_STS_PENDING		0x8000
103 
104 /* brp extension register */
105 #define BRP_EXT_BRPE_MASK	0x0f
106 #define BRP_EXT_BRPE_SHIFT	0
107 
108 /* IFx command request */
109 #define IF_COMR_BUSY		BIT(15)
110 
111 /* IFx command mask */
112 #define IF_COMM_WR		BIT(7)
113 #define IF_COMM_MASK		BIT(6)
114 #define IF_COMM_ARB		BIT(5)
115 #define IF_COMM_CONTROL		BIT(4)
116 #define IF_COMM_CLR_INT_PND	BIT(3)
117 #define IF_COMM_TXRQST		BIT(2)
118 #define IF_COMM_CLR_NEWDAT	IF_COMM_TXRQST
119 #define IF_COMM_DATAA		BIT(1)
120 #define IF_COMM_DATAB		BIT(0)
121 
122 /* TX buffer setup */
123 #define IF_COMM_TX		(IF_COMM_ARB | IF_COMM_CONTROL | \
124 				 IF_COMM_TXRQST |		 \
125 				 IF_COMM_DATAA | IF_COMM_DATAB)
126 
127 /* For the low buffers we clear the interrupt bit, but keep newdat */
128 #define IF_COMM_RCV_LOW		(IF_COMM_MASK | IF_COMM_ARB | \
129 				 IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \
130 				 IF_COMM_DATAA | IF_COMM_DATAB)
131 
132 /* For the high buffers we clear the interrupt bit and newdat */
133 #define IF_COMM_RCV_HIGH	(IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT)
134 
135 /* Receive setup of message objects */
136 #define IF_COMM_RCV_SETUP	(IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL)
137 
138 /* Invalidation of message objects */
139 #define IF_COMM_INVAL		(IF_COMM_ARB | IF_COMM_CONTROL)
140 
141 /* IFx arbitration */
142 #define IF_ARB_MSGVAL		BIT(31)
143 #define IF_ARB_MSGXTD		BIT(30)
144 #define IF_ARB_TRANSMIT		BIT(29)
145 
146 /* IFx message control */
147 #define IF_MCONT_NEWDAT		BIT(15)
148 #define IF_MCONT_MSGLST		BIT(14)
149 #define IF_MCONT_INTPND		BIT(13)
150 #define IF_MCONT_UMASK		BIT(12)
151 #define IF_MCONT_TXIE		BIT(11)
152 #define IF_MCONT_RXIE		BIT(10)
153 #define IF_MCONT_RMTEN		BIT(9)
154 #define IF_MCONT_TXRQST		BIT(8)
155 #define IF_MCONT_EOB		BIT(7)
156 #define IF_MCONT_DLC_MASK	0xf
157 
158 #define IF_MCONT_RCV		(IF_MCONT_RXIE | IF_MCONT_UMASK)
159 #define IF_MCONT_RCV_EOB	(IF_MCONT_RCV | IF_MCONT_EOB)
160 
161 #define IF_MCONT_TX		(IF_MCONT_TXIE | IF_MCONT_EOB)
162 
163 /* Use IF1 in NAPI path and IF2 in TX path */
164 #define IF_NAPI			0
165 #define IF_TX			1
166 
167 /* minimum timeout for checking BUSY status */
168 #define MIN_TIMEOUT_VALUE	6
169 
170 /* Wait for ~1 sec for INIT bit */
171 #define INIT_WAIT_MS		1000
172 
173 /* c_can lec values */
174 enum c_can_lec_type {
175 	LEC_NO_ERROR = 0,
176 	LEC_STUFF_ERROR,
177 	LEC_FORM_ERROR,
178 	LEC_ACK_ERROR,
179 	LEC_BIT1_ERROR,
180 	LEC_BIT0_ERROR,
181 	LEC_CRC_ERROR,
182 	LEC_UNUSED,
183 	LEC_MASK = LEC_UNUSED,
184 };
185 
186 /* c_can error types:
187  * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
188  */
189 enum c_can_bus_error_types {
190 	C_CAN_NO_ERROR = 0,
191 	C_CAN_BUS_OFF,
192 	C_CAN_ERROR_WARNING,
193 	C_CAN_ERROR_PASSIVE,
194 };
195 
196 static const struct can_bittiming_const c_can_bittiming_const = {
197 	.name = KBUILD_MODNAME,
198 	.tseg1_min = 2,		/* Time segment 1 = prop_seg + phase_seg1 */
199 	.tseg1_max = 16,
200 	.tseg2_min = 1,		/* Time segment 2 = phase_seg2 */
201 	.tseg2_max = 8,
202 	.sjw_max = 4,
203 	.brp_min = 1,
204 	.brp_max = 1024,	/* 6-bit BRP field + 4-bit BRPE field*/
205 	.brp_inc = 1,
206 };
207 
c_can_pm_runtime_get_sync(const struct c_can_priv * priv)208 static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv)
209 {
210 	if (priv->device)
211 		pm_runtime_get_sync(priv->device);
212 }
213 
c_can_pm_runtime_put_sync(const struct c_can_priv * priv)214 static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv)
215 {
216 	if (priv->device)
217 		pm_runtime_put_sync(priv->device);
218 }
219 
c_can_reset_ram(const struct c_can_priv * priv,bool enable)220 static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable)
221 {
222 	if (priv->raminit)
223 		priv->raminit(priv, enable);
224 }
225 
c_can_irq_control(struct c_can_priv * priv,bool enable)226 static void c_can_irq_control(struct c_can_priv *priv, bool enable)
227 {
228 	u32 ctrl = priv->read_reg(priv,	C_CAN_CTRL_REG) & ~CONTROL_IRQMSK;
229 
230 	if (enable)
231 		ctrl |= CONTROL_IRQMSK;
232 
233 	priv->write_reg(priv, C_CAN_CTRL_REG, ctrl);
234 }
235 
c_can_obj_update(struct net_device * dev,int iface,u32 cmd,u32 obj)236 static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj)
237 {
238 	struct c_can_priv *priv = netdev_priv(dev);
239 	int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface);
240 
241 	priv->write_reg32(priv, reg, (cmd << 16) | obj);
242 
243 	for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) {
244 		if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY))
245 			return;
246 		udelay(1);
247 	}
248 	netdev_err(dev, "Updating object timed out\n");
249 }
250 
c_can_object_get(struct net_device * dev,int iface,u32 obj,u32 cmd)251 static inline void c_can_object_get(struct net_device *dev, int iface,
252 				    u32 obj, u32 cmd)
253 {
254 	c_can_obj_update(dev, iface, cmd, obj);
255 }
256 
c_can_object_put(struct net_device * dev,int iface,u32 obj,u32 cmd)257 static inline void c_can_object_put(struct net_device *dev, int iface,
258 				    u32 obj, u32 cmd)
259 {
260 	c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj);
261 }
262 
263 /* Note: According to documentation clearing TXIE while MSGVAL is set
264  * is not allowed, but works nicely on C/DCAN. And that lowers the I/O
265  * load significantly.
266  */
c_can_inval_tx_object(struct net_device * dev,int iface,int obj)267 static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj)
268 {
269 	struct c_can_priv *priv = netdev_priv(dev);
270 
271 	priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0);
272 	c_can_object_put(dev, iface, obj, IF_COMM_INVAL);
273 }
274 
c_can_inval_msg_object(struct net_device * dev,int iface,int obj)275 static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj)
276 {
277 	struct c_can_priv *priv = netdev_priv(dev);
278 
279 	priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), 0);
280 	c_can_inval_tx_object(dev, iface, obj);
281 }
282 
c_can_setup_tx_object(struct net_device * dev,int iface,struct can_frame * frame,int idx)283 static void c_can_setup_tx_object(struct net_device *dev, int iface,
284 				  struct can_frame *frame, int idx)
285 {
286 	struct c_can_priv *priv = netdev_priv(dev);
287 	u16 ctrl = IF_MCONT_TX | frame->len;
288 	bool rtr = frame->can_id & CAN_RTR_FLAG;
289 	u32 arb = IF_ARB_MSGVAL;
290 	int i;
291 
292 	if (frame->can_id & CAN_EFF_FLAG) {
293 		arb |= frame->can_id & CAN_EFF_MASK;
294 		arb |= IF_ARB_MSGXTD;
295 	} else {
296 		arb |= (frame->can_id & CAN_SFF_MASK) << 18;
297 	}
298 
299 	if (!rtr)
300 		arb |= IF_ARB_TRANSMIT;
301 
302 	/* If we change the DIR bit, we need to invalidate the buffer
303 	 * first, i.e. clear the MSGVAL flag in the arbiter.
304 	 */
305 	if (rtr != (bool)test_bit(idx, &priv->tx_dir)) {
306 		u32 obj = idx + priv->msg_obj_tx_first;
307 
308 		c_can_inval_msg_object(dev, iface, obj);
309 		change_bit(idx, &priv->tx_dir);
310 	}
311 
312 	priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb);
313 
314 	priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
315 
316 	if (priv->type == BOSCH_D_CAN) {
317 		u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface);
318 
319 		for (i = 0; i < frame->len; i += 4, dreg += 2) {
320 			data = (u32)frame->data[i];
321 			data |= (u32)frame->data[i + 1] << 8;
322 			data |= (u32)frame->data[i + 2] << 16;
323 			data |= (u32)frame->data[i + 3] << 24;
324 			priv->write_reg32(priv, dreg, data);
325 		}
326 	} else {
327 		for (i = 0; i < frame->len; i += 2) {
328 			priv->write_reg(priv,
329 					C_CAN_IFACE(DATA1_REG, iface) + i / 2,
330 					frame->data[i] |
331 					(frame->data[i + 1] << 8));
332 		}
333 	}
334 }
335 
c_can_handle_lost_msg_obj(struct net_device * dev,int iface,int objno,u32 ctrl)336 static int c_can_handle_lost_msg_obj(struct net_device *dev,
337 				     int iface, int objno, u32 ctrl)
338 {
339 	struct net_device_stats *stats = &dev->stats;
340 	struct c_can_priv *priv = netdev_priv(dev);
341 	struct can_frame *frame;
342 	struct sk_buff *skb;
343 
344 	ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT);
345 	priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl);
346 	c_can_object_put(dev, iface, objno, IF_COMM_CONTROL);
347 
348 	stats->rx_errors++;
349 	stats->rx_over_errors++;
350 
351 	/* create an error msg */
352 	skb = alloc_can_err_skb(dev, &frame);
353 	if (unlikely(!skb))
354 		return 0;
355 
356 	frame->can_id |= CAN_ERR_CRTL;
357 	frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
358 
359 	netif_receive_skb(skb);
360 	return 1;
361 }
362 
c_can_read_msg_object(struct net_device * dev,int iface,u32 ctrl)363 static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl)
364 {
365 	struct net_device_stats *stats = &dev->stats;
366 	struct c_can_priv *priv = netdev_priv(dev);
367 	struct can_frame *frame;
368 	struct sk_buff *skb;
369 	u32 arb, data;
370 
371 	skb = alloc_can_skb(dev, &frame);
372 	if (!skb) {
373 		stats->rx_dropped++;
374 		return -ENOMEM;
375 	}
376 
377 	frame->len = can_cc_dlc2len(ctrl & 0x0F);
378 
379 	arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface));
380 
381 	if (arb & IF_ARB_MSGXTD)
382 		frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG;
383 	else
384 		frame->can_id = (arb >> 18) & CAN_SFF_MASK;
385 
386 	if (arb & IF_ARB_TRANSMIT) {
387 		frame->can_id |= CAN_RTR_FLAG;
388 	} else {
389 		int i, dreg = C_CAN_IFACE(DATA1_REG, iface);
390 
391 		if (priv->type == BOSCH_D_CAN) {
392 			for (i = 0; i < frame->len; i += 4, dreg += 2) {
393 				data = priv->read_reg32(priv, dreg);
394 				frame->data[i] = data;
395 				frame->data[i + 1] = data >> 8;
396 				frame->data[i + 2] = data >> 16;
397 				frame->data[i + 3] = data >> 24;
398 			}
399 		} else {
400 			for (i = 0; i < frame->len; i += 2, dreg++) {
401 				data = priv->read_reg(priv, dreg);
402 				frame->data[i] = data;
403 				frame->data[i + 1] = data >> 8;
404 			}
405 		}
406 	}
407 
408 	stats->rx_packets++;
409 	stats->rx_bytes += frame->len;
410 
411 	netif_receive_skb(skb);
412 	return 0;
413 }
414 
c_can_setup_receive_object(struct net_device * dev,int iface,u32 obj,u32 mask,u32 id,u32 mcont)415 static void c_can_setup_receive_object(struct net_device *dev, int iface,
416 				       u32 obj, u32 mask, u32 id, u32 mcont)
417 {
418 	struct c_can_priv *priv = netdev_priv(dev);
419 
420 	mask |= BIT(29);
421 	priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask);
422 
423 	id |= IF_ARB_MSGVAL;
424 	priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id);
425 
426 	priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont);
427 	c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP);
428 }
429 
c_can_tx_busy(const struct c_can_priv * priv,const struct c_can_tx_ring * tx_ring)430 static bool c_can_tx_busy(const struct c_can_priv *priv,
431 			  const struct c_can_tx_ring *tx_ring)
432 {
433 	if (c_can_get_tx_free(tx_ring) > 0)
434 		return false;
435 
436 	netif_stop_queue(priv->dev);
437 
438 	/* Memory barrier before checking tx_free (head and tail) */
439 	smp_mb();
440 
441 	if (c_can_get_tx_free(tx_ring) == 0) {
442 		netdev_dbg(priv->dev,
443 			   "Stopping tx-queue (tx_head=0x%08x, tx_tail=0x%08x, len=%d).\n",
444 			   tx_ring->head, tx_ring->tail,
445 			   tx_ring->head - tx_ring->tail);
446 		return true;
447 	}
448 
449 	netif_start_queue(priv->dev);
450 	return false;
451 }
452 
c_can_start_xmit(struct sk_buff * skb,struct net_device * dev)453 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
454 				    struct net_device *dev)
455 {
456 	struct can_frame *frame = (struct can_frame *)skb->data;
457 	struct c_can_priv *priv = netdev_priv(dev);
458 	struct c_can_tx_ring *tx_ring = &priv->tx;
459 	u32 idx, obj, cmd = IF_COMM_TX;
460 
461 	if (can_dropped_invalid_skb(dev, skb))
462 		return NETDEV_TX_OK;
463 
464 	if (c_can_tx_busy(priv, tx_ring))
465 		return NETDEV_TX_BUSY;
466 
467 	idx = c_can_get_tx_head(tx_ring);
468 	tx_ring->head++;
469 	if (c_can_get_tx_free(tx_ring) == 0)
470 		netif_stop_queue(dev);
471 
472 	if (idx < c_can_get_tx_tail(tx_ring))
473 		cmd &= ~IF_COMM_TXRQST; /* Cache the message */
474 
475 	/* Store the message in the interface so we can call
476 	 * can_put_echo_skb(). We must do this before we enable
477 	 * transmit as we might race against do_tx().
478 	 */
479 	c_can_setup_tx_object(dev, IF_TX, frame, idx);
480 	priv->dlc[idx] = frame->len;
481 	can_put_echo_skb(skb, dev, idx, 0);
482 	obj = idx + priv->msg_obj_tx_first;
483 	c_can_object_put(dev, IF_TX, obj, cmd);
484 
485 	return NETDEV_TX_OK;
486 }
487 
c_can_wait_for_ctrl_init(struct net_device * dev,struct c_can_priv * priv,u32 init)488 static int c_can_wait_for_ctrl_init(struct net_device *dev,
489 				    struct c_can_priv *priv, u32 init)
490 {
491 	int retry = 0;
492 
493 	while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) {
494 		udelay(10);
495 		if (retry++ > 1000) {
496 			netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n");
497 			return -EIO;
498 		}
499 	}
500 	return 0;
501 }
502 
c_can_set_bittiming(struct net_device * dev)503 static int c_can_set_bittiming(struct net_device *dev)
504 {
505 	unsigned int reg_btr, reg_brpe, ctrl_save;
506 	u8 brp, brpe, sjw, tseg1, tseg2;
507 	u32 ten_bit_brp;
508 	struct c_can_priv *priv = netdev_priv(dev);
509 	const struct can_bittiming *bt = &priv->can.bittiming;
510 	int res;
511 
512 	/* c_can provides a 6-bit brp and 4-bit brpe fields */
513 	ten_bit_brp = bt->brp - 1;
514 	brp = ten_bit_brp & BTR_BRP_MASK;
515 	brpe = ten_bit_brp >> 6;
516 
517 	sjw = bt->sjw - 1;
518 	tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
519 	tseg2 = bt->phase_seg2 - 1;
520 	reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
521 			(tseg2 << BTR_TSEG2_SHIFT);
522 	reg_brpe = brpe & BRP_EXT_BRPE_MASK;
523 
524 	netdev_info(dev,
525 		    "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
526 
527 	ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG);
528 	ctrl_save &= ~CONTROL_INIT;
529 	priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT);
530 	res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT);
531 	if (res)
532 		return res;
533 
534 	priv->write_reg(priv, C_CAN_BTR_REG, reg_btr);
535 	priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe);
536 	priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save);
537 
538 	return c_can_wait_for_ctrl_init(dev, priv, 0);
539 }
540 
541 /* Configure C_CAN message objects for Tx and Rx purposes:
542  * C_CAN provides a total of 32 message objects that can be configured
543  * either for Tx or Rx purposes. Here the first 16 message objects are used as
544  * a reception FIFO. The end of reception FIFO is signified by the EoB bit
545  * being SET. The remaining 16 message objects are kept aside for Tx purposes.
546  * See user guide document for further details on configuring message
547  * objects.
548  */
c_can_configure_msg_objects(struct net_device * dev)549 static void c_can_configure_msg_objects(struct net_device *dev)
550 {
551 	struct c_can_priv *priv = netdev_priv(dev);
552 	int i;
553 
554 	/* first invalidate all message objects */
555 	for (i = priv->msg_obj_rx_first; i <= priv->msg_obj_num; i++)
556 		c_can_inval_msg_object(dev, IF_NAPI, i);
557 
558 	/* setup receive message objects */
559 	for (i = priv->msg_obj_rx_first; i < priv->msg_obj_rx_last; i++)
560 		c_can_setup_receive_object(dev, IF_NAPI, i, 0, 0, IF_MCONT_RCV);
561 
562 	c_can_setup_receive_object(dev, IF_NAPI, priv->msg_obj_rx_last, 0, 0,
563 				   IF_MCONT_RCV_EOB);
564 }
565 
c_can_software_reset(struct net_device * dev)566 static int c_can_software_reset(struct net_device *dev)
567 {
568 	struct c_can_priv *priv = netdev_priv(dev);
569 	int retry = 0;
570 
571 	if (priv->type != BOSCH_D_CAN)
572 		return 0;
573 
574 	priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT);
575 	while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) {
576 		msleep(20);
577 		if (retry++ > 100) {
578 			netdev_err(dev, "CCTRL: software reset failed\n");
579 			return -EIO;
580 		}
581 	}
582 
583 	return 0;
584 }
585 
586 /* Configure C_CAN chip:
587  * - enable/disable auto-retransmission
588  * - set operating mode
589  * - configure message objects
590  */
c_can_chip_config(struct net_device * dev)591 static int c_can_chip_config(struct net_device *dev)
592 {
593 	struct c_can_priv *priv = netdev_priv(dev);
594 	struct c_can_tx_ring *tx_ring = &priv->tx;
595 	int err;
596 
597 	err = c_can_software_reset(dev);
598 	if (err)
599 		return err;
600 
601 	/* enable automatic retransmission */
602 	priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR);
603 
604 	if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) &&
605 	    (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) {
606 		/* loopback + silent mode : useful for hot self-test */
607 		priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
608 		priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT);
609 	} else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
610 		/* loopback mode : useful for self-test function */
611 		priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
612 		priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK);
613 	} else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
614 		/* silent mode : bus-monitoring mode */
615 		priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST);
616 		priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT);
617 	}
618 
619 	/* configure message objects */
620 	c_can_configure_msg_objects(dev);
621 
622 	/* set a `lec` value so that we can check for updates later */
623 	priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
624 
625 	/* Clear all internal status */
626 	tx_ring->head = 0;
627 	tx_ring->tail = 0;
628 	priv->tx_dir = 0;
629 
630 	/* set bittiming params */
631 	return c_can_set_bittiming(dev);
632 }
633 
c_can_start(struct net_device * dev)634 static int c_can_start(struct net_device *dev)
635 {
636 	struct c_can_priv *priv = netdev_priv(dev);
637 	int err;
638 	struct pinctrl *p;
639 
640 	/* basic c_can configuration */
641 	err = c_can_chip_config(dev);
642 	if (err)
643 		return err;
644 
645 	/* Setup the command for new messages */
646 	priv->comm_rcv_high = priv->type != BOSCH_D_CAN ?
647 		IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH;
648 
649 	priv->can.state = CAN_STATE_ERROR_ACTIVE;
650 
651 	/* Attempt to use "active" if available else use "default" */
652 	p = pinctrl_get_select(priv->device, "active");
653 	if (!IS_ERR(p))
654 		pinctrl_put(p);
655 	else
656 		pinctrl_pm_select_default_state(priv->device);
657 
658 	return 0;
659 }
660 
c_can_stop(struct net_device * dev)661 static void c_can_stop(struct net_device *dev)
662 {
663 	struct c_can_priv *priv = netdev_priv(dev);
664 
665 	c_can_irq_control(priv, false);
666 
667 	/* put ctrl to init on stop to end ongoing transmission */
668 	priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT);
669 
670 	/* deactivate pins */
671 	pinctrl_pm_select_sleep_state(dev->dev.parent);
672 	priv->can.state = CAN_STATE_STOPPED;
673 }
674 
c_can_set_mode(struct net_device * dev,enum can_mode mode)675 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
676 {
677 	struct c_can_priv *priv = netdev_priv(dev);
678 	int err;
679 
680 	switch (mode) {
681 	case CAN_MODE_START:
682 		err = c_can_start(dev);
683 		if (err)
684 			return err;
685 		netif_wake_queue(dev);
686 		c_can_irq_control(priv, true);
687 		break;
688 	default:
689 		return -EOPNOTSUPP;
690 	}
691 
692 	return 0;
693 }
694 
__c_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)695 static int __c_can_get_berr_counter(const struct net_device *dev,
696 				    struct can_berr_counter *bec)
697 {
698 	unsigned int reg_err_counter;
699 	struct c_can_priv *priv = netdev_priv(dev);
700 
701 	reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
702 	bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
703 				ERR_CNT_REC_SHIFT;
704 	bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
705 
706 	return 0;
707 }
708 
c_can_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)709 static int c_can_get_berr_counter(const struct net_device *dev,
710 				  struct can_berr_counter *bec)
711 {
712 	struct c_can_priv *priv = netdev_priv(dev);
713 	int err;
714 
715 	c_can_pm_runtime_get_sync(priv);
716 	err = __c_can_get_berr_counter(dev, bec);
717 	c_can_pm_runtime_put_sync(priv);
718 
719 	return err;
720 }
721 
c_can_do_tx(struct net_device * dev)722 static void c_can_do_tx(struct net_device *dev)
723 {
724 	struct c_can_priv *priv = netdev_priv(dev);
725 	struct c_can_tx_ring *tx_ring = &priv->tx;
726 	struct net_device_stats *stats = &dev->stats;
727 	u32 idx, obj, pkts = 0, bytes = 0, pend;
728 	u8 tail;
729 
730 	if (priv->msg_obj_tx_last > 32)
731 		pend = priv->read_reg32(priv, C_CAN_INTPND3_REG);
732 	else
733 		pend = priv->read_reg(priv, C_CAN_INTPND2_REG);
734 
735 	while ((idx = ffs(pend))) {
736 		idx--;
737 		pend &= ~BIT(idx);
738 		obj = idx + priv->msg_obj_tx_first;
739 
740 		/* We use IF_NAPI interface instead of IF_TX because we
741 		 * are called from c_can_poll(), which runs inside
742 		 * NAPI. We are not transmitting.
743 		 */
744 		c_can_inval_tx_object(dev, IF_NAPI, obj);
745 		can_get_echo_skb(dev, idx, NULL);
746 		bytes += priv->dlc[idx];
747 		pkts++;
748 	}
749 
750 	if (!pkts)
751 		return;
752 
753 	tx_ring->tail += pkts;
754 	if (c_can_get_tx_free(tx_ring)) {
755 		/* Make sure that anybody stopping the queue after
756 		 * this sees the new tx_ring->tail.
757 		 */
758 		smp_mb();
759 		netif_wake_queue(priv->dev);
760 	}
761 
762 	stats->tx_bytes += bytes;
763 	stats->tx_packets += pkts;
764 	can_led_event(dev, CAN_LED_EVENT_TX);
765 
766 	tail = c_can_get_tx_tail(tx_ring);
767 
768 	if (tail == 0) {
769 		u8 head = c_can_get_tx_head(tx_ring);
770 
771 		/* Start transmission for all cached messages */
772 		for (idx = tail; idx < head; idx++) {
773 			obj = idx + priv->msg_obj_tx_first;
774 			c_can_object_put(dev, IF_NAPI, obj, IF_COMM_TXRQST);
775 		}
776 	}
777 }
778 
779 /* If we have a gap in the pending bits, that means we either
780  * raced with the hardware or failed to readout all upper
781  * objects in the last run due to quota limit.
782  */
c_can_adjust_pending(u32 pend,u32 rx_mask)783 static u32 c_can_adjust_pending(u32 pend, u32 rx_mask)
784 {
785 	u32 weight, lasts;
786 
787 	if (pend == rx_mask)
788 		return pend;
789 
790 	/* If the last set bit is larger than the number of pending
791 	 * bits we have a gap.
792 	 */
793 	weight = hweight32(pend);
794 	lasts = fls(pend);
795 
796 	/* If the bits are linear, nothing to do */
797 	if (lasts == weight)
798 		return pend;
799 
800 	/* Find the first set bit after the gap. We walk backwards
801 	 * from the last set bit.
802 	 */
803 	for (lasts--; pend & BIT(lasts - 1); lasts--)
804 		;
805 
806 	return pend & ~GENMASK(lasts - 1, 0);
807 }
808 
c_can_rx_object_get(struct net_device * dev,struct c_can_priv * priv,u32 obj)809 static inline void c_can_rx_object_get(struct net_device *dev,
810 				       struct c_can_priv *priv, u32 obj)
811 {
812 	c_can_object_get(dev, IF_NAPI, obj, priv->comm_rcv_high);
813 }
814 
c_can_rx_finalize(struct net_device * dev,struct c_can_priv * priv,u32 obj)815 static inline void c_can_rx_finalize(struct net_device *dev,
816 				     struct c_can_priv *priv, u32 obj)
817 {
818 	if (priv->type != BOSCH_D_CAN)
819 		c_can_object_get(dev, IF_NAPI, obj, IF_COMM_CLR_NEWDAT);
820 }
821 
c_can_read_objects(struct net_device * dev,struct c_can_priv * priv,u32 pend,int quota)822 static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv,
823 			      u32 pend, int quota)
824 {
825 	u32 pkts = 0, ctrl, obj;
826 
827 	while ((obj = ffs(pend)) && quota > 0) {
828 		pend &= ~BIT(obj - 1);
829 
830 		c_can_rx_object_get(dev, priv, obj);
831 		ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_NAPI));
832 
833 		if (ctrl & IF_MCONT_MSGLST) {
834 			int n;
835 
836 			n = c_can_handle_lost_msg_obj(dev, IF_NAPI, obj, ctrl);
837 
838 			pkts += n;
839 			quota -= n;
840 			continue;
841 		}
842 
843 		/* This really should not happen, but this covers some
844 		 * odd HW behaviour. Do not remove that unless you
845 		 * want to brick your machine.
846 		 */
847 		if (!(ctrl & IF_MCONT_NEWDAT))
848 			continue;
849 
850 		/* read the data from the message object */
851 		c_can_read_msg_object(dev, IF_NAPI, ctrl);
852 
853 		c_can_rx_finalize(dev, priv, obj);
854 
855 		pkts++;
856 		quota--;
857 	}
858 
859 	return pkts;
860 }
861 
c_can_get_pending(struct c_can_priv * priv)862 static inline u32 c_can_get_pending(struct c_can_priv *priv)
863 {
864 	u32 pend;
865 
866 	if (priv->msg_obj_rx_last > 16)
867 		pend = priv->read_reg32(priv, C_CAN_NEWDAT1_REG);
868 	else
869 		pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG);
870 
871 	return pend;
872 }
873 
874 /* theory of operation:
875  *
876  * c_can core saves a received CAN message into the first free message
877  * object it finds free (starting with the lowest). Bits NEWDAT and
878  * INTPND are set for this message object indicating that a new message
879  * has arrived.
880  *
881  * We clear the newdat bit right away.
882  *
883  * This can result in packet reordering when the readout is slow.
884  */
c_can_do_rx_poll(struct net_device * dev,int quota)885 static int c_can_do_rx_poll(struct net_device *dev, int quota)
886 {
887 	struct c_can_priv *priv = netdev_priv(dev);
888 	u32 pkts = 0, pend = 0, toread, n;
889 
890 	while (quota > 0) {
891 		if (!pend) {
892 			pend = c_can_get_pending(priv);
893 			if (!pend)
894 				break;
895 			/* If the pending field has a gap, handle the
896 			 * bits above the gap first.
897 			 */
898 			toread = c_can_adjust_pending(pend,
899 						      priv->msg_obj_rx_mask);
900 		} else {
901 			toread = pend;
902 		}
903 		/* Remove the bits from pend */
904 		pend &= ~toread;
905 		/* Read the objects */
906 		n = c_can_read_objects(dev, priv, toread, quota);
907 		pkts += n;
908 		quota -= n;
909 	}
910 
911 	if (pkts)
912 		can_led_event(dev, CAN_LED_EVENT_RX);
913 
914 	return pkts;
915 }
916 
c_can_handle_state_change(struct net_device * dev,enum c_can_bus_error_types error_type)917 static int c_can_handle_state_change(struct net_device *dev,
918 				     enum c_can_bus_error_types error_type)
919 {
920 	unsigned int reg_err_counter;
921 	unsigned int rx_err_passive;
922 	struct c_can_priv *priv = netdev_priv(dev);
923 	struct net_device_stats *stats = &dev->stats;
924 	struct can_frame *cf;
925 	struct sk_buff *skb;
926 	struct can_berr_counter bec;
927 
928 	switch (error_type) {
929 	case C_CAN_NO_ERROR:
930 		priv->can.state = CAN_STATE_ERROR_ACTIVE;
931 		break;
932 	case C_CAN_ERROR_WARNING:
933 		/* error warning state */
934 		priv->can.can_stats.error_warning++;
935 		priv->can.state = CAN_STATE_ERROR_WARNING;
936 		break;
937 	case C_CAN_ERROR_PASSIVE:
938 		/* error passive state */
939 		priv->can.can_stats.error_passive++;
940 		priv->can.state = CAN_STATE_ERROR_PASSIVE;
941 		break;
942 	case C_CAN_BUS_OFF:
943 		/* bus-off state */
944 		priv->can.state = CAN_STATE_BUS_OFF;
945 		priv->can.can_stats.bus_off++;
946 		break;
947 	default:
948 		break;
949 	}
950 
951 	/* propagate the error condition to the CAN stack */
952 	skb = alloc_can_err_skb(dev, &cf);
953 	if (unlikely(!skb))
954 		return 0;
955 
956 	__c_can_get_berr_counter(dev, &bec);
957 	reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG);
958 	rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
959 				ERR_CNT_RP_SHIFT;
960 
961 	switch (error_type) {
962 	case C_CAN_NO_ERROR:
963 		/* error warning state */
964 		cf->can_id |= CAN_ERR_CRTL;
965 		cf->data[1] = CAN_ERR_CRTL_ACTIVE;
966 		cf->data[6] = bec.txerr;
967 		cf->data[7] = bec.rxerr;
968 		break;
969 	case C_CAN_ERROR_WARNING:
970 		/* error warning state */
971 		cf->can_id |= CAN_ERR_CRTL;
972 		cf->data[1] = (bec.txerr > bec.rxerr) ?
973 			CAN_ERR_CRTL_TX_WARNING :
974 			CAN_ERR_CRTL_RX_WARNING;
975 		cf->data[6] = bec.txerr;
976 		cf->data[7] = bec.rxerr;
977 
978 		break;
979 	case C_CAN_ERROR_PASSIVE:
980 		/* error passive state */
981 		cf->can_id |= CAN_ERR_CRTL;
982 		if (rx_err_passive)
983 			cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
984 		if (bec.txerr > 127)
985 			cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
986 
987 		cf->data[6] = bec.txerr;
988 		cf->data[7] = bec.rxerr;
989 		break;
990 	case C_CAN_BUS_OFF:
991 		/* bus-off state */
992 		cf->can_id |= CAN_ERR_BUSOFF;
993 		can_bus_off(dev);
994 		break;
995 	default:
996 		break;
997 	}
998 
999 	stats->rx_packets++;
1000 	stats->rx_bytes += cf->len;
1001 	netif_receive_skb(skb);
1002 
1003 	return 1;
1004 }
1005 
c_can_handle_bus_err(struct net_device * dev,enum c_can_lec_type lec_type)1006 static int c_can_handle_bus_err(struct net_device *dev,
1007 				enum c_can_lec_type lec_type)
1008 {
1009 	struct c_can_priv *priv = netdev_priv(dev);
1010 	struct net_device_stats *stats = &dev->stats;
1011 	struct can_frame *cf;
1012 	struct sk_buff *skb;
1013 
1014 	/* early exit if no lec update or no error.
1015 	 * no lec update means that no CAN bus event has been detected
1016 	 * since CPU wrote 0x7 value to status reg.
1017 	 */
1018 	if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
1019 		return 0;
1020 
1021 	if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
1022 		return 0;
1023 
1024 	/* common for all type of bus errors */
1025 	priv->can.can_stats.bus_error++;
1026 	stats->rx_errors++;
1027 
1028 	/* propagate the error condition to the CAN stack */
1029 	skb = alloc_can_err_skb(dev, &cf);
1030 	if (unlikely(!skb))
1031 		return 0;
1032 
1033 	/* check for 'last error code' which tells us the
1034 	 * type of the last error to occur on the CAN bus
1035 	 */
1036 	cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1037 
1038 	switch (lec_type) {
1039 	case LEC_STUFF_ERROR:
1040 		netdev_dbg(dev, "stuff error\n");
1041 		cf->data[2] |= CAN_ERR_PROT_STUFF;
1042 		break;
1043 	case LEC_FORM_ERROR:
1044 		netdev_dbg(dev, "form error\n");
1045 		cf->data[2] |= CAN_ERR_PROT_FORM;
1046 		break;
1047 	case LEC_ACK_ERROR:
1048 		netdev_dbg(dev, "ack error\n");
1049 		cf->data[3] = CAN_ERR_PROT_LOC_ACK;
1050 		break;
1051 	case LEC_BIT1_ERROR:
1052 		netdev_dbg(dev, "bit1 error\n");
1053 		cf->data[2] |= CAN_ERR_PROT_BIT1;
1054 		break;
1055 	case LEC_BIT0_ERROR:
1056 		netdev_dbg(dev, "bit0 error\n");
1057 		cf->data[2] |= CAN_ERR_PROT_BIT0;
1058 		break;
1059 	case LEC_CRC_ERROR:
1060 		netdev_dbg(dev, "CRC error\n");
1061 		cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ;
1062 		break;
1063 	default:
1064 		break;
1065 	}
1066 
1067 	stats->rx_packets++;
1068 	stats->rx_bytes += cf->len;
1069 	netif_receive_skb(skb);
1070 	return 1;
1071 }
1072 
c_can_poll(struct napi_struct * napi,int quota)1073 static int c_can_poll(struct napi_struct *napi, int quota)
1074 {
1075 	struct net_device *dev = napi->dev;
1076 	struct c_can_priv *priv = netdev_priv(dev);
1077 	u16 curr, last = priv->last_status;
1078 	int work_done = 0;
1079 
1080 	/* Only read the status register if a status interrupt was pending */
1081 	if (atomic_xchg(&priv->sie_pending, 0)) {
1082 		priv->last_status = priv->read_reg(priv, C_CAN_STS_REG);
1083 		curr = priv->last_status;
1084 		/* Ack status on C_CAN. D_CAN is self clearing */
1085 		if (priv->type != BOSCH_D_CAN)
1086 			priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED);
1087 	} else {
1088 		/* no change detected ... */
1089 		curr = last;
1090 	}
1091 
1092 	/* handle state changes */
1093 	if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) {
1094 		netdev_dbg(dev, "entered error warning state\n");
1095 		work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1096 	}
1097 
1098 	if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) {
1099 		netdev_dbg(dev, "entered error passive state\n");
1100 		work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1101 	}
1102 
1103 	if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) {
1104 		netdev_dbg(dev, "entered bus off state\n");
1105 		work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF);
1106 		goto end;
1107 	}
1108 
1109 	/* handle bus recovery events */
1110 	if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) {
1111 		netdev_dbg(dev, "left bus off state\n");
1112 		work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE);
1113 	}
1114 
1115 	if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) {
1116 		netdev_dbg(dev, "left error passive state\n");
1117 		work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING);
1118 	}
1119 
1120 	if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) {
1121 		netdev_dbg(dev, "left error warning state\n");
1122 		work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR);
1123 	}
1124 
1125 	/* handle lec errors on the bus */
1126 	work_done += c_can_handle_bus_err(dev, curr & LEC_MASK);
1127 
1128 	/* Handle Tx/Rx events. We do this unconditionally */
1129 	work_done += c_can_do_rx_poll(dev, (quota - work_done));
1130 	c_can_do_tx(dev);
1131 
1132 end:
1133 	if (work_done < quota) {
1134 		napi_complete_done(napi, work_done);
1135 		/* enable all IRQs if we are not in bus off state */
1136 		if (priv->can.state != CAN_STATE_BUS_OFF)
1137 			c_can_irq_control(priv, true);
1138 	}
1139 
1140 	return work_done;
1141 }
1142 
c_can_isr(int irq,void * dev_id)1143 static irqreturn_t c_can_isr(int irq, void *dev_id)
1144 {
1145 	struct net_device *dev = (struct net_device *)dev_id;
1146 	struct c_can_priv *priv = netdev_priv(dev);
1147 	int reg_int;
1148 
1149 	reg_int = priv->read_reg(priv, C_CAN_INT_REG);
1150 	if (!reg_int)
1151 		return IRQ_NONE;
1152 
1153 	/* save for later use */
1154 	if (reg_int & INT_STS_PENDING)
1155 		atomic_set(&priv->sie_pending, 1);
1156 
1157 	/* disable all interrupts and schedule the NAPI */
1158 	c_can_irq_control(priv, false);
1159 	napi_schedule(&priv->napi);
1160 
1161 	return IRQ_HANDLED;
1162 }
1163 
c_can_open(struct net_device * dev)1164 static int c_can_open(struct net_device *dev)
1165 {
1166 	int err;
1167 	struct c_can_priv *priv = netdev_priv(dev);
1168 
1169 	c_can_pm_runtime_get_sync(priv);
1170 	c_can_reset_ram(priv, true);
1171 
1172 	/* open the can device */
1173 	err = open_candev(dev);
1174 	if (err) {
1175 		netdev_err(dev, "failed to open can device\n");
1176 		goto exit_open_fail;
1177 	}
1178 
1179 	/* register interrupt handler */
1180 	err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1181 			  dev);
1182 	if (err < 0) {
1183 		netdev_err(dev, "failed to request interrupt\n");
1184 		goto exit_irq_fail;
1185 	}
1186 
1187 	/* start the c_can controller */
1188 	err = c_can_start(dev);
1189 	if (err)
1190 		goto exit_start_fail;
1191 
1192 	can_led_event(dev, CAN_LED_EVENT_OPEN);
1193 
1194 	napi_enable(&priv->napi);
1195 	/* enable status change, error and module interrupts */
1196 	c_can_irq_control(priv, true);
1197 	netif_start_queue(dev);
1198 
1199 	return 0;
1200 
1201 exit_start_fail:
1202 	free_irq(dev->irq, dev);
1203 exit_irq_fail:
1204 	close_candev(dev);
1205 exit_open_fail:
1206 	c_can_reset_ram(priv, false);
1207 	c_can_pm_runtime_put_sync(priv);
1208 	return err;
1209 }
1210 
c_can_close(struct net_device * dev)1211 static int c_can_close(struct net_device *dev)
1212 {
1213 	struct c_can_priv *priv = netdev_priv(dev);
1214 
1215 	netif_stop_queue(dev);
1216 	napi_disable(&priv->napi);
1217 	c_can_stop(dev);
1218 	free_irq(dev->irq, dev);
1219 	close_candev(dev);
1220 
1221 	c_can_reset_ram(priv, false);
1222 	c_can_pm_runtime_put_sync(priv);
1223 
1224 	can_led_event(dev, CAN_LED_EVENT_STOP);
1225 
1226 	return 0;
1227 }
1228 
alloc_c_can_dev(int msg_obj_num)1229 struct net_device *alloc_c_can_dev(int msg_obj_num)
1230 {
1231 	struct net_device *dev;
1232 	struct c_can_priv *priv;
1233 	int msg_obj_tx_num = msg_obj_num / 2;
1234 
1235 	dev = alloc_candev(struct_size(priv, dlc, msg_obj_tx_num),
1236 			   msg_obj_tx_num);
1237 	if (!dev)
1238 		return NULL;
1239 
1240 	priv = netdev_priv(dev);
1241 	priv->msg_obj_num = msg_obj_num;
1242 	priv->msg_obj_rx_num = msg_obj_num - msg_obj_tx_num;
1243 	priv->msg_obj_rx_first = 1;
1244 	priv->msg_obj_rx_last =
1245 		priv->msg_obj_rx_first + priv->msg_obj_rx_num - 1;
1246 	priv->msg_obj_rx_mask = GENMASK(priv->msg_obj_rx_num - 1, 0);
1247 
1248 	priv->msg_obj_tx_num = msg_obj_tx_num;
1249 	priv->msg_obj_tx_first = priv->msg_obj_rx_last + 1;
1250 	priv->msg_obj_tx_last =
1251 		priv->msg_obj_tx_first + priv->msg_obj_tx_num - 1;
1252 
1253 	priv->tx.head = 0;
1254 	priv->tx.tail = 0;
1255 	priv->tx.obj_num = msg_obj_tx_num;
1256 
1257 	netif_napi_add(dev, &priv->napi, c_can_poll, priv->msg_obj_rx_num);
1258 
1259 	priv->dev = dev;
1260 	priv->can.bittiming_const = &c_can_bittiming_const;
1261 	priv->can.do_set_mode = c_can_set_mode;
1262 	priv->can.do_get_berr_counter = c_can_get_berr_counter;
1263 	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1264 					CAN_CTRLMODE_LISTENONLY |
1265 					CAN_CTRLMODE_BERR_REPORTING;
1266 
1267 	return dev;
1268 }
1269 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1270 
1271 #ifdef CONFIG_PM
c_can_power_down(struct net_device * dev)1272 int c_can_power_down(struct net_device *dev)
1273 {
1274 	u32 val;
1275 	unsigned long time_out;
1276 	struct c_can_priv *priv = netdev_priv(dev);
1277 
1278 	if (!(dev->flags & IFF_UP))
1279 		return 0;
1280 
1281 	WARN_ON(priv->type != BOSCH_D_CAN);
1282 
1283 	/* set PDR value so the device goes to power down mode */
1284 	val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1285 	val |= CONTROL_EX_PDR;
1286 	priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1287 
1288 	/* Wait for the PDA bit to get set */
1289 	time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1290 	while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1291 	       time_after(time_out, jiffies))
1292 		cpu_relax();
1293 
1294 	if (time_after(jiffies, time_out))
1295 		return -ETIMEDOUT;
1296 
1297 	c_can_stop(dev);
1298 
1299 	c_can_reset_ram(priv, false);
1300 	c_can_pm_runtime_put_sync(priv);
1301 
1302 	return 0;
1303 }
1304 EXPORT_SYMBOL_GPL(c_can_power_down);
1305 
c_can_power_up(struct net_device * dev)1306 int c_can_power_up(struct net_device *dev)
1307 {
1308 	u32 val;
1309 	unsigned long time_out;
1310 	struct c_can_priv *priv = netdev_priv(dev);
1311 	int ret;
1312 
1313 	if (!(dev->flags & IFF_UP))
1314 		return 0;
1315 
1316 	WARN_ON(priv->type != BOSCH_D_CAN);
1317 
1318 	c_can_pm_runtime_get_sync(priv);
1319 	c_can_reset_ram(priv, true);
1320 
1321 	/* Clear PDR and INIT bits */
1322 	val = priv->read_reg(priv, C_CAN_CTRL_EX_REG);
1323 	val &= ~CONTROL_EX_PDR;
1324 	priv->write_reg(priv, C_CAN_CTRL_EX_REG, val);
1325 	val = priv->read_reg(priv, C_CAN_CTRL_REG);
1326 	val &= ~CONTROL_INIT;
1327 	priv->write_reg(priv, C_CAN_CTRL_REG, val);
1328 
1329 	/* Wait for the PDA bit to get clear */
1330 	time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS);
1331 	while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) &&
1332 	       time_after(time_out, jiffies))
1333 		cpu_relax();
1334 
1335 	if (time_after(jiffies, time_out)) {
1336 		ret = -ETIMEDOUT;
1337 		goto err_out;
1338 	}
1339 
1340 	ret = c_can_start(dev);
1341 	if (ret)
1342 		goto err_out;
1343 
1344 	c_can_irq_control(priv, true);
1345 
1346 	return 0;
1347 
1348 err_out:
1349 	c_can_reset_ram(priv, false);
1350 	c_can_pm_runtime_put_sync(priv);
1351 
1352 	return ret;
1353 }
1354 EXPORT_SYMBOL_GPL(c_can_power_up);
1355 #endif
1356 
free_c_can_dev(struct net_device * dev)1357 void free_c_can_dev(struct net_device *dev)
1358 {
1359 	struct c_can_priv *priv = netdev_priv(dev);
1360 
1361 	netif_napi_del(&priv->napi);
1362 	free_candev(dev);
1363 }
1364 EXPORT_SYMBOL_GPL(free_c_can_dev);
1365 
1366 static const struct net_device_ops c_can_netdev_ops = {
1367 	.ndo_open = c_can_open,
1368 	.ndo_stop = c_can_close,
1369 	.ndo_start_xmit = c_can_start_xmit,
1370 	.ndo_change_mtu = can_change_mtu,
1371 };
1372 
register_c_can_dev(struct net_device * dev)1373 int register_c_can_dev(struct net_device *dev)
1374 {
1375 	int err;
1376 
1377 	/* Deactivate pins to prevent DRA7 DCAN IP from being
1378 	 * stuck in transition when module is disabled.
1379 	 * Pins are activated in c_can_start() and deactivated
1380 	 * in c_can_stop()
1381 	 */
1382 	pinctrl_pm_select_sleep_state(dev->dev.parent);
1383 
1384 	dev->flags |= IFF_ECHO;	/* we support local echo */
1385 	dev->netdev_ops = &c_can_netdev_ops;
1386 	c_can_set_ethtool_ops(dev);
1387 
1388 	err = register_candev(dev);
1389 	if (!err)
1390 		devm_can_led_init(dev);
1391 	return err;
1392 }
1393 EXPORT_SYMBOL_GPL(register_c_can_dev);
1394 
unregister_c_can_dev(struct net_device * dev)1395 void unregister_c_can_dev(struct net_device *dev)
1396 {
1397 	unregister_candev(dev);
1398 }
1399 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1400 
1401 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1402 MODULE_LICENSE("GPL v2");
1403 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");
1404