1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * lpc_ich.c - LPC interface for Intel ICH
4 *
5 * LPC bridge function of the Intel ICH contains many other
6 * functional units, such as Interrupt controllers, Timers,
7 * Power Management, System Management, GPIO, RTC, and LPC
8 * Configuration Registers.
9 *
10 * This driver is derived from lpc_sch.
11
12 * Copyright (c) 2011 Extreme Engineering Solution, Inc.
13 * Author: Aaron Sierra <asierra@xes-inc.com>
14 *
15 * This driver supports the following I/O Controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 322896-001, 322897-001: NM10
30 * document number 313056-003, 313057-017: 82801H (ICH8)
31 * document number 316972-004, 316973-012: 82801I (ICH9)
32 * document number 319973-002, 319974-002: 82801J (ICH10)
33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
34 * document number 320066-003, 320257-008: EP80597 (IICH)
35 * document number 324645-001, 324646-001: Cougar Point (CPT)
36 */
37
38 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
39
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/errno.h>
43 #include <linux/acpi.h>
44 #include <linux/pci.h>
45 #include <linux/mfd/core.h>
46 #include <linux/mfd/lpc_ich.h>
47 #include <linux/platform_data/itco_wdt.h>
48
49 #define ACPIBASE 0x40
50 #define ACPIBASE_GPE_OFF 0x28
51 #define ACPIBASE_GPE_END 0x2f
52 #define ACPIBASE_SMI_OFF 0x30
53 #define ACPIBASE_SMI_END 0x33
54 #define ACPIBASE_PMC_OFF 0x08
55 #define ACPIBASE_PMC_END 0x0c
56 #define ACPIBASE_TCO_OFF 0x60
57 #define ACPIBASE_TCO_END 0x7f
58 #define ACPICTRL_PMCBASE 0x44
59
60 #define ACPIBASE_GCS_OFF 0x3410
61 #define ACPIBASE_GCS_END 0x3414
62
63 #define SPIBASE_BYT 0x54
64 #define SPIBASE_BYT_SZ 512
65 #define SPIBASE_BYT_EN BIT(1)
66
67 #define SPIBASE_LPT 0x3800
68 #define SPIBASE_LPT_SZ 512
69 #define BCR 0xdc
70 #define BCR_WPD BIT(0)
71
72 #define SPIBASE_APL_SZ 4096
73
74 #define GPIOBASE_ICH0 0x58
75 #define GPIOCTRL_ICH0 0x5C
76 #define GPIOBASE_ICH6 0x48
77 #define GPIOCTRL_ICH6 0x4C
78
79 #define RCBABASE 0xf0
80
81 #define wdt_io_res(i) wdt_res(0, i)
82 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i)
83 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)])
84
85 struct lpc_ich_priv {
86 int chipset;
87
88 int abase; /* ACPI base */
89 int actrl_pbase; /* ACPI control or PMC base */
90 int gbase; /* GPIO base */
91 int gctrl; /* GPIO control */
92
93 int abase_save; /* Cached ACPI base value */
94 int actrl_pbase_save; /* Cached ACPI control or PMC base value */
95 int gctrl_save; /* Cached GPIO control value */
96 };
97
98 static struct resource wdt_ich_res[] = {
99 /* ACPI - TCO */
100 {
101 .flags = IORESOURCE_IO,
102 },
103 /* ACPI - SMI */
104 {
105 .flags = IORESOURCE_IO,
106 },
107 /* GCS or PMC */
108 {
109 .flags = IORESOURCE_MEM,
110 },
111 };
112
113 static struct resource gpio_ich_res[] = {
114 /* GPIO */
115 {
116 .flags = IORESOURCE_IO,
117 },
118 /* ACPI - GPE0 */
119 {
120 .flags = IORESOURCE_IO,
121 },
122 };
123
124 static struct resource intel_spi_res[] = {
125 {
126 .flags = IORESOURCE_MEM,
127 }
128 };
129
130 static struct mfd_cell lpc_ich_wdt_cell = {
131 .name = "iTCO_wdt",
132 .num_resources = ARRAY_SIZE(wdt_ich_res),
133 .resources = wdt_ich_res,
134 .ignore_resource_conflicts = true,
135 };
136
137 static struct mfd_cell lpc_ich_gpio_cell = {
138 .name = "gpio_ich",
139 .num_resources = ARRAY_SIZE(gpio_ich_res),
140 .resources = gpio_ich_res,
141 .ignore_resource_conflicts = true,
142 };
143
144
145 static struct mfd_cell lpc_ich_spi_cell = {
146 .name = "intel-spi",
147 .num_resources = ARRAY_SIZE(intel_spi_res),
148 .resources = intel_spi_res,
149 .ignore_resource_conflicts = true,
150 };
151
152 /* chipset related info */
153 enum lpc_chipsets {
154 LPC_ICH = 0, /* ICH */
155 LPC_ICH0, /* ICH0 */
156 LPC_ICH2, /* ICH2 */
157 LPC_ICH2M, /* ICH2-M */
158 LPC_ICH3, /* ICH3-S */
159 LPC_ICH3M, /* ICH3-M */
160 LPC_ICH4, /* ICH4 */
161 LPC_ICH4M, /* ICH4-M */
162 LPC_CICH, /* C-ICH */
163 LPC_ICH5, /* ICH5 & ICH5R */
164 LPC_6300ESB, /* 6300ESB */
165 LPC_ICH6, /* ICH6 & ICH6R */
166 LPC_ICH6M, /* ICH6-M */
167 LPC_ICH6W, /* ICH6W & ICH6RW */
168 LPC_631XESB, /* 631xESB/632xESB */
169 LPC_ICH7, /* ICH7 & ICH7R */
170 LPC_ICH7DH, /* ICH7DH */
171 LPC_ICH7M, /* ICH7-M & ICH7-U */
172 LPC_ICH7MDH, /* ICH7-M DH */
173 LPC_NM10, /* NM10 */
174 LPC_ICH8, /* ICH8 & ICH8R */
175 LPC_ICH8DH, /* ICH8DH */
176 LPC_ICH8DO, /* ICH8DO */
177 LPC_ICH8M, /* ICH8M */
178 LPC_ICH8ME, /* ICH8M-E */
179 LPC_ICH9, /* ICH9 */
180 LPC_ICH9R, /* ICH9R */
181 LPC_ICH9DH, /* ICH9DH */
182 LPC_ICH9DO, /* ICH9DO */
183 LPC_ICH9M, /* ICH9M */
184 LPC_ICH9ME, /* ICH9M-E */
185 LPC_ICH10, /* ICH10 */
186 LPC_ICH10R, /* ICH10R */
187 LPC_ICH10D, /* ICH10D */
188 LPC_ICH10DO, /* ICH10DO */
189 LPC_PCH, /* PCH Desktop Full Featured */
190 LPC_PCHM, /* PCH Mobile Full Featured */
191 LPC_P55, /* P55 */
192 LPC_PM55, /* PM55 */
193 LPC_H55, /* H55 */
194 LPC_QM57, /* QM57 */
195 LPC_H57, /* H57 */
196 LPC_HM55, /* HM55 */
197 LPC_Q57, /* Q57 */
198 LPC_HM57, /* HM57 */
199 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */
200 LPC_QS57, /* QS57 */
201 LPC_3400, /* 3400 */
202 LPC_3420, /* 3420 */
203 LPC_3450, /* 3450 */
204 LPC_EP80579, /* EP80579 */
205 LPC_CPT, /* Cougar Point */
206 LPC_CPTD, /* Cougar Point Desktop */
207 LPC_CPTM, /* Cougar Point Mobile */
208 LPC_PBG, /* Patsburg */
209 LPC_DH89XXCC, /* DH89xxCC */
210 LPC_PPT, /* Panther Point */
211 LPC_LPT, /* Lynx Point */
212 LPC_LPT_LP, /* Lynx Point-LP */
213 LPC_WBG, /* Wellsburg */
214 LPC_AVN, /* Avoton SoC */
215 LPC_BAYTRAIL, /* Bay Trail SoC */
216 LPC_COLETO, /* Coleto Creek */
217 LPC_WPT_LP, /* Wildcat Point-LP */
218 LPC_BRASWELL, /* Braswell SoC */
219 LPC_LEWISBURG, /* Lewisburg */
220 LPC_9S, /* 9 Series */
221 LPC_APL, /* Apollo Lake SoC */
222 LPC_GLK, /* Gemini Lake SoC */
223 LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/
224 };
225
226 static struct lpc_ich_info lpc_chipset_info[] = {
227 [LPC_ICH] = {
228 .name = "ICH",
229 .iTCO_version = 1,
230 },
231 [LPC_ICH0] = {
232 .name = "ICH0",
233 .iTCO_version = 1,
234 },
235 [LPC_ICH2] = {
236 .name = "ICH2",
237 .iTCO_version = 1,
238 },
239 [LPC_ICH2M] = {
240 .name = "ICH2-M",
241 .iTCO_version = 1,
242 },
243 [LPC_ICH3] = {
244 .name = "ICH3-S",
245 .iTCO_version = 1,
246 },
247 [LPC_ICH3M] = {
248 .name = "ICH3-M",
249 .iTCO_version = 1,
250 },
251 [LPC_ICH4] = {
252 .name = "ICH4",
253 .iTCO_version = 1,
254 },
255 [LPC_ICH4M] = {
256 .name = "ICH4-M",
257 .iTCO_version = 1,
258 },
259 [LPC_CICH] = {
260 .name = "C-ICH",
261 .iTCO_version = 1,
262 },
263 [LPC_ICH5] = {
264 .name = "ICH5 or ICH5R",
265 .iTCO_version = 1,
266 },
267 [LPC_6300ESB] = {
268 .name = "6300ESB",
269 .iTCO_version = 1,
270 },
271 [LPC_ICH6] = {
272 .name = "ICH6 or ICH6R",
273 .iTCO_version = 2,
274 .gpio_version = ICH_V6_GPIO,
275 },
276 [LPC_ICH6M] = {
277 .name = "ICH6-M",
278 .iTCO_version = 2,
279 .gpio_version = ICH_V6_GPIO,
280 },
281 [LPC_ICH6W] = {
282 .name = "ICH6W or ICH6RW",
283 .iTCO_version = 2,
284 .gpio_version = ICH_V6_GPIO,
285 },
286 [LPC_631XESB] = {
287 .name = "631xESB/632xESB",
288 .iTCO_version = 2,
289 .gpio_version = ICH_V6_GPIO,
290 },
291 [LPC_ICH7] = {
292 .name = "ICH7 or ICH7R",
293 .iTCO_version = 2,
294 .gpio_version = ICH_V7_GPIO,
295 },
296 [LPC_ICH7DH] = {
297 .name = "ICH7DH",
298 .iTCO_version = 2,
299 .gpio_version = ICH_V7_GPIO,
300 },
301 [LPC_ICH7M] = {
302 .name = "ICH7-M or ICH7-U",
303 .iTCO_version = 2,
304 .gpio_version = ICH_V7_GPIO,
305 },
306 [LPC_ICH7MDH] = {
307 .name = "ICH7-M DH",
308 .iTCO_version = 2,
309 .gpio_version = ICH_V7_GPIO,
310 },
311 [LPC_NM10] = {
312 .name = "NM10",
313 .iTCO_version = 2,
314 .gpio_version = ICH_V7_GPIO,
315 },
316 [LPC_ICH8] = {
317 .name = "ICH8 or ICH8R",
318 .iTCO_version = 2,
319 .gpio_version = ICH_V7_GPIO,
320 },
321 [LPC_ICH8DH] = {
322 .name = "ICH8DH",
323 .iTCO_version = 2,
324 .gpio_version = ICH_V7_GPIO,
325 },
326 [LPC_ICH8DO] = {
327 .name = "ICH8DO",
328 .iTCO_version = 2,
329 .gpio_version = ICH_V7_GPIO,
330 },
331 [LPC_ICH8M] = {
332 .name = "ICH8M",
333 .iTCO_version = 2,
334 .gpio_version = ICH_V7_GPIO,
335 },
336 [LPC_ICH8ME] = {
337 .name = "ICH8M-E",
338 .iTCO_version = 2,
339 .gpio_version = ICH_V7_GPIO,
340 },
341 [LPC_ICH9] = {
342 .name = "ICH9",
343 .iTCO_version = 2,
344 .gpio_version = ICH_V9_GPIO,
345 },
346 [LPC_ICH9R] = {
347 .name = "ICH9R",
348 .iTCO_version = 2,
349 .gpio_version = ICH_V9_GPIO,
350 },
351 [LPC_ICH9DH] = {
352 .name = "ICH9DH",
353 .iTCO_version = 2,
354 .gpio_version = ICH_V9_GPIO,
355 },
356 [LPC_ICH9DO] = {
357 .name = "ICH9DO",
358 .iTCO_version = 2,
359 .gpio_version = ICH_V9_GPIO,
360 },
361 [LPC_ICH9M] = {
362 .name = "ICH9M",
363 .iTCO_version = 2,
364 .gpio_version = ICH_V9_GPIO,
365 },
366 [LPC_ICH9ME] = {
367 .name = "ICH9M-E",
368 .iTCO_version = 2,
369 .gpio_version = ICH_V9_GPIO,
370 },
371 [LPC_ICH10] = {
372 .name = "ICH10",
373 .iTCO_version = 2,
374 .gpio_version = ICH_V10CONS_GPIO,
375 },
376 [LPC_ICH10R] = {
377 .name = "ICH10R",
378 .iTCO_version = 2,
379 .gpio_version = ICH_V10CONS_GPIO,
380 },
381 [LPC_ICH10D] = {
382 .name = "ICH10D",
383 .iTCO_version = 2,
384 .gpio_version = ICH_V10CORP_GPIO,
385 },
386 [LPC_ICH10DO] = {
387 .name = "ICH10DO",
388 .iTCO_version = 2,
389 .gpio_version = ICH_V10CORP_GPIO,
390 },
391 [LPC_PCH] = {
392 .name = "PCH Desktop Full Featured",
393 .iTCO_version = 2,
394 .gpio_version = ICH_V5_GPIO,
395 },
396 [LPC_PCHM] = {
397 .name = "PCH Mobile Full Featured",
398 .iTCO_version = 2,
399 .gpio_version = ICH_V5_GPIO,
400 },
401 [LPC_P55] = {
402 .name = "P55",
403 .iTCO_version = 2,
404 .gpio_version = ICH_V5_GPIO,
405 },
406 [LPC_PM55] = {
407 .name = "PM55",
408 .iTCO_version = 2,
409 .gpio_version = ICH_V5_GPIO,
410 },
411 [LPC_H55] = {
412 .name = "H55",
413 .iTCO_version = 2,
414 .gpio_version = ICH_V5_GPIO,
415 },
416 [LPC_QM57] = {
417 .name = "QM57",
418 .iTCO_version = 2,
419 .gpio_version = ICH_V5_GPIO,
420 },
421 [LPC_H57] = {
422 .name = "H57",
423 .iTCO_version = 2,
424 .gpio_version = ICH_V5_GPIO,
425 },
426 [LPC_HM55] = {
427 .name = "HM55",
428 .iTCO_version = 2,
429 .gpio_version = ICH_V5_GPIO,
430 },
431 [LPC_Q57] = {
432 .name = "Q57",
433 .iTCO_version = 2,
434 .gpio_version = ICH_V5_GPIO,
435 },
436 [LPC_HM57] = {
437 .name = "HM57",
438 .iTCO_version = 2,
439 .gpio_version = ICH_V5_GPIO,
440 },
441 [LPC_PCHMSFF] = {
442 .name = "PCH Mobile SFF Full Featured",
443 .iTCO_version = 2,
444 .gpio_version = ICH_V5_GPIO,
445 },
446 [LPC_QS57] = {
447 .name = "QS57",
448 .iTCO_version = 2,
449 .gpio_version = ICH_V5_GPIO,
450 },
451 [LPC_3400] = {
452 .name = "3400",
453 .iTCO_version = 2,
454 .gpio_version = ICH_V5_GPIO,
455 },
456 [LPC_3420] = {
457 .name = "3420",
458 .iTCO_version = 2,
459 .gpio_version = ICH_V5_GPIO,
460 },
461 [LPC_3450] = {
462 .name = "3450",
463 .iTCO_version = 2,
464 .gpio_version = ICH_V5_GPIO,
465 },
466 [LPC_EP80579] = {
467 .name = "EP80579",
468 .iTCO_version = 2,
469 },
470 [LPC_CPT] = {
471 .name = "Cougar Point",
472 .iTCO_version = 2,
473 .gpio_version = ICH_V5_GPIO,
474 },
475 [LPC_CPTD] = {
476 .name = "Cougar Point Desktop",
477 .iTCO_version = 2,
478 .gpio_version = ICH_V5_GPIO,
479 },
480 [LPC_CPTM] = {
481 .name = "Cougar Point Mobile",
482 .iTCO_version = 2,
483 .gpio_version = ICH_V5_GPIO,
484 },
485 [LPC_PBG] = {
486 .name = "Patsburg",
487 .iTCO_version = 2,
488 },
489 [LPC_DH89XXCC] = {
490 .name = "DH89xxCC",
491 .iTCO_version = 2,
492 .gpio_version = ICH_V5_GPIO,
493 },
494 [LPC_PPT] = {
495 .name = "Panther Point",
496 .iTCO_version = 2,
497 .gpio_version = ICH_V5_GPIO,
498 },
499 [LPC_LPT] = {
500 .name = "Lynx Point",
501 .iTCO_version = 2,
502 .gpio_version = ICH_V5_GPIO,
503 .spi_type = INTEL_SPI_LPT,
504 },
505 [LPC_LPT_LP] = {
506 .name = "Lynx Point_LP",
507 .iTCO_version = 2,
508 .spi_type = INTEL_SPI_LPT,
509 },
510 [LPC_WBG] = {
511 .name = "Wellsburg",
512 .iTCO_version = 2,
513 },
514 [LPC_AVN] = {
515 .name = "Avoton SoC",
516 .iTCO_version = 3,
517 .gpio_version = AVOTON_GPIO,
518 .spi_type = INTEL_SPI_BYT,
519 },
520 [LPC_BAYTRAIL] = {
521 .name = "Bay Trail SoC",
522 .iTCO_version = 3,
523 .spi_type = INTEL_SPI_BYT,
524 },
525 [LPC_COLETO] = {
526 .name = "Coleto Creek",
527 .iTCO_version = 2,
528 },
529 [LPC_WPT_LP] = {
530 .name = "Wildcat Point_LP",
531 .iTCO_version = 2,
532 .spi_type = INTEL_SPI_LPT,
533 },
534 [LPC_BRASWELL] = {
535 .name = "Braswell SoC",
536 .iTCO_version = 3,
537 .spi_type = INTEL_SPI_BYT,
538 },
539 [LPC_LEWISBURG] = {
540 .name = "Lewisburg",
541 .iTCO_version = 2,
542 },
543 [LPC_9S] = {
544 .name = "9 Series",
545 .iTCO_version = 2,
546 .gpio_version = ICH_V5_GPIO,
547 },
548 [LPC_APL] = {
549 .name = "Apollo Lake SoC",
550 .iTCO_version = 5,
551 .spi_type = INTEL_SPI_BXT,
552 },
553 [LPC_GLK] = {
554 .name = "Gemini Lake SoC",
555 .spi_type = INTEL_SPI_BXT,
556 },
557 [LPC_COUGARMOUNTAIN] = {
558 .name = "Cougar Mountain SoC",
559 .iTCO_version = 3,
560 },
561 };
562
563 /*
564 * This data only exists for exporting the supported PCI ids
565 * via MODULE_DEVICE_TABLE. We do not actually register a
566 * pci_driver, because the I/O Controller Hub has also other
567 * functions that probably will be registered by other drivers.
568 */
569 static const struct pci_device_id lpc_ich_ids[] = {
570 { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL},
571 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT},
572 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD},
573 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM},
574 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT},
575 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT},
576 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT},
577 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT},
578 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT},
579 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT},
580 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT},
581 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT},
582 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT},
583 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT},
584 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT},
585 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT},
586 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT},
587 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT},
588 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT},
589 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT},
590 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT},
591 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT},
592 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT},
593 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT},
594 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT},
595 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT},
596 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT},
597 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT},
598 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT},
599 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT},
600 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT},
601 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT},
602 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG},
603 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG},
604 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT},
605 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT},
606 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT},
607 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT},
608 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT},
609 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT},
610 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT},
611 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT},
612 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT},
613 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT},
614 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT},
615 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT},
616 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT},
617 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT},
618 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT},
619 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT},
620 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT},
621 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT},
622 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT},
623 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT},
624 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT},
625 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT},
626 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT},
627 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT},
628 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT},
629 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT},
630 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT},
631 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT},
632 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT},
633 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT},
634 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT},
635 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT},
636 { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN},
637 { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN},
638 { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN},
639 { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN},
640 { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL},
641 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC},
642 { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO},
643 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH},
644 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0},
645 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2},
646 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M},
647 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH},
648 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3},
649 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M},
650 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4},
651 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M},
652 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5},
653 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB},
654 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6},
655 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M},
656 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W},
657 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB},
658 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB},
659 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB},
660 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB},
661 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB},
662 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB},
663 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB},
664 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB},
665 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB},
666 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB},
667 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB},
668 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB},
669 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB},
670 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB},
671 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB},
672 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB},
673 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH},
674 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7},
675 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M},
676 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10},
677 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH},
678 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8},
679 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME},
680 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH},
681 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO},
682 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M},
683 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH},
684 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO},
685 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R},
686 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME},
687 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9},
688 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M},
689 { PCI_VDEVICE(INTEL, 0x3197), LPC_GLK},
690 { PCI_VDEVICE(INTEL, 0x2b9c), LPC_COUGARMOUNTAIN},
691 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO},
692 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R},
693 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10},
694 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D},
695 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH},
696 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM},
697 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55},
698 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55},
699 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55},
700 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57},
701 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57},
702 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55},
703 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57},
704 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57},
705 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF},
706 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57},
707 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400},
708 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420},
709 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450},
710 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579},
711 { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL},
712 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT},
713 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT},
714 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT},
715 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT},
716 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT},
717 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT},
718 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT},
719 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT},
720 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT},
721 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT},
722 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT},
723 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT},
724 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT},
725 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT},
726 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT},
727 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT},
728 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT},
729 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT},
730 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT},
731 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT},
732 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT},
733 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT},
734 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT},
735 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT},
736 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT},
737 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT},
738 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT},
739 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT},
740 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT},
741 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT},
742 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT},
743 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT},
744 { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S},
745 { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S},
746 { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S},
747 { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S},
748 { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S},
749 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG},
750 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG},
751 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG},
752 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG},
753 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG},
754 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG},
755 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG},
756 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG},
757 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG},
758 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG},
759 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG},
760 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG},
761 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG},
762 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG},
763 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG},
764 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG},
765 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG},
766 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG},
767 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG},
768 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG},
769 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG},
770 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG},
771 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG},
772 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG},
773 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG},
774 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG},
775 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG},
776 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG},
777 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG},
778 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG},
779 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG},
780 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG},
781 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP},
782 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP},
783 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP},
784 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP},
785 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP},
786 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP},
787 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP},
788 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP},
789 { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP},
790 { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP},
791 { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP},
792 { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP},
793 { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP},
794 { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP},
795 { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP},
796 { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG},
797 { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG},
798 { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG},
799 { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG},
800 { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG},
801 { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG},
802 { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG},
803 { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG},
804 { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG},
805 { 0, }, /* End of list */
806 };
807 MODULE_DEVICE_TABLE(pci, lpc_ich_ids);
808
lpc_ich_restore_config_space(struct pci_dev * dev)809 static void lpc_ich_restore_config_space(struct pci_dev *dev)
810 {
811 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
812
813 if (priv->abase_save >= 0) {
814 pci_write_config_byte(dev, priv->abase, priv->abase_save);
815 priv->abase_save = -1;
816 }
817
818 if (priv->actrl_pbase_save >= 0) {
819 pci_write_config_byte(dev, priv->actrl_pbase,
820 priv->actrl_pbase_save);
821 priv->actrl_pbase_save = -1;
822 }
823
824 if (priv->gctrl_save >= 0) {
825 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save);
826 priv->gctrl_save = -1;
827 }
828 }
829
lpc_ich_enable_acpi_space(struct pci_dev * dev)830 static void lpc_ich_enable_acpi_space(struct pci_dev *dev)
831 {
832 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
833 u8 reg_save;
834
835 switch (lpc_chipset_info[priv->chipset].iTCO_version) {
836 case 3:
837 /*
838 * Some chipsets (eg Avoton) enable the ACPI space in the
839 * ACPI BASE register.
840 */
841 pci_read_config_byte(dev, priv->abase, ®_save);
842 pci_write_config_byte(dev, priv->abase, reg_save | 0x2);
843 priv->abase_save = reg_save;
844 break;
845 default:
846 /*
847 * Most chipsets enable the ACPI space in the ACPI control
848 * register.
849 */
850 pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
851 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80);
852 priv->actrl_pbase_save = reg_save;
853 break;
854 }
855 }
856
lpc_ich_enable_gpio_space(struct pci_dev * dev)857 static void lpc_ich_enable_gpio_space(struct pci_dev *dev)
858 {
859 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
860 u8 reg_save;
861
862 pci_read_config_byte(dev, priv->gctrl, ®_save);
863 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10);
864 priv->gctrl_save = reg_save;
865 }
866
lpc_ich_enable_pmc_space(struct pci_dev * dev)867 static void lpc_ich_enable_pmc_space(struct pci_dev *dev)
868 {
869 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
870 u8 reg_save;
871
872 pci_read_config_byte(dev, priv->actrl_pbase, ®_save);
873 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2);
874
875 priv->actrl_pbase_save = reg_save;
876 }
877
lpc_ich_finalize_wdt_cell(struct pci_dev * dev)878 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev)
879 {
880 struct itco_wdt_platform_data *pdata;
881 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
882 struct lpc_ich_info *info;
883 struct mfd_cell *cell = &lpc_ich_wdt_cell;
884
885 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
886 if (!pdata)
887 return -ENOMEM;
888
889 info = &lpc_chipset_info[priv->chipset];
890
891 pdata->version = info->iTCO_version;
892 strlcpy(pdata->name, info->name, sizeof(pdata->name));
893
894 cell->platform_data = pdata;
895 cell->pdata_size = sizeof(*pdata);
896 return 0;
897 }
898
lpc_ich_finalize_gpio_cell(struct pci_dev * dev)899 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev)
900 {
901 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
902 struct mfd_cell *cell = &lpc_ich_gpio_cell;
903
904 cell->platform_data = &lpc_chipset_info[priv->chipset];
905 cell->pdata_size = sizeof(struct lpc_ich_info);
906 }
907
908 /*
909 * We don't check for resource conflict globally. There are 2 or 3 independent
910 * GPIO groups and it's enough to have access to one of these to instantiate
911 * the device.
912 */
lpc_ich_check_conflict_gpio(struct resource * res)913 static int lpc_ich_check_conflict_gpio(struct resource *res)
914 {
915 int ret;
916 u8 use_gpio = 0;
917
918 if (resource_size(res) >= 0x50 &&
919 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3"))
920 use_gpio |= 1 << 2;
921
922 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2"))
923 use_gpio |= 1 << 1;
924
925 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1");
926 if (!ret)
927 use_gpio |= 1 << 0;
928
929 return use_gpio ? use_gpio : ret;
930 }
931
lpc_ich_init_gpio(struct pci_dev * dev)932 static int lpc_ich_init_gpio(struct pci_dev *dev)
933 {
934 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
935 u32 base_addr_cfg;
936 u32 base_addr;
937 int ret;
938 bool acpi_conflict = false;
939 struct resource *res;
940
941 /* Setup power management base register */
942 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
943 base_addr = base_addr_cfg & 0x0000ff80;
944 if (!base_addr) {
945 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
946 lpc_ich_gpio_cell.num_resources--;
947 goto gpe0_done;
948 }
949
950 res = &gpio_ich_res[ICH_RES_GPE0];
951 res->start = base_addr + ACPIBASE_GPE_OFF;
952 res->end = base_addr + ACPIBASE_GPE_END;
953 ret = acpi_check_resource_conflict(res);
954 if (ret) {
955 /*
956 * This isn't fatal for the GPIO, but we have to make sure that
957 * the platform_device subsystem doesn't see this resource
958 * or it will register an invalid region.
959 */
960 lpc_ich_gpio_cell.num_resources--;
961 acpi_conflict = true;
962 } else {
963 lpc_ich_enable_acpi_space(dev);
964 }
965
966 gpe0_done:
967 /* Setup GPIO base register */
968 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg);
969 base_addr = base_addr_cfg & 0x0000ff80;
970 if (!base_addr) {
971 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n");
972 ret = -ENODEV;
973 goto gpio_done;
974 }
975
976 /* Older devices provide fewer GPIO and have a smaller resource size. */
977 res = &gpio_ich_res[ICH_RES_GPIO];
978 res->start = base_addr;
979 switch (lpc_chipset_info[priv->chipset].gpio_version) {
980 case ICH_V5_GPIO:
981 case ICH_V10CORP_GPIO:
982 res->end = res->start + 128 - 1;
983 break;
984 default:
985 res->end = res->start + 64 - 1;
986 break;
987 }
988
989 ret = lpc_ich_check_conflict_gpio(res);
990 if (ret < 0) {
991 /* this isn't necessarily fatal for the GPIO */
992 acpi_conflict = true;
993 goto gpio_done;
994 }
995 lpc_chipset_info[priv->chipset].use_gpio = ret;
996 lpc_ich_enable_gpio_space(dev);
997
998 lpc_ich_finalize_gpio_cell(dev);
999 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1000 &lpc_ich_gpio_cell, 1, NULL, 0, NULL);
1001
1002 gpio_done:
1003 if (acpi_conflict)
1004 pr_warn("Resource conflict(s) found affecting %s\n",
1005 lpc_ich_gpio_cell.name);
1006 return ret;
1007 }
1008
lpc_ich_init_wdt(struct pci_dev * dev)1009 static int lpc_ich_init_wdt(struct pci_dev *dev)
1010 {
1011 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1012 u32 base_addr_cfg;
1013 u32 base_addr;
1014 int ret;
1015 struct resource *res;
1016
1017 /* If we have ACPI based watchdog use that instead */
1018 if (acpi_has_watchdog())
1019 return -ENODEV;
1020
1021 /* Setup power management base register */
1022 pci_read_config_dword(dev, priv->abase, &base_addr_cfg);
1023 base_addr = base_addr_cfg & 0x0000ff80;
1024 if (!base_addr) {
1025 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n");
1026 ret = -ENODEV;
1027 goto wdt_done;
1028 }
1029
1030 res = wdt_io_res(ICH_RES_IO_TCO);
1031 res->start = base_addr + ACPIBASE_TCO_OFF;
1032 res->end = base_addr + ACPIBASE_TCO_END;
1033
1034 res = wdt_io_res(ICH_RES_IO_SMI);
1035 res->start = base_addr + ACPIBASE_SMI_OFF;
1036 res->end = base_addr + ACPIBASE_SMI_END;
1037
1038 lpc_ich_enable_acpi_space(dev);
1039
1040 /*
1041 * iTCO v2:
1042 * Get the Memory-Mapped GCS register. To get access to it
1043 * we have to read RCBA from PCI Config space 0xf0 and use
1044 * it as base. GCS = RCBA + ICH6_GCS(0x3410).
1045 *
1046 * iTCO v3:
1047 * Get the Power Management Configuration register. To get access
1048 * to it we have to read the PMC BASE from config space and address
1049 * the register at offset 0x8.
1050 */
1051 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) {
1052 /* Don't register iomem for TCO ver 1 */
1053 lpc_ich_wdt_cell.num_resources--;
1054 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) {
1055 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg);
1056 base_addr = base_addr_cfg & 0xffffc000;
1057 if (!(base_addr_cfg & 1)) {
1058 dev_notice(&dev->dev, "RCBA is disabled by "
1059 "hardware/BIOS, device disabled\n");
1060 ret = -ENODEV;
1061 goto wdt_done;
1062 }
1063 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1064 res->start = base_addr + ACPIBASE_GCS_OFF;
1065 res->end = base_addr + ACPIBASE_GCS_END;
1066 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) {
1067 lpc_ich_enable_pmc_space(dev);
1068 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg);
1069 base_addr = base_addr_cfg & 0xfffffe00;
1070
1071 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC);
1072 res->start = base_addr + ACPIBASE_PMC_OFF;
1073 res->end = base_addr + ACPIBASE_PMC_END;
1074 }
1075
1076 ret = lpc_ich_finalize_wdt_cell(dev);
1077 if (ret)
1078 goto wdt_done;
1079
1080 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
1081 &lpc_ich_wdt_cell, 1, NULL, 0, NULL);
1082
1083 wdt_done:
1084 return ret;
1085 }
1086
lpc_ich_init_spi(struct pci_dev * dev)1087 static int lpc_ich_init_spi(struct pci_dev *dev)
1088 {
1089 struct lpc_ich_priv *priv = pci_get_drvdata(dev);
1090 struct resource *res = &intel_spi_res[0];
1091 struct intel_spi_boardinfo *info;
1092 u32 spi_base, rcba, bcr;
1093
1094 info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL);
1095 if (!info)
1096 return -ENOMEM;
1097
1098 info->type = lpc_chipset_info[priv->chipset].spi_type;
1099
1100 switch (info->type) {
1101 case INTEL_SPI_BYT:
1102 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base);
1103 if (spi_base & SPIBASE_BYT_EN) {
1104 res->start = spi_base & ~(SPIBASE_BYT_SZ - 1);
1105 res->end = res->start + SPIBASE_BYT_SZ - 1;
1106 }
1107 break;
1108
1109 case INTEL_SPI_LPT:
1110 pci_read_config_dword(dev, RCBABASE, &rcba);
1111 if (rcba & 1) {
1112 spi_base = round_down(rcba, SPIBASE_LPT_SZ);
1113 res->start = spi_base + SPIBASE_LPT;
1114 res->end = res->start + SPIBASE_LPT_SZ - 1;
1115
1116 pci_read_config_dword(dev, BCR, &bcr);
1117 info->writeable = !!(bcr & BCR_WPD);
1118 }
1119 break;
1120
1121 case INTEL_SPI_BXT: {
1122 unsigned int p2sb = PCI_DEVFN(13, 0);
1123 unsigned int spi = PCI_DEVFN(13, 2);
1124 struct pci_bus *bus = dev->bus;
1125
1126 /*
1127 * The P2SB is hidden by BIOS and we need to unhide it in
1128 * order to read BAR of the SPI flash device. Once that is
1129 * done we hide it again.
1130 */
1131 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0);
1132 pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0,
1133 &spi_base);
1134 if (spi_base != ~0) {
1135 res->start = spi_base & 0xfffffff0;
1136 res->end = res->start + SPIBASE_APL_SZ - 1;
1137
1138 pci_bus_read_config_dword(bus, spi, BCR, &bcr);
1139 info->writeable = !!(bcr & BCR_WPD);
1140 }
1141
1142 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1);
1143 break;
1144 }
1145
1146 default:
1147 return -EINVAL;
1148 }
1149
1150 if (!res->start)
1151 return -ENODEV;
1152
1153 lpc_ich_spi_cell.platform_data = info;
1154 lpc_ich_spi_cell.pdata_size = sizeof(*info);
1155
1156 return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE,
1157 &lpc_ich_spi_cell, 1, NULL, 0, NULL);
1158 }
1159
lpc_ich_probe(struct pci_dev * dev,const struct pci_device_id * id)1160 static int lpc_ich_probe(struct pci_dev *dev,
1161 const struct pci_device_id *id)
1162 {
1163 struct lpc_ich_priv *priv;
1164 int ret;
1165 bool cell_added = false;
1166
1167 priv = devm_kzalloc(&dev->dev,
1168 sizeof(struct lpc_ich_priv), GFP_KERNEL);
1169 if (!priv)
1170 return -ENOMEM;
1171
1172 priv->chipset = id->driver_data;
1173
1174 priv->actrl_pbase_save = -1;
1175 priv->abase_save = -1;
1176
1177 priv->abase = ACPIBASE;
1178 priv->actrl_pbase = ACPICTRL_PMCBASE;
1179
1180 priv->gctrl_save = -1;
1181 if (priv->chipset <= LPC_ICH5) {
1182 priv->gbase = GPIOBASE_ICH0;
1183 priv->gctrl = GPIOCTRL_ICH0;
1184 } else {
1185 priv->gbase = GPIOBASE_ICH6;
1186 priv->gctrl = GPIOCTRL_ICH6;
1187 }
1188
1189 pci_set_drvdata(dev, priv);
1190
1191 if (lpc_chipset_info[priv->chipset].iTCO_version) {
1192 ret = lpc_ich_init_wdt(dev);
1193 if (!ret)
1194 cell_added = true;
1195 }
1196
1197 if (lpc_chipset_info[priv->chipset].gpio_version) {
1198 ret = lpc_ich_init_gpio(dev);
1199 if (!ret)
1200 cell_added = true;
1201 }
1202
1203 if (lpc_chipset_info[priv->chipset].spi_type) {
1204 ret = lpc_ich_init_spi(dev);
1205 if (!ret)
1206 cell_added = true;
1207 }
1208
1209 /*
1210 * We only care if at least one or none of the cells registered
1211 * successfully.
1212 */
1213 if (!cell_added) {
1214 dev_warn(&dev->dev, "No MFD cells added\n");
1215 lpc_ich_restore_config_space(dev);
1216 return -ENODEV;
1217 }
1218
1219 return 0;
1220 }
1221
lpc_ich_remove(struct pci_dev * dev)1222 static void lpc_ich_remove(struct pci_dev *dev)
1223 {
1224 mfd_remove_devices(&dev->dev);
1225 lpc_ich_restore_config_space(dev);
1226 }
1227
1228 static struct pci_driver lpc_ich_driver = {
1229 .name = "lpc_ich",
1230 .id_table = lpc_ich_ids,
1231 .probe = lpc_ich_probe,
1232 .remove = lpc_ich_remove,
1233 };
1234
1235 module_pci_driver(lpc_ich_driver);
1236
1237 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");
1238 MODULE_DESCRIPTION("LPC interface for Intel ICH");
1239 MODULE_LICENSE("GPL");
1240
