1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Rockchip ISP1 Driver - ISP Subdevice
4 *
5 * Copyright (C) 2019 Collabora, Ltd.
6 *
7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
9 */
10
11 #include <linux/iopoll.h>
12 #include <linux/phy/phy.h>
13 #include <linux/phy/phy-mipi-dphy.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/videodev2.h>
16 #include <linux/vmalloc.h>
17 #include <media/v4l2-event.h>
18
19 #include "rkisp1-common.h"
20
21 #define RKISP1_DEF_SINK_PAD_FMT MEDIA_BUS_FMT_SRGGB10_1X10
22 #define RKISP1_DEF_SRC_PAD_FMT MEDIA_BUS_FMT_YUYV8_2X8
23
24 #define RKISP1_ISP_DEV_NAME RKISP1_DRIVER_NAME "_isp"
25
26 /*
27 * NOTE: MIPI controller and input MUX are also configured in this file.
28 * This is because ISP Subdev describes not only ISP submodule (input size,
29 * format, output size, format), but also a virtual route device.
30 */
31
32 /*
33 * There are many variables named with format/frame in below code,
34 * please see here for their meaning.
35 * Cropping in the sink pad defines the image region from the sensor.
36 * Cropping in the source pad defines the region for the Image Stabilizer (IS)
37 *
38 * Cropping regions of ISP
39 *
40 * +---------------------------------------------------------+
41 * | Sensor image |
42 * | +---------------------------------------------------+ |
43 * | | CIF_ISP_ACQ (for black level) | |
44 * | | sink pad format | |
45 * | | +--------------------------------------------+ | |
46 * | | | CIF_ISP_OUT | | |
47 * | | | sink pad crop | | |
48 * | | | +---------------------------------+ | | |
49 * | | | | CIF_ISP_IS | | | |
50 * | | | | source pad crop and format | | | |
51 * | | | +---------------------------------+ | | |
52 * | | +--------------------------------------------+ | |
53 * | +---------------------------------------------------+ |
54 * +---------------------------------------------------------+
55 */
56
57 static const struct rkisp1_isp_mbus_info rkisp1_isp_formats[] = {
58 {
59 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
60 .pixel_enc = V4L2_PIXEL_ENC_YUV,
61 .direction = RKISP1_ISP_SD_SRC,
62 }, {
63 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
64 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
65 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
66 .bayer_pat = RKISP1_RAW_RGGB,
67 .bus_width = 10,
68 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
69 }, {
70 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
71 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
72 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
73 .bayer_pat = RKISP1_RAW_BGGR,
74 .bus_width = 10,
75 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
76 }, {
77 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
78 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
79 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
80 .bayer_pat = RKISP1_RAW_GBRG,
81 .bus_width = 10,
82 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
83 }, {
84 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
85 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
86 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10,
87 .bayer_pat = RKISP1_RAW_GRBG,
88 .bus_width = 10,
89 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
90 }, {
91 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
92 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
93 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
94 .bayer_pat = RKISP1_RAW_RGGB,
95 .bus_width = 12,
96 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
97 }, {
98 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
99 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
100 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
101 .bayer_pat = RKISP1_RAW_BGGR,
102 .bus_width = 12,
103 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
104 }, {
105 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
106 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
107 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
108 .bayer_pat = RKISP1_RAW_GBRG,
109 .bus_width = 12,
110 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
111 }, {
112 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
113 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
114 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12,
115 .bayer_pat = RKISP1_RAW_GRBG,
116 .bus_width = 12,
117 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
118 }, {
119 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
120 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
121 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
122 .bayer_pat = RKISP1_RAW_RGGB,
123 .bus_width = 8,
124 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
125 }, {
126 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
127 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
128 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
129 .bayer_pat = RKISP1_RAW_BGGR,
130 .bus_width = 8,
131 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
132 }, {
133 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
134 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
135 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
136 .bayer_pat = RKISP1_RAW_GBRG,
137 .bus_width = 8,
138 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
139 }, {
140 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
141 .pixel_enc = V4L2_PIXEL_ENC_BAYER,
142 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8,
143 .bayer_pat = RKISP1_RAW_GRBG,
144 .bus_width = 8,
145 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC,
146 }, {
147 .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16,
148 .pixel_enc = V4L2_PIXEL_ENC_YUV,
149 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
150 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCBYCR,
151 .bus_width = 16,
152 .direction = RKISP1_ISP_SD_SINK,
153 }, {
154 .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16,
155 .pixel_enc = V4L2_PIXEL_ENC_YUV,
156 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
157 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCRYCB,
158 .bus_width = 16,
159 .direction = RKISP1_ISP_SD_SINK,
160 }, {
161 .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16,
162 .pixel_enc = V4L2_PIXEL_ENC_YUV,
163 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
164 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CBYCRY,
165 .bus_width = 16,
166 .direction = RKISP1_ISP_SD_SINK,
167 }, {
168 .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16,
169 .pixel_enc = V4L2_PIXEL_ENC_YUV,
170 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b,
171 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CRYCBY,
172 .bus_width = 16,
173 .direction = RKISP1_ISP_SD_SINK,
174 },
175 };
176
177 /* ----------------------------------------------------------------------------
178 * Helpers
179 */
180
rkisp1_isp_mbus_info_get(u32 mbus_code)181 const struct rkisp1_isp_mbus_info *rkisp1_isp_mbus_info_get(u32 mbus_code)
182 {
183 unsigned int i;
184
185 for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) {
186 const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i];
187
188 if (fmt->mbus_code == mbus_code)
189 return fmt;
190 }
191
192 return NULL;
193 }
194
rkisp1_get_remote_sensor(struct v4l2_subdev * sd)195 static struct v4l2_subdev *rkisp1_get_remote_sensor(struct v4l2_subdev *sd)
196 {
197 struct media_pad *local, *remote;
198 struct media_entity *sensor_me;
199
200 local = &sd->entity.pads[RKISP1_ISP_PAD_SINK_VIDEO];
201 remote = media_entity_remote_pad(local);
202 if (!remote)
203 return NULL;
204
205 sensor_me = remote->entity;
206 return media_entity_to_v4l2_subdev(sensor_me);
207 }
208
209 static struct v4l2_mbus_framefmt *
rkisp1_isp_get_pad_fmt(struct rkisp1_isp * isp,struct v4l2_subdev_state * sd_state,unsigned int pad,u32 which)210 rkisp1_isp_get_pad_fmt(struct rkisp1_isp *isp,
211 struct v4l2_subdev_state *sd_state,
212 unsigned int pad, u32 which)
213 {
214 struct v4l2_subdev_state state = {
215 .pads = isp->pad_cfg
216 };
217 if (which == V4L2_SUBDEV_FORMAT_TRY)
218 return v4l2_subdev_get_try_format(&isp->sd, sd_state, pad);
219 else
220 return v4l2_subdev_get_try_format(&isp->sd, &state, pad);
221 }
222
223 static struct v4l2_rect *
rkisp1_isp_get_pad_crop(struct rkisp1_isp * isp,struct v4l2_subdev_state * sd_state,unsigned int pad,u32 which)224 rkisp1_isp_get_pad_crop(struct rkisp1_isp *isp,
225 struct v4l2_subdev_state *sd_state,
226 unsigned int pad, u32 which)
227 {
228 struct v4l2_subdev_state state = {
229 .pads = isp->pad_cfg
230 };
231 if (which == V4L2_SUBDEV_FORMAT_TRY)
232 return v4l2_subdev_get_try_crop(&isp->sd, sd_state, pad);
233 else
234 return v4l2_subdev_get_try_crop(&isp->sd, &state, pad);
235 }
236
237 /* ----------------------------------------------------------------------------
238 * Camera Interface registers configurations
239 */
240
241 /*
242 * Image Stabilization.
243 * This should only be called when configuring CIF
244 * or at the frame end interrupt
245 */
rkisp1_config_ism(struct rkisp1_device * rkisp1)246 static void rkisp1_config_ism(struct rkisp1_device *rkisp1)
247 {
248 struct v4l2_rect *src_crop =
249 rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL,
250 RKISP1_ISP_PAD_SOURCE_VIDEO,
251 V4L2_SUBDEV_FORMAT_ACTIVE);
252 u32 val;
253
254 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_RECENTER);
255 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DX);
256 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DY);
257 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_DISPLACE);
258 rkisp1_write(rkisp1, src_crop->left, RKISP1_CIF_ISP_IS_H_OFFS);
259 rkisp1_write(rkisp1, src_crop->top, RKISP1_CIF_ISP_IS_V_OFFS);
260 rkisp1_write(rkisp1, src_crop->width, RKISP1_CIF_ISP_IS_H_SIZE);
261 rkisp1_write(rkisp1, src_crop->height, RKISP1_CIF_ISP_IS_V_SIZE);
262
263 /* IS(Image Stabilization) is always on, working as output crop */
264 rkisp1_write(rkisp1, 1, RKISP1_CIF_ISP_IS_CTRL);
265 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
266 val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD;
267 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
268 }
269
270 /*
271 * configure ISP blocks with input format, size......
272 */
rkisp1_config_isp(struct rkisp1_device * rkisp1)273 static int rkisp1_config_isp(struct rkisp1_device *rkisp1)
274 {
275 u32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0;
276 const struct rkisp1_isp_mbus_info *src_fmt, *sink_fmt;
277 struct rkisp1_sensor_async *sensor;
278 struct v4l2_mbus_framefmt *sink_frm;
279 struct v4l2_rect *sink_crop;
280
281 sensor = rkisp1->active_sensor;
282 sink_fmt = rkisp1->isp.sink_fmt;
283 src_fmt = rkisp1->isp.src_fmt;
284 sink_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL,
285 RKISP1_ISP_PAD_SINK_VIDEO,
286 V4L2_SUBDEV_FORMAT_ACTIVE);
287 sink_crop = rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL,
288 RKISP1_ISP_PAD_SINK_VIDEO,
289 V4L2_SUBDEV_FORMAT_ACTIVE);
290
291 if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
292 acq_mult = 1;
293 if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
294 if (sensor->mbus_type == V4L2_MBUS_BT656)
295 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656;
296 else
297 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT;
298 } else {
299 rkisp1_write(rkisp1, RKISP1_CIF_ISP_DEMOSAIC_TH(0xc),
300 RKISP1_CIF_ISP_DEMOSAIC);
301
302 if (sensor->mbus_type == V4L2_MBUS_BT656)
303 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656;
304 else
305 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601;
306 }
307 } else if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_YUV) {
308 acq_mult = 2;
309 if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
310 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601;
311 } else {
312 if (sensor->mbus_type == V4L2_MBUS_BT656)
313 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU656;
314 else
315 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601;
316 }
317
318 irq_mask |= RKISP1_CIF_ISP_DATA_LOSS;
319 }
320
321 /* Set up input acquisition properties */
322 if (sensor->mbus_type == V4L2_MBUS_BT656 ||
323 sensor->mbus_type == V4L2_MBUS_PARALLEL) {
324 if (sensor->mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
325 signal = RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE;
326 }
327
328 if (sensor->mbus_type == V4L2_MBUS_PARALLEL) {
329 if (sensor->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
330 signal |= RKISP1_CIF_ISP_ACQ_PROP_VSYNC_LOW;
331
332 if (sensor->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
333 signal |= RKISP1_CIF_ISP_ACQ_PROP_HSYNC_LOW;
334 }
335
336 rkisp1_write(rkisp1, isp_ctrl, RKISP1_CIF_ISP_CTRL);
337 rkisp1_write(rkisp1, signal | sink_fmt->yuv_seq |
338 RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT(sink_fmt->bayer_pat) |
339 RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL,
340 RKISP1_CIF_ISP_ACQ_PROP);
341 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_NR_FRAMES);
342
343 /* Acquisition Size */
344 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_H_OFFS);
345 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_V_OFFS);
346 rkisp1_write(rkisp1,
347 acq_mult * sink_frm->width, RKISP1_CIF_ISP_ACQ_H_SIZE);
348 rkisp1_write(rkisp1, sink_frm->height, RKISP1_CIF_ISP_ACQ_V_SIZE);
349
350 /* ISP Out Area */
351 rkisp1_write(rkisp1, sink_crop->left, RKISP1_CIF_ISP_OUT_H_OFFS);
352 rkisp1_write(rkisp1, sink_crop->top, RKISP1_CIF_ISP_OUT_V_OFFS);
353 rkisp1_write(rkisp1, sink_crop->width, RKISP1_CIF_ISP_OUT_H_SIZE);
354 rkisp1_write(rkisp1, sink_crop->height, RKISP1_CIF_ISP_OUT_V_SIZE);
355
356 irq_mask |= RKISP1_CIF_ISP_FRAME | RKISP1_CIF_ISP_V_START |
357 RKISP1_CIF_ISP_PIC_SIZE_ERROR;
358 rkisp1_write(rkisp1, irq_mask, RKISP1_CIF_ISP_IMSC);
359
360 if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
361 rkisp1_params_disable(&rkisp1->params);
362 } else {
363 struct v4l2_mbus_framefmt *src_frm;
364
365 src_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL,
366 RKISP1_ISP_PAD_SINK_VIDEO,
367 V4L2_SUBDEV_FORMAT_ACTIVE);
368 rkisp1_params_configure(&rkisp1->params, sink_fmt->bayer_pat,
369 src_frm->quantization);
370 }
371
372 return 0;
373 }
374
rkisp1_config_dvp(struct rkisp1_device * rkisp1)375 static int rkisp1_config_dvp(struct rkisp1_device *rkisp1)
376 {
377 const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt;
378 u32 val, input_sel;
379
380 switch (sink_fmt->bus_width) {
381 case 8:
382 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO;
383 break;
384 case 10:
385 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO;
386 break;
387 case 12:
388 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B;
389 break;
390 default:
391 dev_err(rkisp1->dev, "Invalid bus width\n");
392 return -EINVAL;
393 }
394
395 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ACQ_PROP);
396 rkisp1_write(rkisp1, val | input_sel, RKISP1_CIF_ISP_ACQ_PROP);
397
398 return 0;
399 }
400
rkisp1_config_mipi(struct rkisp1_device * rkisp1)401 static int rkisp1_config_mipi(struct rkisp1_device *rkisp1)
402 {
403 const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt;
404 unsigned int lanes = rkisp1->active_sensor->lanes;
405 u32 mipi_ctrl;
406
407 if (lanes < 1 || lanes > 4)
408 return -EINVAL;
409
410 mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) |
411 RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) |
412 RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP |
413 RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA;
414
415 rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL);
416
417 /* Configure Data Type and Virtual Channel */
418 rkisp1_write(rkisp1,
419 RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) |
420 RKISP1_CIF_MIPI_DATA_SEL_VC(0),
421 RKISP1_CIF_MIPI_IMG_DATA_SEL);
422
423 /* Clear MIPI interrupts */
424 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR);
425 /*
426 * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for
427 * isp bus may be dead when switch isp.
428 */
429 rkisp1_write(rkisp1,
430 RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI |
431 RKISP1_CIF_MIPI_ERR_DPHY |
432 RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) |
433 RKISP1_CIF_MIPI_ADD_DATA_OVFLW,
434 RKISP1_CIF_MIPI_IMSC);
435
436 dev_dbg(rkisp1->dev, "\n MIPI_CTRL 0x%08x\n"
437 " MIPI_IMG_DATA_SEL 0x%08x\n"
438 " MIPI_STATUS 0x%08x\n"
439 " MIPI_IMSC 0x%08x\n",
440 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL),
441 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL),
442 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS),
443 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC));
444
445 return 0;
446 }
447
448 /* Configure MUX */
rkisp1_config_path(struct rkisp1_device * rkisp1)449 static int rkisp1_config_path(struct rkisp1_device *rkisp1)
450 {
451 struct rkisp1_sensor_async *sensor = rkisp1->active_sensor;
452 u32 dpcl = rkisp1_read(rkisp1, RKISP1_CIF_VI_DPCL);
453 int ret = 0;
454
455 if (sensor->mbus_type == V4L2_MBUS_BT656 ||
456 sensor->mbus_type == V4L2_MBUS_PARALLEL) {
457 ret = rkisp1_config_dvp(rkisp1);
458 dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_PARALLEL;
459 } else if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
460 ret = rkisp1_config_mipi(rkisp1);
461 dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_MIPI;
462 }
463
464 rkisp1_write(rkisp1, dpcl, RKISP1_CIF_VI_DPCL);
465
466 return ret;
467 }
468
469 /* Hardware configure Entry */
rkisp1_config_cif(struct rkisp1_device * rkisp1)470 static int rkisp1_config_cif(struct rkisp1_device *rkisp1)
471 {
472 u32 cif_id;
473 int ret;
474
475 cif_id = rkisp1_read(rkisp1, RKISP1_CIF_VI_ID);
476 dev_dbg(rkisp1->dev, "CIF_ID 0x%08x\n", cif_id);
477
478 ret = rkisp1_config_isp(rkisp1);
479 if (ret)
480 return ret;
481 ret = rkisp1_config_path(rkisp1);
482 if (ret)
483 return ret;
484 rkisp1_config_ism(rkisp1);
485
486 return 0;
487 }
488
rkisp1_isp_stop(struct rkisp1_device * rkisp1)489 static void rkisp1_isp_stop(struct rkisp1_device *rkisp1)
490 {
491 u32 val;
492
493 /*
494 * ISP(mi) stop in mi frame end -> Stop ISP(mipi) ->
495 * Stop ISP(isp) ->wait for ISP isp off
496 */
497 /* stop and clear MI, MIPI, and ISP interrupts */
498 rkisp1_write(rkisp1, 0, RKISP1_CIF_MIPI_IMSC);
499 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR);
500
501 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IMSC);
502 rkisp1_write(rkisp1, ~0, RKISP1_CIF_ISP_ICR);
503
504 rkisp1_write(rkisp1, 0, RKISP1_CIF_MI_IMSC);
505 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MI_ICR);
506 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
507 rkisp1_write(rkisp1, val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA),
508 RKISP1_CIF_MIPI_CTRL);
509 /* stop ISP */
510 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
511 val &= ~(RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE |
512 RKISP1_CIF_ISP_CTRL_ISP_ENABLE);
513 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
514
515 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
516 rkisp1_write(rkisp1, val | RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD,
517 RKISP1_CIF_ISP_CTRL);
518
519 readx_poll_timeout(readl, rkisp1->base_addr + RKISP1_CIF_ISP_RIS,
520 val, val & RKISP1_CIF_ISP_OFF, 20, 100);
521 rkisp1_write(rkisp1,
522 RKISP1_CIF_IRCL_MIPI_SW_RST | RKISP1_CIF_IRCL_ISP_SW_RST,
523 RKISP1_CIF_IRCL);
524 rkisp1_write(rkisp1, 0x0, RKISP1_CIF_IRCL);
525 }
526
rkisp1_config_clk(struct rkisp1_device * rkisp1)527 static void rkisp1_config_clk(struct rkisp1_device *rkisp1)
528 {
529 u32 val = RKISP1_CIF_ICCL_ISP_CLK | RKISP1_CIF_ICCL_CP_CLK |
530 RKISP1_CIF_ICCL_MRSZ_CLK | RKISP1_CIF_ICCL_SRSZ_CLK |
531 RKISP1_CIF_ICCL_JPEG_CLK | RKISP1_CIF_ICCL_MI_CLK |
532 RKISP1_CIF_ICCL_IE_CLK | RKISP1_CIF_ICCL_MIPI_CLK |
533 RKISP1_CIF_ICCL_DCROP_CLK;
534
535 rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL);
536 }
537
rkisp1_isp_start(struct rkisp1_device * rkisp1)538 static void rkisp1_isp_start(struct rkisp1_device *rkisp1)
539 {
540 struct rkisp1_sensor_async *sensor = rkisp1->active_sensor;
541 u32 val;
542
543 rkisp1_config_clk(rkisp1);
544
545 /* Activate MIPI */
546 if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) {
547 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
548 rkisp1_write(rkisp1, val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA,
549 RKISP1_CIF_MIPI_CTRL);
550 }
551 /* Activate ISP */
552 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL);
553 val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD |
554 RKISP1_CIF_ISP_CTRL_ISP_ENABLE |
555 RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE;
556 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL);
557
558 /*
559 * CIF spec says to wait for sufficient time after enabling
560 * the MIPI interface and before starting the sensor output.
561 */
562 usleep_range(1000, 1200);
563 }
564
565 /* ----------------------------------------------------------------------------
566 * Subdev pad operations
567 */
568
rkisp1_isp_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)569 static int rkisp1_isp_enum_mbus_code(struct v4l2_subdev *sd,
570 struct v4l2_subdev_state *sd_state,
571 struct v4l2_subdev_mbus_code_enum *code)
572 {
573 unsigned int i, dir;
574 int pos = 0;
575
576 if (code->pad == RKISP1_ISP_PAD_SINK_VIDEO) {
577 dir = RKISP1_ISP_SD_SINK;
578 } else if (code->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) {
579 dir = RKISP1_ISP_SD_SRC;
580 } else {
581 if (code->index > 0)
582 return -EINVAL;
583 code->code = MEDIA_BUS_FMT_METADATA_FIXED;
584 return 0;
585 }
586
587 if (code->index >= ARRAY_SIZE(rkisp1_isp_formats))
588 return -EINVAL;
589
590 for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) {
591 const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i];
592
593 if (fmt->direction & dir)
594 pos++;
595
596 if (code->index == pos - 1) {
597 code->code = fmt->mbus_code;
598 if (fmt->pixel_enc == V4L2_PIXEL_ENC_YUV &&
599 dir == RKISP1_ISP_SD_SRC)
600 code->flags =
601 V4L2_SUBDEV_MBUS_CODE_CSC_QUANTIZATION;
602 return 0;
603 }
604 }
605
606 return -EINVAL;
607 }
608
rkisp1_isp_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)609 static int rkisp1_isp_enum_frame_size(struct v4l2_subdev *sd,
610 struct v4l2_subdev_state *sd_state,
611 struct v4l2_subdev_frame_size_enum *fse)
612 {
613 const struct rkisp1_isp_mbus_info *mbus_info;
614
615 if (fse->pad == RKISP1_ISP_PAD_SINK_PARAMS ||
616 fse->pad == RKISP1_ISP_PAD_SOURCE_STATS)
617 return -ENOTTY;
618
619 if (fse->index > 0)
620 return -EINVAL;
621
622 mbus_info = rkisp1_isp_mbus_info_get(fse->code);
623 if (!mbus_info)
624 return -EINVAL;
625
626 if (!(mbus_info->direction & RKISP1_ISP_SD_SINK) &&
627 fse->pad == RKISP1_ISP_PAD_SINK_VIDEO)
628 return -EINVAL;
629
630 if (!(mbus_info->direction & RKISP1_ISP_SD_SRC) &&
631 fse->pad == RKISP1_ISP_PAD_SOURCE_VIDEO)
632 return -EINVAL;
633
634 fse->min_width = RKISP1_ISP_MIN_WIDTH;
635 fse->max_width = RKISP1_ISP_MAX_WIDTH;
636 fse->min_height = RKISP1_ISP_MIN_HEIGHT;
637 fse->max_height = RKISP1_ISP_MAX_HEIGHT;
638
639 return 0;
640 }
641
rkisp1_isp_init_config(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)642 static int rkisp1_isp_init_config(struct v4l2_subdev *sd,
643 struct v4l2_subdev_state *sd_state)
644 {
645 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
646 struct v4l2_rect *sink_crop, *src_crop;
647
648 sink_fmt = v4l2_subdev_get_try_format(sd, sd_state,
649 RKISP1_ISP_PAD_SINK_VIDEO);
650 sink_fmt->width = RKISP1_DEFAULT_WIDTH;
651 sink_fmt->height = RKISP1_DEFAULT_HEIGHT;
652 sink_fmt->field = V4L2_FIELD_NONE;
653 sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT;
654
655 sink_crop = v4l2_subdev_get_try_crop(sd, sd_state,
656 RKISP1_ISP_PAD_SINK_VIDEO);
657 sink_crop->width = RKISP1_DEFAULT_WIDTH;
658 sink_crop->height = RKISP1_DEFAULT_HEIGHT;
659 sink_crop->left = 0;
660 sink_crop->top = 0;
661
662 src_fmt = v4l2_subdev_get_try_format(sd, sd_state,
663 RKISP1_ISP_PAD_SOURCE_VIDEO);
664 *src_fmt = *sink_fmt;
665 src_fmt->code = RKISP1_DEF_SRC_PAD_FMT;
666
667 src_crop = v4l2_subdev_get_try_crop(sd, sd_state,
668 RKISP1_ISP_PAD_SOURCE_VIDEO);
669 *src_crop = *sink_crop;
670
671 sink_fmt = v4l2_subdev_get_try_format(sd, sd_state,
672 RKISP1_ISP_PAD_SINK_PARAMS);
673 src_fmt = v4l2_subdev_get_try_format(sd, sd_state,
674 RKISP1_ISP_PAD_SOURCE_STATS);
675 sink_fmt->width = 0;
676 sink_fmt->height = 0;
677 sink_fmt->field = V4L2_FIELD_NONE;
678 sink_fmt->code = MEDIA_BUS_FMT_METADATA_FIXED;
679 *src_fmt = *sink_fmt;
680
681 return 0;
682 }
683
rkisp1_isp_set_src_fmt(struct rkisp1_isp * isp,struct v4l2_subdev_state * sd_state,struct v4l2_mbus_framefmt * format,unsigned int which)684 static void rkisp1_isp_set_src_fmt(struct rkisp1_isp *isp,
685 struct v4l2_subdev_state *sd_state,
686 struct v4l2_mbus_framefmt *format,
687 unsigned int which)
688 {
689 const struct rkisp1_isp_mbus_info *mbus_info;
690 struct v4l2_mbus_framefmt *src_fmt;
691 const struct v4l2_rect *src_crop;
692
693 src_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state,
694 RKISP1_ISP_PAD_SOURCE_VIDEO, which);
695 src_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
696 RKISP1_ISP_PAD_SOURCE_VIDEO, which);
697
698 src_fmt->code = format->code;
699 mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code);
700 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SRC)) {
701 src_fmt->code = RKISP1_DEF_SRC_PAD_FMT;
702 mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code);
703 }
704 if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
705 isp->src_fmt = mbus_info;
706 src_fmt->width = src_crop->width;
707 src_fmt->height = src_crop->height;
708
709 /*
710 * The CSC API is used to allow userspace to force full
711 * quantization on YUV formats.
712 */
713 if (format->flags & V4L2_MBUS_FRAMEFMT_SET_CSC &&
714 format->quantization == V4L2_QUANTIZATION_FULL_RANGE &&
715 mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV)
716 src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
717 else if (mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV)
718 src_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE;
719 else
720 src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
721
722 *format = *src_fmt;
723 }
724
rkisp1_isp_set_src_crop(struct rkisp1_isp * isp,struct v4l2_subdev_state * sd_state,struct v4l2_rect * r,unsigned int which)725 static void rkisp1_isp_set_src_crop(struct rkisp1_isp *isp,
726 struct v4l2_subdev_state *sd_state,
727 struct v4l2_rect *r, unsigned int which)
728 {
729 struct v4l2_mbus_framefmt *src_fmt;
730 const struct v4l2_rect *sink_crop;
731 struct v4l2_rect *src_crop;
732
733 src_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
734 RKISP1_ISP_PAD_SOURCE_VIDEO,
735 which);
736 sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
737 RKISP1_ISP_PAD_SINK_VIDEO,
738 which);
739
740 src_crop->left = ALIGN(r->left, 2);
741 src_crop->width = ALIGN(r->width, 2);
742 src_crop->top = r->top;
743 src_crop->height = r->height;
744 rkisp1_sd_adjust_crop_rect(src_crop, sink_crop);
745
746 *r = *src_crop;
747
748 /* Propagate to out format */
749 src_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state,
750 RKISP1_ISP_PAD_SOURCE_VIDEO, which);
751 rkisp1_isp_set_src_fmt(isp, sd_state, src_fmt, which);
752 }
753
rkisp1_isp_set_sink_crop(struct rkisp1_isp * isp,struct v4l2_subdev_state * sd_state,struct v4l2_rect * r,unsigned int which)754 static void rkisp1_isp_set_sink_crop(struct rkisp1_isp *isp,
755 struct v4l2_subdev_state *sd_state,
756 struct v4l2_rect *r, unsigned int which)
757 {
758 struct v4l2_rect *sink_crop, *src_crop;
759 struct v4l2_mbus_framefmt *sink_fmt;
760
761 sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
762 RKISP1_ISP_PAD_SINK_VIDEO,
763 which);
764 sink_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state,
765 RKISP1_ISP_PAD_SINK_VIDEO,
766 which);
767
768 sink_crop->left = ALIGN(r->left, 2);
769 sink_crop->width = ALIGN(r->width, 2);
770 sink_crop->top = r->top;
771 sink_crop->height = r->height;
772 rkisp1_sd_adjust_crop(sink_crop, sink_fmt);
773
774 *r = *sink_crop;
775
776 /* Propagate to out crop */
777 src_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
778 RKISP1_ISP_PAD_SOURCE_VIDEO, which);
779 rkisp1_isp_set_src_crop(isp, sd_state, src_crop, which);
780 }
781
rkisp1_isp_set_sink_fmt(struct rkisp1_isp * isp,struct v4l2_subdev_state * sd_state,struct v4l2_mbus_framefmt * format,unsigned int which)782 static void rkisp1_isp_set_sink_fmt(struct rkisp1_isp *isp,
783 struct v4l2_subdev_state *sd_state,
784 struct v4l2_mbus_framefmt *format,
785 unsigned int which)
786 {
787 const struct rkisp1_isp_mbus_info *mbus_info;
788 struct v4l2_mbus_framefmt *sink_fmt;
789 struct v4l2_rect *sink_crop;
790
791 sink_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state,
792 RKISP1_ISP_PAD_SINK_VIDEO,
793 which);
794 sink_fmt->code = format->code;
795 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
796 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) {
797 sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT;
798 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
799 }
800 if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
801 isp->sink_fmt = mbus_info;
802
803 sink_fmt->width = clamp_t(u32, format->width,
804 RKISP1_ISP_MIN_WIDTH,
805 RKISP1_ISP_MAX_WIDTH);
806 sink_fmt->height = clamp_t(u32, format->height,
807 RKISP1_ISP_MIN_HEIGHT,
808 RKISP1_ISP_MAX_HEIGHT);
809
810 *format = *sink_fmt;
811
812 /* Propagate to in crop */
813 sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state,
814 RKISP1_ISP_PAD_SINK_VIDEO,
815 which);
816 rkisp1_isp_set_sink_crop(isp, sd_state, sink_crop, which);
817 }
818
rkisp1_isp_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)819 static int rkisp1_isp_get_fmt(struct v4l2_subdev *sd,
820 struct v4l2_subdev_state *sd_state,
821 struct v4l2_subdev_format *fmt)
822 {
823 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
824
825 mutex_lock(&isp->ops_lock);
826 fmt->format = *rkisp1_isp_get_pad_fmt(isp, sd_state, fmt->pad,
827 fmt->which);
828 mutex_unlock(&isp->ops_lock);
829 return 0;
830 }
831
rkisp1_isp_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)832 static int rkisp1_isp_set_fmt(struct v4l2_subdev *sd,
833 struct v4l2_subdev_state *sd_state,
834 struct v4l2_subdev_format *fmt)
835 {
836 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
837
838 mutex_lock(&isp->ops_lock);
839 if (fmt->pad == RKISP1_ISP_PAD_SINK_VIDEO)
840 rkisp1_isp_set_sink_fmt(isp, sd_state, &fmt->format,
841 fmt->which);
842 else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_VIDEO)
843 rkisp1_isp_set_src_fmt(isp, sd_state, &fmt->format,
844 fmt->which);
845 else
846 fmt->format = *rkisp1_isp_get_pad_fmt(isp, sd_state, fmt->pad,
847 fmt->which);
848
849 mutex_unlock(&isp->ops_lock);
850 return 0;
851 }
852
rkisp1_isp_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)853 static int rkisp1_isp_get_selection(struct v4l2_subdev *sd,
854 struct v4l2_subdev_state *sd_state,
855 struct v4l2_subdev_selection *sel)
856 {
857 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
858 int ret = 0;
859
860 if (sel->pad != RKISP1_ISP_PAD_SOURCE_VIDEO &&
861 sel->pad != RKISP1_ISP_PAD_SINK_VIDEO)
862 return -EINVAL;
863
864 mutex_lock(&isp->ops_lock);
865 switch (sel->target) {
866 case V4L2_SEL_TGT_CROP_BOUNDS:
867 if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO) {
868 struct v4l2_mbus_framefmt *fmt;
869
870 fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, sel->pad,
871 sel->which);
872 sel->r.height = fmt->height;
873 sel->r.width = fmt->width;
874 sel->r.left = 0;
875 sel->r.top = 0;
876 } else {
877 sel->r = *rkisp1_isp_get_pad_crop(isp, sd_state,
878 RKISP1_ISP_PAD_SINK_VIDEO,
879 sel->which);
880 }
881 break;
882 case V4L2_SEL_TGT_CROP:
883 sel->r = *rkisp1_isp_get_pad_crop(isp, sd_state, sel->pad,
884 sel->which);
885 break;
886 default:
887 ret = -EINVAL;
888 }
889 mutex_unlock(&isp->ops_lock);
890 return ret;
891 }
892
rkisp1_isp_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)893 static int rkisp1_isp_set_selection(struct v4l2_subdev *sd,
894 struct v4l2_subdev_state *sd_state,
895 struct v4l2_subdev_selection *sel)
896 {
897 struct rkisp1_device *rkisp1 =
898 container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev);
899 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd);
900 int ret = 0;
901
902 if (sel->target != V4L2_SEL_TGT_CROP)
903 return -EINVAL;
904
905 dev_dbg(rkisp1->dev, "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__,
906 sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height);
907 mutex_lock(&isp->ops_lock);
908 if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO)
909 rkisp1_isp_set_sink_crop(isp, sd_state, &sel->r, sel->which);
910 else if (sel->pad == RKISP1_ISP_PAD_SOURCE_VIDEO)
911 rkisp1_isp_set_src_crop(isp, sd_state, &sel->r, sel->which);
912 else
913 ret = -EINVAL;
914
915 mutex_unlock(&isp->ops_lock);
916 return ret;
917 }
918
rkisp1_subdev_link_validate(struct media_link * link)919 static int rkisp1_subdev_link_validate(struct media_link *link)
920 {
921 if (link->sink->index == RKISP1_ISP_PAD_SINK_PARAMS)
922 return 0;
923
924 return v4l2_subdev_link_validate(link);
925 }
926
927 static const struct v4l2_subdev_pad_ops rkisp1_isp_pad_ops = {
928 .enum_mbus_code = rkisp1_isp_enum_mbus_code,
929 .enum_frame_size = rkisp1_isp_enum_frame_size,
930 .get_selection = rkisp1_isp_get_selection,
931 .set_selection = rkisp1_isp_set_selection,
932 .init_cfg = rkisp1_isp_init_config,
933 .get_fmt = rkisp1_isp_get_fmt,
934 .set_fmt = rkisp1_isp_set_fmt,
935 .link_validate = v4l2_subdev_link_validate_default,
936 };
937
938 /* ----------------------------------------------------------------------------
939 * Stream operations
940 */
941
rkisp1_mipi_csi2_start(struct rkisp1_isp * isp,struct rkisp1_sensor_async * sensor)942 static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
943 struct rkisp1_sensor_async *sensor)
944 {
945 struct rkisp1_device *rkisp1 =
946 container_of(isp->sd.v4l2_dev, struct rkisp1_device, v4l2_dev);
947 union phy_configure_opts opts;
948 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
949 s64 pixel_clock;
950
951 if (!sensor->pixel_rate_ctrl) {
952 dev_warn(rkisp1->dev, "No pixel rate control in sensor subdev\n");
953 return -EPIPE;
954 }
955
956 pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl);
957 if (!pixel_clock) {
958 dev_err(rkisp1->dev, "Invalid pixel rate value\n");
959 return -EINVAL;
960 }
961
962 phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
963 sensor->lanes, cfg);
964 phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
965 phy_configure(sensor->dphy, &opts);
966 phy_power_on(sensor->dphy);
967
968 return 0;
969 }
970
rkisp1_mipi_csi2_stop(struct rkisp1_sensor_async * sensor)971 static void rkisp1_mipi_csi2_stop(struct rkisp1_sensor_async *sensor)
972 {
973 phy_power_off(sensor->dphy);
974 }
975
rkisp1_isp_s_stream(struct v4l2_subdev * sd,int enable)976 static int rkisp1_isp_s_stream(struct v4l2_subdev *sd, int enable)
977 {
978 struct rkisp1_device *rkisp1 =
979 container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev);
980 struct rkisp1_isp *isp = &rkisp1->isp;
981 struct v4l2_subdev *sensor_sd;
982 int ret = 0;
983
984 if (!enable) {
985 rkisp1_isp_stop(rkisp1);
986 rkisp1_mipi_csi2_stop(rkisp1->active_sensor);
987 return 0;
988 }
989
990 sensor_sd = rkisp1_get_remote_sensor(sd);
991 if (!sensor_sd) {
992 dev_warn(rkisp1->dev, "No link between isp and sensor\n");
993 return -ENODEV;
994 }
995
996 rkisp1->active_sensor = container_of(sensor_sd->asd,
997 struct rkisp1_sensor_async, asd);
998
999 if (rkisp1->active_sensor->mbus_type != V4L2_MBUS_CSI2_DPHY)
1000 return -EINVAL;
1001
1002 rkisp1->isp.frame_sequence = -1;
1003 mutex_lock(&isp->ops_lock);
1004 ret = rkisp1_config_cif(rkisp1);
1005 if (ret)
1006 goto mutex_unlock;
1007
1008 ret = rkisp1_mipi_csi2_start(&rkisp1->isp, rkisp1->active_sensor);
1009 if (ret)
1010 goto mutex_unlock;
1011
1012 rkisp1_isp_start(rkisp1);
1013
1014 mutex_unlock:
1015 mutex_unlock(&isp->ops_lock);
1016 return ret;
1017 }
1018
rkisp1_isp_subs_evt(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)1019 static int rkisp1_isp_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1020 struct v4l2_event_subscription *sub)
1021 {
1022 if (sub->type != V4L2_EVENT_FRAME_SYNC)
1023 return -EINVAL;
1024
1025 /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */
1026 if (sub->id != 0)
1027 return -EINVAL;
1028
1029 return v4l2_event_subscribe(fh, sub, 0, NULL);
1030 }
1031
1032 static const struct media_entity_operations rkisp1_isp_media_ops = {
1033 .link_validate = rkisp1_subdev_link_validate,
1034 };
1035
1036 static const struct v4l2_subdev_video_ops rkisp1_isp_video_ops = {
1037 .s_stream = rkisp1_isp_s_stream,
1038 };
1039
1040 static const struct v4l2_subdev_core_ops rkisp1_isp_core_ops = {
1041 .subscribe_event = rkisp1_isp_subs_evt,
1042 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1043 };
1044
1045 static const struct v4l2_subdev_ops rkisp1_isp_ops = {
1046 .core = &rkisp1_isp_core_ops,
1047 .video = &rkisp1_isp_video_ops,
1048 .pad = &rkisp1_isp_pad_ops,
1049 };
1050
rkisp1_isp_register(struct rkisp1_device * rkisp1)1051 int rkisp1_isp_register(struct rkisp1_device *rkisp1)
1052 {
1053 struct v4l2_subdev_state state = {
1054 .pads = rkisp1->isp.pad_cfg
1055 };
1056 struct rkisp1_isp *isp = &rkisp1->isp;
1057 struct media_pad *pads = isp->pads;
1058 struct v4l2_subdev *sd = &isp->sd;
1059 int ret;
1060
1061 v4l2_subdev_init(sd, &rkisp1_isp_ops);
1062 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1063 sd->entity.ops = &rkisp1_isp_media_ops;
1064 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1065 sd->owner = THIS_MODULE;
1066 strscpy(sd->name, RKISP1_ISP_DEV_NAME, sizeof(sd->name));
1067
1068 pads[RKISP1_ISP_PAD_SINK_VIDEO].flags = MEDIA_PAD_FL_SINK |
1069 MEDIA_PAD_FL_MUST_CONNECT;
1070 pads[RKISP1_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK;
1071 pads[RKISP1_ISP_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE;
1072 pads[RKISP1_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE;
1073
1074 isp->sink_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SINK_PAD_FMT);
1075 isp->src_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SRC_PAD_FMT);
1076
1077 mutex_init(&isp->ops_lock);
1078 ret = media_entity_pads_init(&sd->entity, RKISP1_ISP_PAD_MAX, pads);
1079 if (ret)
1080 return ret;
1081
1082 ret = v4l2_device_register_subdev(&rkisp1->v4l2_dev, sd);
1083 if (ret) {
1084 dev_err(rkisp1->dev, "Failed to register isp subdev\n");
1085 goto err_cleanup_media_entity;
1086 }
1087
1088 rkisp1_isp_init_config(sd, &state);
1089 return 0;
1090
1091 err_cleanup_media_entity:
1092 media_entity_cleanup(&sd->entity);
1093
1094 return ret;
1095 }
1096
rkisp1_isp_unregister(struct rkisp1_device * rkisp1)1097 void rkisp1_isp_unregister(struct rkisp1_device *rkisp1)
1098 {
1099 struct v4l2_subdev *sd = &rkisp1->isp.sd;
1100
1101 v4l2_device_unregister_subdev(sd);
1102 media_entity_cleanup(&sd->entity);
1103 }
1104
1105 /* ----------------------------------------------------------------------------
1106 * Interrupt handlers
1107 */
1108
rkisp1_mipi_isr(struct rkisp1_device * rkisp1)1109 void rkisp1_mipi_isr(struct rkisp1_device *rkisp1)
1110 {
1111 u32 val, status;
1112
1113 status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS);
1114 if (!status)
1115 return;
1116
1117 rkisp1_write(rkisp1, status, RKISP1_CIF_MIPI_ICR);
1118
1119 /*
1120 * Disable DPHY errctrl interrupt, because this dphy
1121 * erctrl signal is asserted until the next changes
1122 * of line state. This time is may be too long and cpu
1123 * is hold in this interrupt.
1124 */
1125 if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) {
1126 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
1127 rkisp1_write(rkisp1, val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f),
1128 RKISP1_CIF_MIPI_IMSC);
1129 rkisp1->isp.is_dphy_errctrl_disabled = true;
1130 }
1131
1132 /*
1133 * Enable DPHY errctrl interrupt again, if mipi have receive
1134 * the whole frame without any error.
1135 */
1136 if (status == RKISP1_CIF_MIPI_FRAME_END) {
1137 /*
1138 * Enable DPHY errctrl interrupt again, if mipi have receive
1139 * the whole frame without any error.
1140 */
1141 if (rkisp1->isp.is_dphy_errctrl_disabled) {
1142 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
1143 val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f);
1144 rkisp1_write(rkisp1, val, RKISP1_CIF_MIPI_IMSC);
1145 rkisp1->isp.is_dphy_errctrl_disabled = false;
1146 }
1147 } else {
1148 rkisp1->debug.mipi_error++;
1149 }
1150 }
1151
rkisp1_isp_queue_event_sof(struct rkisp1_isp * isp)1152 static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp)
1153 {
1154 struct v4l2_event event = {
1155 .type = V4L2_EVENT_FRAME_SYNC,
1156 };
1157 event.u.frame_sync.frame_sequence = isp->frame_sequence;
1158
1159 v4l2_event_queue(isp->sd.devnode, &event);
1160 }
1161
rkisp1_isp_isr(struct rkisp1_device * rkisp1)1162 void rkisp1_isp_isr(struct rkisp1_device *rkisp1)
1163 {
1164 u32 status, isp_err;
1165
1166 status = rkisp1_read(rkisp1, RKISP1_CIF_ISP_MIS);
1167 if (!status)
1168 return;
1169
1170 rkisp1_write(rkisp1, status, RKISP1_CIF_ISP_ICR);
1171
1172 /* Vertical sync signal, starting generating new frame */
1173 if (status & RKISP1_CIF_ISP_V_START) {
1174 rkisp1->isp.frame_sequence++;
1175 rkisp1_isp_queue_event_sof(&rkisp1->isp);
1176 if (status & RKISP1_CIF_ISP_FRAME) {
1177 WARN_ONCE(1, "irq delay is too long, buffers might not be in sync\n");
1178 rkisp1->debug.irq_delay++;
1179 }
1180 }
1181 if (status & RKISP1_CIF_ISP_PIC_SIZE_ERROR) {
1182 /* Clear pic_size_error */
1183 isp_err = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ERR);
1184 if (isp_err & RKISP1_CIF_ISP_ERR_INFORM_SIZE)
1185 rkisp1->debug.inform_size_error++;
1186 if (isp_err & RKISP1_CIF_ISP_ERR_IS_SIZE)
1187 rkisp1->debug.img_stabilization_size_error++;
1188 if (isp_err & RKISP1_CIF_ISP_ERR_OUTFORM_SIZE)
1189 rkisp1->debug.outform_size_error++;
1190 rkisp1_write(rkisp1, isp_err, RKISP1_CIF_ISP_ERR_CLR);
1191 } else if (status & RKISP1_CIF_ISP_DATA_LOSS) {
1192 /* keep track of data_loss in debugfs */
1193 rkisp1->debug.data_loss++;
1194 }
1195
1196 if (status & RKISP1_CIF_ISP_FRAME) {
1197 u32 isp_ris;
1198
1199 /* New frame from the sensor received */
1200 isp_ris = rkisp1_read(rkisp1, RKISP1_CIF_ISP_RIS);
1201 if (isp_ris & RKISP1_STATS_MEAS_MASK)
1202 rkisp1_stats_isr(&rkisp1->stats, isp_ris);
1203 /*
1204 * Then update changed configs. Some of them involve
1205 * lot of register writes. Do those only one per frame.
1206 * Do the updates in the order of the processing flow.
1207 */
1208 rkisp1_params_isr(rkisp1);
1209 }
1210 }
1211
