1 /*
2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012-2013 Xilinx, Inc.
4 * Copyright (C) 2007-2009 PetaLogix
5 * Copyright (C) 2006 Atmark Techno, Inc.
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12 #include <linux/irqdomain.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/of_address.h>
17 #include <linux/io.h>
18 #include <linux/jump_label.h>
19 #include <linux/bug.h>
20 #include <linux/of_irq.h>
21
22 /* No one else should require these constants, so define them locally here. */
23 #define ISR 0x00 /* Interrupt Status Register */
24 #define IPR 0x04 /* Interrupt Pending Register */
25 #define IER 0x08 /* Interrupt Enable Register */
26 #define IAR 0x0c /* Interrupt Acknowledge Register */
27 #define SIE 0x10 /* Set Interrupt Enable bits */
28 #define CIE 0x14 /* Clear Interrupt Enable bits */
29 #define IVR 0x18 /* Interrupt Vector Register */
30 #define MER 0x1c /* Master Enable Register */
31
32 #define MER_ME (1<<0)
33 #define MER_HIE (1<<1)
34
35 static DEFINE_STATIC_KEY_FALSE(xintc_is_be);
36
37 struct xintc_irq_chip {
38 void __iomem *base;
39 struct irq_domain *root_domain;
40 u32 intr_mask;
41 u32 nr_irq;
42 };
43
44 static struct xintc_irq_chip *primary_intc;
45
xintc_write(struct xintc_irq_chip * irqc,int reg,u32 data)46 static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data)
47 {
48 if (static_branch_unlikely(&xintc_is_be))
49 iowrite32be(data, irqc->base + reg);
50 else
51 iowrite32(data, irqc->base + reg);
52 }
53
xintc_read(struct xintc_irq_chip * irqc,int reg)54 static u32 xintc_read(struct xintc_irq_chip *irqc, int reg)
55 {
56 if (static_branch_unlikely(&xintc_is_be))
57 return ioread32be(irqc->base + reg);
58 else
59 return ioread32(irqc->base + reg);
60 }
61
intc_enable_or_unmask(struct irq_data * d)62 static void intc_enable_or_unmask(struct irq_data *d)
63 {
64 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
65 unsigned long mask = BIT(d->hwirq);
66
67 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
68
69 /* ack level irqs because they can't be acked during
70 * ack function since the handle_level_irq function
71 * acks the irq before calling the interrupt handler
72 */
73 if (irqd_is_level_type(d))
74 xintc_write(irqc, IAR, mask);
75
76 xintc_write(irqc, SIE, mask);
77 }
78
intc_disable_or_mask(struct irq_data * d)79 static void intc_disable_or_mask(struct irq_data *d)
80 {
81 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
82
83 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
84 xintc_write(irqc, CIE, BIT(d->hwirq));
85 }
86
intc_ack(struct irq_data * d)87 static void intc_ack(struct irq_data *d)
88 {
89 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
90
91 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
92 xintc_write(irqc, IAR, BIT(d->hwirq));
93 }
94
intc_mask_ack(struct irq_data * d)95 static void intc_mask_ack(struct irq_data *d)
96 {
97 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
98 unsigned long mask = BIT(d->hwirq);
99
100 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
101 xintc_write(irqc, CIE, mask);
102 xintc_write(irqc, IAR, mask);
103 }
104
105 static struct irq_chip intc_dev = {
106 .name = "Xilinx INTC",
107 .irq_unmask = intc_enable_or_unmask,
108 .irq_mask = intc_disable_or_mask,
109 .irq_ack = intc_ack,
110 .irq_mask_ack = intc_mask_ack,
111 };
112
xintc_get_irq(void)113 unsigned int xintc_get_irq(void)
114 {
115 unsigned int irq = -1;
116 u32 hwirq;
117
118 hwirq = xintc_read(primary_intc, IVR);
119 if (hwirq != -1U)
120 irq = irq_find_mapping(primary_intc->root_domain, hwirq);
121
122 pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
123
124 return irq;
125 }
126
xintc_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)127 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
128 {
129 struct xintc_irq_chip *irqc = d->host_data;
130
131 if (irqc->intr_mask & BIT(hw)) {
132 irq_set_chip_and_handler_name(irq, &intc_dev,
133 handle_edge_irq, "edge");
134 irq_clear_status_flags(irq, IRQ_LEVEL);
135 } else {
136 irq_set_chip_and_handler_name(irq, &intc_dev,
137 handle_level_irq, "level");
138 irq_set_status_flags(irq, IRQ_LEVEL);
139 }
140 irq_set_chip_data(irq, irqc);
141 return 0;
142 }
143
144 static const struct irq_domain_ops xintc_irq_domain_ops = {
145 .xlate = irq_domain_xlate_onetwocell,
146 .map = xintc_map,
147 };
148
xil_intc_irq_handler(struct irq_desc * desc)149 static void xil_intc_irq_handler(struct irq_desc *desc)
150 {
151 struct irq_chip *chip = irq_desc_get_chip(desc);
152 struct xintc_irq_chip *irqc;
153
154 irqc = irq_data_get_irq_handler_data(&desc->irq_data);
155 chained_irq_enter(chip, desc);
156 do {
157 u32 hwirq = xintc_read(irqc, IVR);
158
159 if (hwirq == -1U)
160 break;
161
162 generic_handle_domain_irq(irqc->root_domain, hwirq);
163 } while (true);
164 chained_irq_exit(chip, desc);
165 }
166
xilinx_intc_of_init(struct device_node * intc,struct device_node * parent)167 static int __init xilinx_intc_of_init(struct device_node *intc,
168 struct device_node *parent)
169 {
170 struct xintc_irq_chip *irqc;
171 int ret, irq;
172
173 irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
174 if (!irqc)
175 return -ENOMEM;
176 irqc->base = of_iomap(intc, 0);
177 BUG_ON(!irqc->base);
178
179 ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);
180 if (ret < 0) {
181 pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
182 goto error;
183 }
184
185 ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
186 if (ret < 0) {
187 pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
188 irqc->intr_mask = 0;
189 }
190
191 if (irqc->intr_mask >> irqc->nr_irq)
192 pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
193
194 pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",
195 intc, irqc->nr_irq, irqc->intr_mask);
196
197
198 /*
199 * Disable all external interrupts until they are
200 * explicitly requested.
201 */
202 xintc_write(irqc, IER, 0);
203
204 /* Acknowledge any pending interrupts just in case. */
205 xintc_write(irqc, IAR, 0xffffffff);
206
207 /* Turn on the Master Enable. */
208 xintc_write(irqc, MER, MER_HIE | MER_ME);
209 if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) {
210 static_branch_enable(&xintc_is_be);
211 xintc_write(irqc, MER, MER_HIE | MER_ME);
212 }
213
214 irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
215 &xintc_irq_domain_ops, irqc);
216 if (!irqc->root_domain) {
217 pr_err("irq-xilinx: Unable to create IRQ domain\n");
218 ret = -EINVAL;
219 goto error;
220 }
221
222 if (parent) {
223 irq = irq_of_parse_and_map(intc, 0);
224 if (irq) {
225 irq_set_chained_handler_and_data(irq,
226 xil_intc_irq_handler,
227 irqc);
228 } else {
229 pr_err("irq-xilinx: interrupts property not in DT\n");
230 ret = -EINVAL;
231 goto error;
232 }
233 } else {
234 primary_intc = irqc;
235 irq_set_default_host(primary_intc->root_domain);
236 }
237
238 return 0;
239
240 error:
241 iounmap(irqc->base);
242 kfree(irqc);
243 return ret;
244
245 }
246
247 IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
248 IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);
249
