1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Atmel ADC driver for SAMA5D2 devices and compatible.
4 *
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 */
8
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/wait.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/trigger.h>
25 #include <linux/iio/trigger_consumer.h>
26 #include <linux/iio/triggered_buffer.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/regulator/consumer.h>
29
30 /* Control Register */
31 #define AT91_SAMA5D2_CR 0x00
32 /* Software Reset */
33 #define AT91_SAMA5D2_CR_SWRST BIT(0)
34 /* Start Conversion */
35 #define AT91_SAMA5D2_CR_START BIT(1)
36 /* Touchscreen Calibration */
37 #define AT91_SAMA5D2_CR_TSCALIB BIT(2)
38 /* Comparison Restart */
39 #define AT91_SAMA5D2_CR_CMPRST BIT(4)
40
41 /* Mode Register */
42 #define AT91_SAMA5D2_MR 0x04
43 /* Trigger Selection */
44 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
45 /* ADTRG */
46 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
47 /* TIOA0 */
48 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
49 /* TIOA1 */
50 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
51 /* TIOA2 */
52 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
53 /* PWM event line 0 */
54 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
55 /* PWM event line 1 */
56 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
57 /* TIOA3 */
58 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
59 /* RTCOUT0 */
60 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
61 /* Sleep Mode */
62 #define AT91_SAMA5D2_MR_SLEEP BIT(5)
63 /* Fast Wake Up */
64 #define AT91_SAMA5D2_MR_FWUP BIT(6)
65 /* Prescaler Rate Selection */
66 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
67 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
68 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
69 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)
70 /* Startup Time */
71 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
72 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)
73 /* Analog Change */
74 #define AT91_SAMA5D2_MR_ANACH BIT(23)
75 /* Tracking Time */
76 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
77 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff
78 /* Transfer Time */
79 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
80 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
81 /* Use Sequence Enable */
82 #define AT91_SAMA5D2_MR_USEQ BIT(31)
83
84 /* Channel Sequence Register 1 */
85 #define AT91_SAMA5D2_SEQR1 0x08
86 /* Channel Sequence Register 2 */
87 #define AT91_SAMA5D2_SEQR2 0x0c
88 /* Channel Enable Register */
89 #define AT91_SAMA5D2_CHER 0x10
90 /* Channel Disable Register */
91 #define AT91_SAMA5D2_CHDR 0x14
92 /* Channel Status Register */
93 #define AT91_SAMA5D2_CHSR 0x18
94 /* Last Converted Data Register */
95 #define AT91_SAMA5D2_LCDR 0x20
96 /* Interrupt Enable Register */
97 #define AT91_SAMA5D2_IER 0x24
98 /* Interrupt Enable Register - TS X measurement ready */
99 #define AT91_SAMA5D2_IER_XRDY BIT(20)
100 /* Interrupt Enable Register - TS Y measurement ready */
101 #define AT91_SAMA5D2_IER_YRDY BIT(21)
102 /* Interrupt Enable Register - TS pressure measurement ready */
103 #define AT91_SAMA5D2_IER_PRDY BIT(22)
104 /* Interrupt Enable Register - Data ready */
105 #define AT91_SAMA5D2_IER_DRDY BIT(24)
106 /* Interrupt Enable Register - general overrun error */
107 #define AT91_SAMA5D2_IER_GOVRE BIT(25)
108 /* Interrupt Enable Register - Pen detect */
109 #define AT91_SAMA5D2_IER_PEN BIT(29)
110 /* Interrupt Enable Register - No pen detect */
111 #define AT91_SAMA5D2_IER_NOPEN BIT(30)
112 /* Interrupt Disable Register */
113 #define AT91_SAMA5D2_IDR 0x28
114 /* Interrupt Mask Register */
115 #define AT91_SAMA5D2_IMR 0x2c
116 /* Interrupt Status Register */
117 #define AT91_SAMA5D2_ISR 0x30
118 /* Interrupt Status Register - Pen touching sense status */
119 #define AT91_SAMA5D2_ISR_PENS BIT(31)
120 /* Last Channel Trigger Mode Register */
121 #define AT91_SAMA5D2_LCTMR 0x34
122 /* Last Channel Compare Window Register */
123 #define AT91_SAMA5D2_LCCWR 0x38
124 /* Overrun Status Register */
125 #define AT91_SAMA5D2_OVER 0x3c
126 /* Extended Mode Register */
127 #define AT91_SAMA5D2_EMR 0x40
128 /* Extended Mode Register - Oversampling rate */
129 #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16)
130 #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16)
131 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0
132 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1
133 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2
134
135 /* Extended Mode Register - Averaging on single trigger event */
136 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20)
137 /* Compare Window Register */
138 #define AT91_SAMA5D2_CWR 0x44
139 /* Channel Gain Register */
140 #define AT91_SAMA5D2_CGR 0x48
141
142 /* Channel Offset Register */
143 #define AT91_SAMA5D2_COR 0x4c
144 #define AT91_SAMA5D2_COR_DIFF_OFFSET 16
145
146 /* Channel Data Register 0 */
147 #define AT91_SAMA5D2_CDR0 0x50
148 /* Analog Control Register */
149 #define AT91_SAMA5D2_ACR 0x94
150 /* Analog Control Register - Pen detect sensitivity mask */
151 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0)
152
153 /* Touchscreen Mode Register */
154 #define AT91_SAMA5D2_TSMR 0xb0
155 /* Touchscreen Mode Register - No touch mode */
156 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0
157 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
158 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1
159 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */
160 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2
161 /* Touchscreen Mode Register - 5 wire screen */
162 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3
163 /* Touchscreen Mode Register - Average samples mask */
164 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4)
165 /* Touchscreen Mode Register - Average samples */
166 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4)
167 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
168 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8)
169 /* Touchscreen Mode Register - Touch/trigger frequency ratio */
170 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8)
171 /* Touchscreen Mode Register - Pen Debounce Time mask */
172 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28)
173 /* Touchscreen Mode Register - Pen Debounce Time */
174 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28)
175 /* Touchscreen Mode Register - No DMA for touch measurements */
176 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22)
177 /* Touchscreen Mode Register - Disable pen detection */
178 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24)
179 /* Touchscreen Mode Register - Enable pen detection */
180 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24)
181
182 /* Touchscreen X Position Register */
183 #define AT91_SAMA5D2_XPOSR 0xb4
184 /* Touchscreen Y Position Register */
185 #define AT91_SAMA5D2_YPOSR 0xb8
186 /* Touchscreen Pressure Register */
187 #define AT91_SAMA5D2_PRESSR 0xbc
188 /* Trigger Register */
189 #define AT91_SAMA5D2_TRGR 0xc0
190 /* Mask for TRGMOD field of TRGR register */
191 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
192 /* No trigger, only software trigger can start conversions */
193 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
194 /* Trigger Mode external trigger rising edge */
195 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
196 /* Trigger Mode external trigger falling edge */
197 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
198 /* Trigger Mode external trigger any edge */
199 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
200 /* Trigger Mode internal periodic */
201 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5
202 /* Trigger Mode - trigger period mask */
203 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16)
204 /* Trigger Mode - trigger period */
205 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16)
206
207 /* Correction Select Register */
208 #define AT91_SAMA5D2_COSR 0xd0
209 /* Correction Value Register */
210 #define AT91_SAMA5D2_CVR 0xd4
211 /* Channel Error Correction Register */
212 #define AT91_SAMA5D2_CECR 0xd8
213 /* Write Protection Mode Register */
214 #define AT91_SAMA5D2_WPMR 0xe4
215 /* Write Protection Status Register */
216 #define AT91_SAMA5D2_WPSR 0xe8
217 /* Version Register */
218 #define AT91_SAMA5D2_VERSION 0xfc
219
220 #define AT91_SAMA5D2_HW_TRIG_CNT 3
221 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
222 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
223
224 #define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
225 AT91_SAMA5D2_DIFF_CHAN_CNT + 1)
226
227 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
228 AT91_SAMA5D2_DIFF_CHAN_CNT * 2)
229 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1)
230 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1)
231 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX
232
233 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
234 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200
235
236 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0)
237
238 #define AT91_SAMA5D2_MAX_POS_BITS 12
239
240 /*
241 * Maximum number of bytes to hold conversion from all channels
242 * without the timestamp.
243 */
244 #define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \
245 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2)
246
247 /* This total must also include the timestamp */
248 #define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8)
249
250 #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2)
251
252 #define AT91_HWFIFO_MAX_SIZE_STR "128"
253 #define AT91_HWFIFO_MAX_SIZE 128
254
255 /* Possible values for oversampling ratio */
256 #define AT91_OSR_1SAMPLES 1
257 #define AT91_OSR_4SAMPLES 4
258 #define AT91_OSR_16SAMPLES 16
259
260 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \
261 { \
262 .type = IIO_VOLTAGE, \
263 .channel = num, \
264 .address = addr, \
265 .scan_index = num, \
266 .scan_type = { \
267 .sign = 'u', \
268 .realbits = 14, \
269 .storagebits = 16, \
270 }, \
271 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
272 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
273 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
274 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
275 .datasheet_name = "CH"#num, \
276 .indexed = 1, \
277 }
278
279 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \
280 { \
281 .type = IIO_VOLTAGE, \
282 .differential = 1, \
283 .channel = num, \
284 .channel2 = num2, \
285 .address = addr, \
286 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \
287 .scan_type = { \
288 .sign = 's', \
289 .realbits = 14, \
290 .storagebits = 16, \
291 }, \
292 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
293 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
294 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
295 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
296 .datasheet_name = "CH"#num"-CH"#num2, \
297 .indexed = 1, \
298 }
299
300 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \
301 { \
302 .type = IIO_POSITIONRELATIVE, \
303 .modified = 1, \
304 .channel = num, \
305 .channel2 = mod, \
306 .scan_index = num, \
307 .scan_type = { \
308 .sign = 'u', \
309 .realbits = 12, \
310 .storagebits = 16, \
311 }, \
312 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
313 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
314 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
315 .datasheet_name = name, \
316 }
317 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \
318 { \
319 .type = IIO_PRESSURE, \
320 .channel = num, \
321 .scan_index = num, \
322 .scan_type = { \
323 .sign = 'u', \
324 .realbits = 12, \
325 .storagebits = 16, \
326 }, \
327 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
328 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
329 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
330 .datasheet_name = name, \
331 }
332
333 #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg)
334 #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg)
335
336 struct at91_adc_soc_info {
337 unsigned startup_time;
338 unsigned min_sample_rate;
339 unsigned max_sample_rate;
340 };
341
342 struct at91_adc_trigger {
343 char *name;
344 unsigned int trgmod_value;
345 unsigned int edge_type;
346 bool hw_trig;
347 };
348
349 /**
350 * struct at91_adc_dma - at91-sama5d2 dma information struct
351 * @dma_chan: the dma channel acquired
352 * @rx_buf: dma coherent allocated area
353 * @rx_dma_buf: dma handler for the buffer
354 * @phys_addr: physical address of the ADC base register
355 * @buf_idx: index inside the dma buffer where reading was last done
356 * @rx_buf_sz: size of buffer used by DMA operation
357 * @watermark: number of conversions to copy before DMA triggers irq
358 * @dma_ts: hold the start timestamp of dma operation
359 */
360 struct at91_adc_dma {
361 struct dma_chan *dma_chan;
362 u8 *rx_buf;
363 dma_addr_t rx_dma_buf;
364 phys_addr_t phys_addr;
365 int buf_idx;
366 int rx_buf_sz;
367 int watermark;
368 s64 dma_ts;
369 };
370
371 /**
372 * struct at91_adc_touch - at91-sama5d2 touchscreen information struct
373 * @sample_period_val: the value for periodic trigger interval
374 * @touching: is the pen touching the screen or not
375 * @x_pos: temporary placeholder for pressure computation
376 * @channels_bitmask: bitmask with the touchscreen channels enabled
377 * @workq: workqueue for buffer data pushing
378 */
379 struct at91_adc_touch {
380 u16 sample_period_val;
381 bool touching;
382 u16 x_pos;
383 unsigned long channels_bitmask;
384 struct work_struct workq;
385 };
386
387 struct at91_adc_state {
388 void __iomem *base;
389 int irq;
390 struct clk *per_clk;
391 struct regulator *reg;
392 struct regulator *vref;
393 int vref_uv;
394 unsigned int current_sample_rate;
395 struct iio_trigger *trig;
396 const struct at91_adc_trigger *selected_trig;
397 const struct iio_chan_spec *chan;
398 bool conversion_done;
399 u32 conversion_value;
400 unsigned int oversampling_ratio;
401 struct at91_adc_soc_info soc_info;
402 wait_queue_head_t wq_data_available;
403 struct at91_adc_dma dma_st;
404 struct at91_adc_touch touch_st;
405 struct iio_dev *indio_dev;
406 /* Ensure naturally aligned timestamp */
407 u16 buffer[AT91_BUFFER_MAX_HWORDS] __aligned(8);
408 /*
409 * lock to prevent concurrent 'single conversion' requests through
410 * sysfs.
411 */
412 struct mutex lock;
413 };
414
415 static const struct at91_adc_trigger at91_adc_trigger_list[] = {
416 {
417 .name = "external_rising",
418 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
419 .edge_type = IRQ_TYPE_EDGE_RISING,
420 .hw_trig = true,
421 },
422 {
423 .name = "external_falling",
424 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
425 .edge_type = IRQ_TYPE_EDGE_FALLING,
426 .hw_trig = true,
427 },
428 {
429 .name = "external_any",
430 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
431 .edge_type = IRQ_TYPE_EDGE_BOTH,
432 .hw_trig = true,
433 },
434 {
435 .name = "software",
436 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
437 .edge_type = IRQ_TYPE_NONE,
438 .hw_trig = false,
439 },
440 };
441
442 static const struct iio_chan_spec at91_adc_channels[] = {
443 AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
444 AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
445 AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
446 AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
447 AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
448 AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
449 AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
450 AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
451 AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
452 AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
453 AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
454 AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
455 AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
456 AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
457 AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
458 AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
459 AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
460 AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
461 IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX),
462 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X),
463 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y),
464 AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"),
465 };
466
at91_adc_chan_xlate(struct iio_dev * indio_dev,int chan)467 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
468 {
469 int i;
470
471 for (i = 0; i < indio_dev->num_channels; i++) {
472 if (indio_dev->channels[i].scan_index == chan)
473 return i;
474 }
475 return -EINVAL;
476 }
477
478 static inline struct iio_chan_spec const *
at91_adc_chan_get(struct iio_dev * indio_dev,int chan)479 at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
480 {
481 int index = at91_adc_chan_xlate(indio_dev, chan);
482
483 if (index < 0)
484 return NULL;
485 return indio_dev->channels + index;
486 }
487
at91_adc_of_xlate(struct iio_dev * indio_dev,const struct of_phandle_args * iiospec)488 static inline int at91_adc_of_xlate(struct iio_dev *indio_dev,
489 const struct of_phandle_args *iiospec)
490 {
491 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
492 }
493
at91_adc_active_scan_mask_to_reg(struct iio_dev * indio_dev)494 static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev)
495 {
496 u32 mask = 0;
497 u8 bit;
498
499 for_each_set_bit(bit, indio_dev->active_scan_mask,
500 indio_dev->num_channels) {
501 struct iio_chan_spec const *chan =
502 at91_adc_chan_get(indio_dev, bit);
503 mask |= BIT(chan->channel);
504 }
505
506 return mask & GENMASK(11, 0);
507 }
508
at91_adc_config_emr(struct at91_adc_state * st)509 static void at91_adc_config_emr(struct at91_adc_state *st)
510 {
511 /* configure the extended mode register */
512 unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR);
513
514 /* select oversampling per single trigger event */
515 emr |= AT91_SAMA5D2_EMR_ASTE(1);
516
517 /* delete leftover content if it's the case */
518 emr &= ~AT91_SAMA5D2_EMR_OSR_MASK;
519
520 /* select oversampling ratio from configuration */
521 switch (st->oversampling_ratio) {
522 case AT91_OSR_1SAMPLES:
523 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) &
524 AT91_SAMA5D2_EMR_OSR_MASK;
525 break;
526 case AT91_OSR_4SAMPLES:
527 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) &
528 AT91_SAMA5D2_EMR_OSR_MASK;
529 break;
530 case AT91_OSR_16SAMPLES:
531 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) &
532 AT91_SAMA5D2_EMR_OSR_MASK;
533 break;
534 }
535
536 at91_adc_writel(st, AT91_SAMA5D2_EMR, emr);
537 }
538
at91_adc_adjust_val_osr(struct at91_adc_state * st,int * val)539 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
540 {
541 if (st->oversampling_ratio == AT91_OSR_1SAMPLES) {
542 /*
543 * in this case we only have 12 bits of real data, but channel
544 * is registered as 14 bits, so shift left two bits
545 */
546 *val <<= 2;
547 } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) {
548 /*
549 * in this case we have 13 bits of real data, but channel
550 * is registered as 14 bits, so left shift one bit
551 */
552 *val <<= 1;
553 }
554
555 return IIO_VAL_INT;
556 }
557
at91_adc_adjust_val_osr_array(struct at91_adc_state * st,void * buf,int len)558 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
559 int len)
560 {
561 int i = 0, val;
562 u16 *buf_u16 = (u16 *) buf;
563
564 /*
565 * We are converting each two bytes (each sample).
566 * First convert the byte based array to u16, and convert each sample
567 * separately.
568 * Each value is two bytes in an array of chars, so to not shift
569 * more than we need, save the value separately.
570 * len is in bytes, so divide by two to get number of samples.
571 */
572 while (i < len / 2) {
573 val = buf_u16[i];
574 at91_adc_adjust_val_osr(st, &val);
575 buf_u16[i] = val;
576 i++;
577 }
578 }
579
at91_adc_configure_touch(struct at91_adc_state * st,bool state)580 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
581 {
582 u32 clk_khz = st->current_sample_rate / 1000;
583 int i = 0;
584 u16 pendbc;
585 u32 tsmr, acr;
586
587 if (!state) {
588 /* disabling touch IRQs and setting mode to no touch enabled */
589 at91_adc_writel(st, AT91_SAMA5D2_IDR,
590 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN);
591 at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0);
592 return 0;
593 }
594 /*
595 * debounce time is in microseconds, we need it in milliseconds to
596 * multiply with kilohertz, so, divide by 1000, but after the multiply.
597 * round up to make sure pendbc is at least 1
598 */
599 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US *
600 clk_khz / 1000, 1);
601
602 /* get the required exponent */
603 while (pendbc >> i++)
604 ;
605
606 pendbc = i;
607
608 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS;
609
610 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK;
611 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) &
612 AT91_SAMA5D2_TSMR_PENDBC_MASK;
613 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA;
614 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA;
615 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK;
616
617 at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr);
618
619 acr = at91_adc_readl(st, AT91_SAMA5D2_ACR);
620 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK;
621 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK;
622 at91_adc_writel(st, AT91_SAMA5D2_ACR, acr);
623
624 /* Sample Period Time = (TRGPER + 1) / ADCClock */
625 st->touch_st.sample_period_val =
626 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US *
627 clk_khz / 1000) - 1, 1);
628 /* enable pen detect IRQ */
629 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
630
631 return 0;
632 }
633
at91_adc_touch_pos(struct at91_adc_state * st,int reg)634 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
635 {
636 u32 val;
637 u32 scale, result, pos;
638
639 /*
640 * to obtain the actual position we must divide by scale
641 * and multiply with max, where
642 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1
643 */
644 /* first half of register is the x or y, second half is the scale */
645 val = at91_adc_readl(st, reg);
646 if (!val)
647 dev_dbg(&st->indio_dev->dev, "pos is 0\n");
648
649 pos = val & AT91_SAMA5D2_XYZ_MASK;
650 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos;
651 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
652 if (scale == 0) {
653 dev_err(&st->indio_dev->dev, "scale is 0\n");
654 return 0;
655 }
656 result /= scale;
657
658 return result;
659 }
660
at91_adc_touch_x_pos(struct at91_adc_state * st)661 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
662 {
663 st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR);
664 return st->touch_st.x_pos;
665 }
666
at91_adc_touch_y_pos(struct at91_adc_state * st)667 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
668 {
669 return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR);
670 }
671
at91_adc_touch_pressure(struct at91_adc_state * st)672 static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
673 {
674 u32 val;
675 u32 z1, z2;
676 u32 pres;
677 u32 rxp = 1;
678 u32 factor = 1000;
679
680 /* calculate the pressure */
681 val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
682 z1 = val & AT91_SAMA5D2_XYZ_MASK;
683 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
684
685 if (z1 != 0)
686 pres = rxp * (st->touch_st.x_pos * factor / 1024) *
687 (z2 * factor / z1 - factor) /
688 factor;
689 else
690 pres = 0xFFFF; /* no pen contact */
691
692 /*
693 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0.
694 * We compute it this way, but let's return it in the expected way,
695 * growing from 0 to 0xFFFF.
696 */
697 return 0xFFFF - pres;
698 }
699
at91_adc_read_position(struct at91_adc_state * st,int chan,u16 * val)700 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
701 {
702 *val = 0;
703 if (!st->touch_st.touching)
704 return -ENODATA;
705 if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX)
706 *val = at91_adc_touch_x_pos(st);
707 else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX)
708 *val = at91_adc_touch_y_pos(st);
709 else
710 return -ENODATA;
711
712 return IIO_VAL_INT;
713 }
714
at91_adc_read_pressure(struct at91_adc_state * st,int chan,u16 * val)715 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
716 {
717 *val = 0;
718 if (!st->touch_st.touching)
719 return -ENODATA;
720 if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX)
721 *val = at91_adc_touch_pressure(st);
722 else
723 return -ENODATA;
724
725 return IIO_VAL_INT;
726 }
727
at91_adc_configure_trigger(struct iio_trigger * trig,bool state)728 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
729 {
730 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
731 struct at91_adc_state *st = iio_priv(indio);
732 u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
733
734 /* clear TRGMOD */
735 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
736
737 if (state)
738 status |= st->selected_trig->trgmod_value;
739
740 /* set/unset hw trigger */
741 at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
742
743 return 0;
744 }
745
at91_adc_reenable_trigger(struct iio_trigger * trig)746 static void at91_adc_reenable_trigger(struct iio_trigger *trig)
747 {
748 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
749 struct at91_adc_state *st = iio_priv(indio);
750
751 /* if we are using DMA, we must not reenable irq after each trigger */
752 if (st->dma_st.dma_chan)
753 return;
754
755 enable_irq(st->irq);
756
757 /* Needed to ACK the DRDY interruption */
758 at91_adc_readl(st, AT91_SAMA5D2_LCDR);
759 }
760
761 static const struct iio_trigger_ops at91_adc_trigger_ops = {
762 .set_trigger_state = &at91_adc_configure_trigger,
763 .reenable = &at91_adc_reenable_trigger,
764 .validate_device = iio_trigger_validate_own_device,
765 };
766
at91_adc_dma_size_done(struct at91_adc_state * st)767 static int at91_adc_dma_size_done(struct at91_adc_state *st)
768 {
769 struct dma_tx_state state;
770 enum dma_status status;
771 int i, size;
772
773 status = dmaengine_tx_status(st->dma_st.dma_chan,
774 st->dma_st.dma_chan->cookie,
775 &state);
776 if (status != DMA_IN_PROGRESS)
777 return 0;
778
779 /* Transferred length is size in bytes from end of buffer */
780 i = st->dma_st.rx_buf_sz - state.residue;
781
782 /* Return available bytes */
783 if (i >= st->dma_st.buf_idx)
784 size = i - st->dma_st.buf_idx;
785 else
786 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
787 return size;
788 }
789
at91_dma_buffer_done(void * data)790 static void at91_dma_buffer_done(void *data)
791 {
792 struct iio_dev *indio_dev = data;
793
794 iio_trigger_poll_chained(indio_dev->trig);
795 }
796
at91_adc_dma_start(struct iio_dev * indio_dev)797 static int at91_adc_dma_start(struct iio_dev *indio_dev)
798 {
799 struct at91_adc_state *st = iio_priv(indio_dev);
800 struct dma_async_tx_descriptor *desc;
801 dma_cookie_t cookie;
802 int ret;
803 u8 bit;
804
805 if (!st->dma_st.dma_chan)
806 return 0;
807
808 /* we start a new DMA, so set buffer index to start */
809 st->dma_st.buf_idx = 0;
810
811 /*
812 * compute buffer size w.r.t. watermark and enabled channels.
813 * scan_bytes is aligned so we need an exact size for DMA
814 */
815 st->dma_st.rx_buf_sz = 0;
816
817 for_each_set_bit(bit, indio_dev->active_scan_mask,
818 indio_dev->num_channels) {
819 struct iio_chan_spec const *chan =
820 at91_adc_chan_get(indio_dev, bit);
821
822 if (!chan)
823 continue;
824
825 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
826 }
827 st->dma_st.rx_buf_sz *= st->dma_st.watermark;
828
829 /* Prepare a DMA cyclic transaction */
830 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
831 st->dma_st.rx_dma_buf,
832 st->dma_st.rx_buf_sz,
833 st->dma_st.rx_buf_sz / 2,
834 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
835
836 if (!desc) {
837 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n");
838 return -EBUSY;
839 }
840
841 desc->callback = at91_dma_buffer_done;
842 desc->callback_param = indio_dev;
843
844 cookie = dmaengine_submit(desc);
845 ret = dma_submit_error(cookie);
846 if (ret) {
847 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n");
848 dmaengine_terminate_async(st->dma_st.dma_chan);
849 return ret;
850 }
851
852 /* enable general overrun error signaling */
853 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE);
854 /* Issue pending DMA requests */
855 dma_async_issue_pending(st->dma_st.dma_chan);
856
857 /* consider current time as DMA start time for timestamps */
858 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
859
860 dev_dbg(&indio_dev->dev, "DMA cyclic started\n");
861
862 return 0;
863 }
864
at91_adc_buffer_check_use_irq(struct iio_dev * indio,struct at91_adc_state * st)865 static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio,
866 struct at91_adc_state *st)
867 {
868 /* if using DMA, we do not use our own IRQ (we use DMA-controller) */
869 if (st->dma_st.dma_chan)
870 return false;
871 /* if the trigger is not ours, then it has its own IRQ */
872 if (iio_trigger_validate_own_device(indio->trig, indio))
873 return false;
874 return true;
875 }
876
at91_adc_current_chan_is_touch(struct iio_dev * indio_dev)877 static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev)
878 {
879 struct at91_adc_state *st = iio_priv(indio_dev);
880
881 return !!bitmap_subset(indio_dev->active_scan_mask,
882 &st->touch_st.channels_bitmask,
883 AT91_SAMA5D2_MAX_CHAN_IDX + 1);
884 }
885
at91_adc_buffer_prepare(struct iio_dev * indio_dev)886 static int at91_adc_buffer_prepare(struct iio_dev *indio_dev)
887 {
888 int ret;
889 u8 bit;
890 struct at91_adc_state *st = iio_priv(indio_dev);
891
892 /* check if we are enabling triggered buffer or the touchscreen */
893 if (at91_adc_current_chan_is_touch(indio_dev))
894 return at91_adc_configure_touch(st, true);
895
896 /* if we are not in triggered mode, we cannot enable the buffer. */
897 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
898 return -EINVAL;
899
900 /* we continue with the triggered buffer */
901 ret = at91_adc_dma_start(indio_dev);
902 if (ret) {
903 dev_err(&indio_dev->dev, "buffer prepare failed\n");
904 return ret;
905 }
906
907 for_each_set_bit(bit, indio_dev->active_scan_mask,
908 indio_dev->num_channels) {
909 struct iio_chan_spec const *chan =
910 at91_adc_chan_get(indio_dev, bit);
911 u32 cor;
912
913 if (!chan)
914 continue;
915 /* these channel types cannot be handled by this trigger */
916 if (chan->type == IIO_POSITIONRELATIVE ||
917 chan->type == IIO_PRESSURE)
918 continue;
919
920 cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
921
922 if (chan->differential)
923 cor |= (BIT(chan->channel) | BIT(chan->channel2)) <<
924 AT91_SAMA5D2_COR_DIFF_OFFSET;
925 else
926 cor &= ~(BIT(chan->channel) <<
927 AT91_SAMA5D2_COR_DIFF_OFFSET);
928
929 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
930
931 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
932 }
933
934 if (at91_adc_buffer_check_use_irq(indio_dev, st))
935 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY);
936
937 return 0;
938 }
939
at91_adc_buffer_postdisable(struct iio_dev * indio_dev)940 static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev)
941 {
942 struct at91_adc_state *st = iio_priv(indio_dev);
943 u8 bit;
944
945 /* check if we are disabling triggered buffer or the touchscreen */
946 if (at91_adc_current_chan_is_touch(indio_dev))
947 return at91_adc_configure_touch(st, false);
948
949 /* if we are not in triggered mode, nothing to do here */
950 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
951 return -EINVAL;
952
953 /*
954 * For each enable channel we must disable it in hardware.
955 * In the case of DMA, we must read the last converted value
956 * to clear EOC status and not get a possible interrupt later.
957 * This value is being read by DMA from LCDR anyway, so it's not lost.
958 */
959 for_each_set_bit(bit, indio_dev->active_scan_mask,
960 indio_dev->num_channels) {
961 struct iio_chan_spec const *chan =
962 at91_adc_chan_get(indio_dev, bit);
963
964 if (!chan)
965 continue;
966 /* these channel types are virtual, no need to do anything */
967 if (chan->type == IIO_POSITIONRELATIVE ||
968 chan->type == IIO_PRESSURE)
969 continue;
970
971 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
972
973 if (st->dma_st.dma_chan)
974 at91_adc_readl(st, chan->address);
975 }
976
977 if (at91_adc_buffer_check_use_irq(indio_dev, st))
978 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY);
979
980 /* read overflow register to clear possible overflow status */
981 at91_adc_readl(st, AT91_SAMA5D2_OVER);
982
983 /* if we are using DMA we must clear registers and end DMA */
984 if (st->dma_st.dma_chan)
985 dmaengine_terminate_sync(st->dma_st.dma_chan);
986
987 return 0;
988 }
989
990 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = {
991 .postdisable = &at91_adc_buffer_postdisable,
992 };
993
at91_adc_allocate_trigger(struct iio_dev * indio,char * trigger_name)994 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
995 char *trigger_name)
996 {
997 struct iio_trigger *trig;
998 int ret;
999
1000 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
1001 iio_device_id(indio), trigger_name);
1002 if (!trig)
1003 return NULL;
1004
1005 trig->dev.parent = indio->dev.parent;
1006 iio_trigger_set_drvdata(trig, indio);
1007 trig->ops = &at91_adc_trigger_ops;
1008
1009 ret = devm_iio_trigger_register(&indio->dev, trig);
1010 if (ret)
1011 return ERR_PTR(ret);
1012
1013 return trig;
1014 }
at91_adc_trigger_handler_nodma(struct iio_dev * indio_dev,struct iio_poll_func * pf)1015 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
1016 struct iio_poll_func *pf)
1017 {
1018 struct at91_adc_state *st = iio_priv(indio_dev);
1019 int i = 0;
1020 int val;
1021 u8 bit;
1022 u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev);
1023 unsigned int timeout = 50;
1024
1025 /*
1026 * Check if the conversion is ready. If not, wait a little bit, and
1027 * in case of timeout exit with an error.
1028 */
1029 while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask &&
1030 timeout) {
1031 usleep_range(50, 100);
1032 timeout--;
1033 }
1034
1035 /* Cannot read data, not ready. Continue without reporting data */
1036 if (!timeout)
1037 return;
1038
1039 for_each_set_bit(bit, indio_dev->active_scan_mask,
1040 indio_dev->num_channels) {
1041 struct iio_chan_spec const *chan =
1042 at91_adc_chan_get(indio_dev, bit);
1043
1044 if (!chan)
1045 continue;
1046 /*
1047 * Our external trigger only supports the voltage channels.
1048 * In case someone requested a different type of channel
1049 * just put zeroes to buffer.
1050 * This should not happen because we check the scan mode
1051 * and scan mask when we enable the buffer, and we don't allow
1052 * the buffer to start with a mixed mask (voltage and something
1053 * else).
1054 * Thus, emit a warning.
1055 */
1056 if (chan->type == IIO_VOLTAGE) {
1057 val = at91_adc_readl(st, chan->address);
1058 at91_adc_adjust_val_osr(st, &val);
1059 st->buffer[i] = val;
1060 } else {
1061 st->buffer[i] = 0;
1062 WARN(true, "This trigger cannot handle this type of channel");
1063 }
1064 i++;
1065 }
1066 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
1067 pf->timestamp);
1068 }
1069
at91_adc_trigger_handler_dma(struct iio_dev * indio_dev)1070 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev)
1071 {
1072 struct at91_adc_state *st = iio_priv(indio_dev);
1073 int transferred_len = at91_adc_dma_size_done(st);
1074 s64 ns = iio_get_time_ns(indio_dev);
1075 s64 interval;
1076 int sample_index = 0, sample_count, sample_size;
1077
1078 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
1079 /* if we reached this point, we cannot sample faster */
1080 if (status & AT91_SAMA5D2_IER_GOVRE)
1081 pr_info_ratelimited("%s: conversion overrun detected\n",
1082 indio_dev->name);
1083
1084 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
1085
1086 sample_count = div_s64(transferred_len, sample_size);
1087
1088 /*
1089 * interval between samples is total time since last transfer handling
1090 * divided by the number of samples (total size divided by sample size)
1091 */
1092 interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
1093
1094 while (transferred_len >= sample_size) {
1095 /*
1096 * for all the values in the current sample,
1097 * adjust the values inside the buffer for oversampling
1098 */
1099 at91_adc_adjust_val_osr_array(st,
1100 &st->dma_st.rx_buf[st->dma_st.buf_idx],
1101 sample_size);
1102
1103 iio_push_to_buffers_with_timestamp(indio_dev,
1104 (st->dma_st.rx_buf + st->dma_st.buf_idx),
1105 (st->dma_st.dma_ts + interval * sample_index));
1106 /* adjust remaining length */
1107 transferred_len -= sample_size;
1108 /* adjust buffer index */
1109 st->dma_st.buf_idx += sample_size;
1110 /* in case of reaching end of buffer, reset index */
1111 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
1112 st->dma_st.buf_idx = 0;
1113 sample_index++;
1114 }
1115 /* adjust saved time for next transfer handling */
1116 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1117 }
1118
at91_adc_trigger_handler(int irq,void * p)1119 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
1120 {
1121 struct iio_poll_func *pf = p;
1122 struct iio_dev *indio_dev = pf->indio_dev;
1123 struct at91_adc_state *st = iio_priv(indio_dev);
1124
1125 /*
1126 * If it's not our trigger, start a conversion now, as we are
1127 * actually polling the trigger now.
1128 */
1129 if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
1130 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
1131
1132 if (st->dma_st.dma_chan)
1133 at91_adc_trigger_handler_dma(indio_dev);
1134 else
1135 at91_adc_trigger_handler_nodma(indio_dev, pf);
1136
1137 iio_trigger_notify_done(indio_dev->trig);
1138
1139 return IRQ_HANDLED;
1140 }
1141
at91_adc_startup_time(unsigned startup_time_min,unsigned adc_clk_khz)1142 static unsigned at91_adc_startup_time(unsigned startup_time_min,
1143 unsigned adc_clk_khz)
1144 {
1145 static const unsigned int startup_lookup[] = {
1146 0, 8, 16, 24,
1147 64, 80, 96, 112,
1148 512, 576, 640, 704,
1149 768, 832, 896, 960
1150 };
1151 unsigned ticks_min, i;
1152
1153 /*
1154 * Since the adc frequency is checked before, there is no reason
1155 * to not meet the startup time constraint.
1156 */
1157
1158 ticks_min = startup_time_min * adc_clk_khz / 1000;
1159 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
1160 if (startup_lookup[i] > ticks_min)
1161 break;
1162
1163 return i;
1164 }
1165
at91_adc_setup_samp_freq(struct iio_dev * indio_dev,unsigned freq)1166 static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq)
1167 {
1168 struct at91_adc_state *st = iio_priv(indio_dev);
1169 unsigned f_per, prescal, startup, mr;
1170
1171 f_per = clk_get_rate(st->per_clk);
1172 prescal = (f_per / (2 * freq)) - 1;
1173
1174 startup = at91_adc_startup_time(st->soc_info.startup_time,
1175 freq / 1000);
1176
1177 mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
1178 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
1179 mr |= AT91_SAMA5D2_MR_STARTUP(startup);
1180 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
1181 at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
1182
1183 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
1184 freq, startup, prescal);
1185 st->current_sample_rate = freq;
1186 }
1187
at91_adc_get_sample_freq(struct at91_adc_state * st)1188 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
1189 {
1190 return st->current_sample_rate;
1191 }
1192
at91_adc_touch_data_handler(struct iio_dev * indio_dev)1193 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev)
1194 {
1195 struct at91_adc_state *st = iio_priv(indio_dev);
1196 u8 bit;
1197 u16 val;
1198 int i = 0;
1199
1200 for_each_set_bit(bit, indio_dev->active_scan_mask,
1201 AT91_SAMA5D2_MAX_CHAN_IDX + 1) {
1202 struct iio_chan_spec const *chan =
1203 at91_adc_chan_get(indio_dev, bit);
1204
1205 if (chan->type == IIO_POSITIONRELATIVE)
1206 at91_adc_read_position(st, chan->channel, &val);
1207 else if (chan->type == IIO_PRESSURE)
1208 at91_adc_read_pressure(st, chan->channel, &val);
1209 else
1210 continue;
1211 st->buffer[i] = val;
1212 i++;
1213 }
1214 /*
1215 * Schedule work to push to buffers.
1216 * This is intended to push to the callback buffer that another driver
1217 * registered. We are still in a handler from our IRQ. If we push
1218 * directly, it means the other driver has it's callback called
1219 * from our IRQ context. Which is something we better avoid.
1220 * Let's schedule it after our IRQ is completed.
1221 */
1222 schedule_work(&st->touch_st.workq);
1223 }
1224
at91_adc_pen_detect_interrupt(struct at91_adc_state * st)1225 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
1226 {
1227 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN);
1228 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN |
1229 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1230 AT91_SAMA5D2_IER_PRDY);
1231 at91_adc_writel(st, AT91_SAMA5D2_TRGR,
1232 AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
1233 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
1234 st->touch_st.touching = true;
1235 }
1236
at91_adc_no_pen_detect_interrupt(struct iio_dev * indio_dev)1237 static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev)
1238 {
1239 struct at91_adc_state *st = iio_priv(indio_dev);
1240
1241 at91_adc_writel(st, AT91_SAMA5D2_TRGR,
1242 AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
1243 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN |
1244 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1245 AT91_SAMA5D2_IER_PRDY);
1246 st->touch_st.touching = false;
1247
1248 at91_adc_touch_data_handler(indio_dev);
1249
1250 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
1251 }
1252
at91_adc_workq_handler(struct work_struct * workq)1253 static void at91_adc_workq_handler(struct work_struct *workq)
1254 {
1255 struct at91_adc_touch *touch_st = container_of(workq,
1256 struct at91_adc_touch, workq);
1257 struct at91_adc_state *st = container_of(touch_st,
1258 struct at91_adc_state, touch_st);
1259 struct iio_dev *indio_dev = st->indio_dev;
1260
1261 iio_push_to_buffers(indio_dev, st->buffer);
1262 }
1263
at91_adc_interrupt(int irq,void * private)1264 static irqreturn_t at91_adc_interrupt(int irq, void *private)
1265 {
1266 struct iio_dev *indio = private;
1267 struct at91_adc_state *st = iio_priv(indio);
1268 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
1269 u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
1270 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1271 AT91_SAMA5D2_IER_PRDY;
1272
1273 if (!(status & imr))
1274 return IRQ_NONE;
1275 if (status & AT91_SAMA5D2_IER_PEN) {
1276 /* pen detected IRQ */
1277 at91_adc_pen_detect_interrupt(st);
1278 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) {
1279 /* nopen detected IRQ */
1280 at91_adc_no_pen_detect_interrupt(indio);
1281 } else if ((status & AT91_SAMA5D2_ISR_PENS) &&
1282 ((status & rdy_mask) == rdy_mask)) {
1283 /* periodic trigger IRQ - during pen sense */
1284 at91_adc_touch_data_handler(indio);
1285 } else if (status & AT91_SAMA5D2_ISR_PENS) {
1286 /*
1287 * touching, but the measurements are not ready yet.
1288 * read and ignore.
1289 */
1290 status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR);
1291 status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR);
1292 status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
1293 } else if (iio_buffer_enabled(indio) &&
1294 (status & AT91_SAMA5D2_IER_DRDY)) {
1295 /* triggered buffer without DMA */
1296 disable_irq_nosync(irq);
1297 iio_trigger_poll(indio->trig);
1298 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
1299 /* triggered buffer with DMA - should not happen */
1300 disable_irq_nosync(irq);
1301 WARN(true, "Unexpected irq occurred\n");
1302 } else if (!iio_buffer_enabled(indio)) {
1303 /* software requested conversion */
1304 st->conversion_value = at91_adc_readl(st, st->chan->address);
1305 st->conversion_done = true;
1306 wake_up_interruptible(&st->wq_data_available);
1307 }
1308 return IRQ_HANDLED;
1309 }
1310
at91_adc_read_info_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)1311 static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
1312 struct iio_chan_spec const *chan, int *val)
1313 {
1314 struct at91_adc_state *st = iio_priv(indio_dev);
1315 u32 cor = 0;
1316 u16 tmp_val;
1317 int ret;
1318
1319 /*
1320 * Keep in mind that we cannot use software trigger or touchscreen
1321 * if external trigger is enabled
1322 */
1323 if (chan->type == IIO_POSITIONRELATIVE) {
1324 ret = iio_device_claim_direct_mode(indio_dev);
1325 if (ret)
1326 return ret;
1327 mutex_lock(&st->lock);
1328
1329 ret = at91_adc_read_position(st, chan->channel,
1330 &tmp_val);
1331 *val = tmp_val;
1332 mutex_unlock(&st->lock);
1333 iio_device_release_direct_mode(indio_dev);
1334
1335 return at91_adc_adjust_val_osr(st, val);
1336 }
1337 if (chan->type == IIO_PRESSURE) {
1338 ret = iio_device_claim_direct_mode(indio_dev);
1339 if (ret)
1340 return ret;
1341 mutex_lock(&st->lock);
1342
1343 ret = at91_adc_read_pressure(st, chan->channel,
1344 &tmp_val);
1345 *val = tmp_val;
1346 mutex_unlock(&st->lock);
1347 iio_device_release_direct_mode(indio_dev);
1348
1349 return at91_adc_adjust_val_osr(st, val);
1350 }
1351
1352 /* in this case we have a voltage channel */
1353
1354 ret = iio_device_claim_direct_mode(indio_dev);
1355 if (ret)
1356 return ret;
1357 mutex_lock(&st->lock);
1358
1359 st->chan = chan;
1360
1361 if (chan->differential)
1362 cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
1363 AT91_SAMA5D2_COR_DIFF_OFFSET;
1364
1365 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
1366 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
1367 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
1368 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
1369
1370 ret = wait_event_interruptible_timeout(st->wq_data_available,
1371 st->conversion_done,
1372 msecs_to_jiffies(1000));
1373 if (ret == 0)
1374 ret = -ETIMEDOUT;
1375
1376 if (ret > 0) {
1377 *val = st->conversion_value;
1378 ret = at91_adc_adjust_val_osr(st, val);
1379 if (chan->scan_type.sign == 's')
1380 *val = sign_extend32(*val, 11);
1381 st->conversion_done = false;
1382 }
1383
1384 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
1385 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
1386
1387 /* Needed to ACK the DRDY interruption */
1388 at91_adc_readl(st, AT91_SAMA5D2_LCDR);
1389
1390 mutex_unlock(&st->lock);
1391
1392 iio_device_release_direct_mode(indio_dev);
1393 return ret;
1394 }
1395
at91_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)1396 static int at91_adc_read_raw(struct iio_dev *indio_dev,
1397 struct iio_chan_spec const *chan,
1398 int *val, int *val2, long mask)
1399 {
1400 struct at91_adc_state *st = iio_priv(indio_dev);
1401
1402 switch (mask) {
1403 case IIO_CHAN_INFO_RAW:
1404 return at91_adc_read_info_raw(indio_dev, chan, val);
1405 case IIO_CHAN_INFO_SCALE:
1406 *val = st->vref_uv / 1000;
1407 if (chan->differential)
1408 *val *= 2;
1409 *val2 = chan->scan_type.realbits;
1410 return IIO_VAL_FRACTIONAL_LOG2;
1411
1412 case IIO_CHAN_INFO_SAMP_FREQ:
1413 *val = at91_adc_get_sample_freq(st);
1414 return IIO_VAL_INT;
1415
1416 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1417 *val = st->oversampling_ratio;
1418 return IIO_VAL_INT;
1419
1420 default:
1421 return -EINVAL;
1422 }
1423 }
1424
at91_adc_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1425 static int at91_adc_write_raw(struct iio_dev *indio_dev,
1426 struct iio_chan_spec const *chan,
1427 int val, int val2, long mask)
1428 {
1429 struct at91_adc_state *st = iio_priv(indio_dev);
1430
1431 switch (mask) {
1432 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1433 if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) &&
1434 (val != AT91_OSR_16SAMPLES))
1435 return -EINVAL;
1436 /* if no change, optimize out */
1437 if (val == st->oversampling_ratio)
1438 return 0;
1439 st->oversampling_ratio = val;
1440 /* update ratio */
1441 at91_adc_config_emr(st);
1442 return 0;
1443 case IIO_CHAN_INFO_SAMP_FREQ:
1444 if (val < st->soc_info.min_sample_rate ||
1445 val > st->soc_info.max_sample_rate)
1446 return -EINVAL;
1447
1448 at91_adc_setup_samp_freq(indio_dev, val);
1449 return 0;
1450 default:
1451 return -EINVAL;
1452 }
1453 }
1454
at91_adc_dma_init(struct platform_device * pdev)1455 static void at91_adc_dma_init(struct platform_device *pdev)
1456 {
1457 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1458 struct at91_adc_state *st = iio_priv(indio_dev);
1459 struct dma_slave_config config = {0};
1460 /*
1461 * We make the buffer double the size of the fifo,
1462 * such that DMA uses one half of the buffer (full fifo size)
1463 * and the software uses the other half to read/write.
1464 */
1465 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1466 AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
1467 PAGE_SIZE);
1468
1469 if (st->dma_st.dma_chan)
1470 return;
1471
1472 st->dma_st.dma_chan = dma_request_chan(&pdev->dev, "rx");
1473 if (IS_ERR(st->dma_st.dma_chan)) {
1474 dev_info(&pdev->dev, "can't get DMA channel\n");
1475 st->dma_st.dma_chan = NULL;
1476 goto dma_exit;
1477 }
1478
1479 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
1480 pages * PAGE_SIZE,
1481 &st->dma_st.rx_dma_buf,
1482 GFP_KERNEL);
1483 if (!st->dma_st.rx_buf) {
1484 dev_info(&pdev->dev, "can't allocate coherent DMA area\n");
1485 goto dma_chan_disable;
1486 }
1487
1488 /* Configure DMA channel to read data register */
1489 config.direction = DMA_DEV_TO_MEM;
1490 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
1491 + AT91_SAMA5D2_LCDR);
1492 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1493 config.src_maxburst = 1;
1494 config.dst_maxburst = 1;
1495
1496 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
1497 dev_info(&pdev->dev, "can't configure DMA slave\n");
1498 goto dma_free_area;
1499 }
1500
1501 dev_info(&pdev->dev, "using %s for rx DMA transfers\n",
1502 dma_chan_name(st->dma_st.dma_chan));
1503
1504 return;
1505
1506 dma_free_area:
1507 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1508 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1509 dma_chan_disable:
1510 dma_release_channel(st->dma_st.dma_chan);
1511 st->dma_st.dma_chan = NULL;
1512 dma_exit:
1513 dev_info(&pdev->dev, "continuing without DMA support\n");
1514 }
1515
at91_adc_dma_disable(struct platform_device * pdev)1516 static void at91_adc_dma_disable(struct platform_device *pdev)
1517 {
1518 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1519 struct at91_adc_state *st = iio_priv(indio_dev);
1520 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1521 AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
1522 PAGE_SIZE);
1523
1524 /* if we are not using DMA, just return */
1525 if (!st->dma_st.dma_chan)
1526 return;
1527
1528 /* wait for all transactions to be terminated first*/
1529 dmaengine_terminate_sync(st->dma_st.dma_chan);
1530
1531 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1532 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1533 dma_release_channel(st->dma_st.dma_chan);
1534 st->dma_st.dma_chan = NULL;
1535
1536 dev_info(&pdev->dev, "continuing without DMA support\n");
1537 }
1538
at91_adc_set_watermark(struct iio_dev * indio_dev,unsigned int val)1539 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1540 {
1541 struct at91_adc_state *st = iio_priv(indio_dev);
1542 int ret;
1543
1544 if (val > AT91_HWFIFO_MAX_SIZE)
1545 return -EINVAL;
1546
1547 if (!st->selected_trig->hw_trig) {
1548 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n");
1549 return 0;
1550 }
1551
1552 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val);
1553 st->dma_st.watermark = val;
1554
1555 /*
1556 * The logic here is: if we have watermark 1, it means we do
1557 * each conversion with it's own IRQ, thus we don't need DMA.
1558 * If the watermark is higher, we do DMA to do all the transfers in bulk
1559 */
1560
1561 if (val == 1)
1562 at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
1563 else if (val > 1)
1564 at91_adc_dma_init(to_platform_device(&indio_dev->dev));
1565
1566 /*
1567 * We can start the DMA only after setting the watermark and
1568 * having the DMA initialization completed
1569 */
1570 ret = at91_adc_buffer_prepare(indio_dev);
1571 if (ret)
1572 at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
1573
1574 return ret;
1575 }
1576
at91_adc_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)1577 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev,
1578 const unsigned long *scan_mask)
1579 {
1580 struct at91_adc_state *st = iio_priv(indio_dev);
1581
1582 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
1583 AT91_SAMA5D2_MAX_CHAN_IDX + 1))
1584 return 0;
1585 /*
1586 * if the new bitmap is a combination of touchscreen and regular
1587 * channels, then we are not fine
1588 */
1589 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
1590 AT91_SAMA5D2_MAX_CHAN_IDX + 1))
1591 return -EINVAL;
1592 return 0;
1593 }
1594
at91_adc_hw_init(struct iio_dev * indio_dev)1595 static void at91_adc_hw_init(struct iio_dev *indio_dev)
1596 {
1597 struct at91_adc_state *st = iio_priv(indio_dev);
1598
1599 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
1600 at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
1601 /*
1602 * Transfer field must be set to 2 according to the datasheet and
1603 * allows different analog settings for each channel.
1604 */
1605 at91_adc_writel(st, AT91_SAMA5D2_MR,
1606 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
1607
1608 at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate);
1609
1610 /* configure extended mode register */
1611 at91_adc_config_emr(st);
1612 }
1613
at91_adc_get_fifo_state(struct device * dev,struct device_attribute * attr,char * buf)1614 static ssize_t at91_adc_get_fifo_state(struct device *dev,
1615 struct device_attribute *attr, char *buf)
1616 {
1617 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1618 struct at91_adc_state *st = iio_priv(indio_dev);
1619
1620 return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan);
1621 }
1622
at91_adc_get_watermark(struct device * dev,struct device_attribute * attr,char * buf)1623 static ssize_t at91_adc_get_watermark(struct device *dev,
1624 struct device_attribute *attr, char *buf)
1625 {
1626 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1627 struct at91_adc_state *st = iio_priv(indio_dev);
1628
1629 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark);
1630 }
1631
1632 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1633 at91_adc_get_fifo_state, NULL, 0);
1634 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1635 at91_adc_get_watermark, NULL, 0);
1636
1637 static IIO_CONST_ATTR(hwfifo_watermark_min, "2");
1638 static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
1639
1640 static IIO_CONST_ATTR(oversampling_ratio_available,
1641 __stringify(AT91_OSR_1SAMPLES) " "
1642 __stringify(AT91_OSR_4SAMPLES) " "
1643 __stringify(AT91_OSR_16SAMPLES));
1644
1645 static struct attribute *at91_adc_attributes[] = {
1646 &iio_const_attr_oversampling_ratio_available.dev_attr.attr,
1647 NULL,
1648 };
1649
1650 static const struct attribute_group at91_adc_attribute_group = {
1651 .attrs = at91_adc_attributes,
1652 };
1653
1654 static const struct attribute *at91_adc_fifo_attributes[] = {
1655 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
1656 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
1657 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
1658 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
1659 NULL,
1660 };
1661
1662 static const struct iio_info at91_adc_info = {
1663 .attrs = &at91_adc_attribute_group,
1664 .read_raw = &at91_adc_read_raw,
1665 .write_raw = &at91_adc_write_raw,
1666 .update_scan_mode = &at91_adc_update_scan_mode,
1667 .of_xlate = &at91_adc_of_xlate,
1668 .hwfifo_set_watermark = &at91_adc_set_watermark,
1669 };
1670
at91_adc_buffer_and_trigger_init(struct device * dev,struct iio_dev * indio)1671 static int at91_adc_buffer_and_trigger_init(struct device *dev,
1672 struct iio_dev *indio)
1673 {
1674 struct at91_adc_state *st = iio_priv(indio);
1675 const struct attribute **fifo_attrs;
1676 int ret;
1677
1678 if (st->selected_trig->hw_trig)
1679 fifo_attrs = at91_adc_fifo_attributes;
1680 else
1681 fifo_attrs = NULL;
1682
1683 ret = devm_iio_triggered_buffer_setup_ext(&indio->dev, indio,
1684 &iio_pollfunc_store_time,
1685 &at91_adc_trigger_handler, &at91_buffer_setup_ops, fifo_attrs);
1686 if (ret < 0) {
1687 dev_err(dev, "couldn't initialize the buffer.\n");
1688 return ret;
1689 }
1690
1691 if (!st->selected_trig->hw_trig)
1692 return 0;
1693
1694 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
1695 if (IS_ERR(st->trig)) {
1696 dev_err(dev, "could not allocate trigger\n");
1697 return PTR_ERR(st->trig);
1698 }
1699
1700 /*
1701 * Initially the iio buffer has a length of 2 and
1702 * a watermark of 1
1703 */
1704 st->dma_st.watermark = 1;
1705
1706 return 0;
1707 }
1708
at91_adc_probe(struct platform_device * pdev)1709 static int at91_adc_probe(struct platform_device *pdev)
1710 {
1711 struct iio_dev *indio_dev;
1712 struct at91_adc_state *st;
1713 struct resource *res;
1714 int ret, i;
1715 u32 edge_type = IRQ_TYPE_NONE;
1716
1717 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
1718 if (!indio_dev)
1719 return -ENOMEM;
1720
1721 indio_dev->name = dev_name(&pdev->dev);
1722 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1723 indio_dev->info = &at91_adc_info;
1724 indio_dev->channels = at91_adc_channels;
1725 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
1726
1727 st = iio_priv(indio_dev);
1728 st->indio_dev = indio_dev;
1729
1730 bitmap_set(&st->touch_st.channels_bitmask,
1731 AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1);
1732 bitmap_set(&st->touch_st.channels_bitmask,
1733 AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1);
1734 bitmap_set(&st->touch_st.channels_bitmask,
1735 AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1);
1736
1737 st->oversampling_ratio = AT91_OSR_1SAMPLES;
1738
1739 ret = of_property_read_u32(pdev->dev.of_node,
1740 "atmel,min-sample-rate-hz",
1741 &st->soc_info.min_sample_rate);
1742 if (ret) {
1743 dev_err(&pdev->dev,
1744 "invalid or missing value for atmel,min-sample-rate-hz\n");
1745 return ret;
1746 }
1747
1748 ret = of_property_read_u32(pdev->dev.of_node,
1749 "atmel,max-sample-rate-hz",
1750 &st->soc_info.max_sample_rate);
1751 if (ret) {
1752 dev_err(&pdev->dev,
1753 "invalid or missing value for atmel,max-sample-rate-hz\n");
1754 return ret;
1755 }
1756
1757 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
1758 &st->soc_info.startup_time);
1759 if (ret) {
1760 dev_err(&pdev->dev,
1761 "invalid or missing value for atmel,startup-time-ms\n");
1762 return ret;
1763 }
1764
1765 ret = of_property_read_u32(pdev->dev.of_node,
1766 "atmel,trigger-edge-type", &edge_type);
1767 if (ret) {
1768 dev_dbg(&pdev->dev,
1769 "atmel,trigger-edge-type not specified, only software trigger available\n");
1770 }
1771
1772 st->selected_trig = NULL;
1773
1774 /* find the right trigger, or no trigger at all */
1775 for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++)
1776 if (at91_adc_trigger_list[i].edge_type == edge_type) {
1777 st->selected_trig = &at91_adc_trigger_list[i];
1778 break;
1779 }
1780
1781 if (!st->selected_trig) {
1782 dev_err(&pdev->dev, "invalid external trigger edge value\n");
1783 return -EINVAL;
1784 }
1785
1786 init_waitqueue_head(&st->wq_data_available);
1787 mutex_init(&st->lock);
1788 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
1789
1790 st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1791 if (IS_ERR(st->base))
1792 return PTR_ERR(st->base);
1793
1794 /* if we plan to use DMA, we need the physical address of the regs */
1795 st->dma_st.phys_addr = res->start;
1796
1797 st->irq = platform_get_irq(pdev, 0);
1798 if (st->irq <= 0) {
1799 if (!st->irq)
1800 st->irq = -ENXIO;
1801
1802 return st->irq;
1803 }
1804
1805 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
1806 if (IS_ERR(st->per_clk))
1807 return PTR_ERR(st->per_clk);
1808
1809 st->reg = devm_regulator_get(&pdev->dev, "vddana");
1810 if (IS_ERR(st->reg))
1811 return PTR_ERR(st->reg);
1812
1813 st->vref = devm_regulator_get(&pdev->dev, "vref");
1814 if (IS_ERR(st->vref))
1815 return PTR_ERR(st->vref);
1816
1817 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
1818 pdev->dev.driver->name, indio_dev);
1819 if (ret)
1820 return ret;
1821
1822 ret = regulator_enable(st->reg);
1823 if (ret)
1824 return ret;
1825
1826 ret = regulator_enable(st->vref);
1827 if (ret)
1828 goto reg_disable;
1829
1830 st->vref_uv = regulator_get_voltage(st->vref);
1831 if (st->vref_uv <= 0) {
1832 ret = -EINVAL;
1833 goto vref_disable;
1834 }
1835
1836 at91_adc_hw_init(indio_dev);
1837
1838 ret = clk_prepare_enable(st->per_clk);
1839 if (ret)
1840 goto vref_disable;
1841
1842 platform_set_drvdata(pdev, indio_dev);
1843
1844 ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev);
1845 if (ret < 0)
1846 goto per_clk_disable_unprepare;
1847
1848 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32)))
1849 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n");
1850
1851 ret = iio_device_register(indio_dev);
1852 if (ret < 0)
1853 goto dma_disable;
1854
1855 if (st->selected_trig->hw_trig)
1856 dev_info(&pdev->dev, "setting up trigger as %s\n",
1857 st->selected_trig->name);
1858
1859 dev_info(&pdev->dev, "version: %x\n",
1860 readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
1861
1862 return 0;
1863
1864 dma_disable:
1865 at91_adc_dma_disable(pdev);
1866 per_clk_disable_unprepare:
1867 clk_disable_unprepare(st->per_clk);
1868 vref_disable:
1869 regulator_disable(st->vref);
1870 reg_disable:
1871 regulator_disable(st->reg);
1872 return ret;
1873 }
1874
at91_adc_remove(struct platform_device * pdev)1875 static int at91_adc_remove(struct platform_device *pdev)
1876 {
1877 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1878 struct at91_adc_state *st = iio_priv(indio_dev);
1879
1880 iio_device_unregister(indio_dev);
1881
1882 at91_adc_dma_disable(pdev);
1883
1884 clk_disable_unprepare(st->per_clk);
1885
1886 regulator_disable(st->vref);
1887 regulator_disable(st->reg);
1888
1889 return 0;
1890 }
1891
at91_adc_suspend(struct device * dev)1892 static __maybe_unused int at91_adc_suspend(struct device *dev)
1893 {
1894 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1895 struct at91_adc_state *st = iio_priv(indio_dev);
1896
1897 /*
1898 * Do a sofware reset of the ADC before we go to suspend.
1899 * this will ensure that all pins are free from being muxed by the ADC
1900 * and can be used by for other devices.
1901 * Otherwise, ADC will hog them and we can't go to suspend mode.
1902 */
1903 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
1904
1905 clk_disable_unprepare(st->per_clk);
1906 regulator_disable(st->vref);
1907 regulator_disable(st->reg);
1908
1909 return pinctrl_pm_select_sleep_state(dev);
1910 }
1911
at91_adc_resume(struct device * dev)1912 static __maybe_unused int at91_adc_resume(struct device *dev)
1913 {
1914 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1915 struct at91_adc_state *st = iio_priv(indio_dev);
1916 int ret;
1917
1918 ret = pinctrl_pm_select_default_state(dev);
1919 if (ret)
1920 goto resume_failed;
1921
1922 ret = regulator_enable(st->reg);
1923 if (ret)
1924 goto resume_failed;
1925
1926 ret = regulator_enable(st->vref);
1927 if (ret)
1928 goto reg_disable_resume;
1929
1930 ret = clk_prepare_enable(st->per_clk);
1931 if (ret)
1932 goto vref_disable_resume;
1933
1934 at91_adc_hw_init(indio_dev);
1935
1936 /* reconfiguring trigger hardware state */
1937 if (!iio_buffer_enabled(indio_dev))
1938 return 0;
1939
1940 /* check if we are enabling triggered buffer or the touchscreen */
1941 if (at91_adc_current_chan_is_touch(indio_dev))
1942 return at91_adc_configure_touch(st, true);
1943 else
1944 return at91_adc_configure_trigger(st->trig, true);
1945
1946 /* not needed but more explicit */
1947 return 0;
1948
1949 vref_disable_resume:
1950 regulator_disable(st->vref);
1951 reg_disable_resume:
1952 regulator_disable(st->reg);
1953 resume_failed:
1954 dev_err(&indio_dev->dev, "failed to resume\n");
1955 return ret;
1956 }
1957
1958 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1959
1960 static const struct of_device_id at91_adc_dt_match[] = {
1961 {
1962 .compatible = "atmel,sama5d2-adc",
1963 }, {
1964 /* sentinel */
1965 }
1966 };
1967 MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
1968
1969 static struct platform_driver at91_adc_driver = {
1970 .probe = at91_adc_probe,
1971 .remove = at91_adc_remove,
1972 .driver = {
1973 .name = "at91-sama5d2_adc",
1974 .of_match_table = at91_adc_dt_match,
1975 .pm = &at91_adc_pm_ops,
1976 },
1977 };
1978 module_platform_driver(at91_adc_driver)
1979
1980 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1981 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
1982 MODULE_LICENSE("GPL v2");
1983
