1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "core_types.h"
29
30 #include "reg_helper.h"
31 #include "dcn10_dpp.h"
32 #include "basics/conversion.h"
33
34
35 #define NUM_PHASES 64
36 #define HORZ_MAX_TAPS 8
37 #define VERT_MAX_TAPS 8
38
39 #define BLACK_OFFSET_RGB_Y 0x0
40 #define BLACK_OFFSET_CBCR 0x8000
41
42 #define REG(reg)\
43 dpp->tf_regs->reg
44
45 #define CTX \
46 dpp->base.ctx
47
48 #undef FN
49 #define FN(reg_name, field_name) \
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51
52 enum dcn10_coef_filter_type_sel {
53 SCL_COEF_LUMA_VERT_FILTER = 0,
54 SCL_COEF_LUMA_HORZ_FILTER = 1,
55 SCL_COEF_CHROMA_VERT_FILTER = 2,
56 SCL_COEF_CHROMA_HORZ_FILTER = 3,
57 SCL_COEF_ALPHA_VERT_FILTER = 4,
58 SCL_COEF_ALPHA_HORZ_FILTER = 5
59 };
60
61 enum dscl_autocal_mode {
62 AUTOCAL_MODE_OFF = 0,
63
64 /* Autocal calculate the scaling ratio and initial phase and the
65 * DSCL_MODE_SEL must be set to 1
66 */
67 AUTOCAL_MODE_AUTOSCALE = 1,
68 /* Autocal perform auto centering without replication and the
69 * DSCL_MODE_SEL must be set to 0
70 */
71 AUTOCAL_MODE_AUTOCENTER = 2,
72 /* Autocal perform auto centering and auto replication and the
73 * DSCL_MODE_SEL must be set to 0
74 */
75 AUTOCAL_MODE_AUTOREPLICATE = 3
76 };
77
78 enum dscl_mode_sel {
79 DSCL_MODE_SCALING_444_BYPASS = 0,
80 DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
81 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
82 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
83 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
84 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
85 DSCL_MODE_DSCL_BYPASS = 6
86 };
87
dpp1_dscl_set_overscan(struct dcn10_dpp * dpp,const struct scaler_data * data)88 static void dpp1_dscl_set_overscan(
89 struct dcn10_dpp *dpp,
90 const struct scaler_data *data)
91 {
92 uint32_t left = data->recout.x;
93 uint32_t top = data->recout.y;
94
95 int right = data->h_active - data->recout.x - data->recout.width;
96 int bottom = data->v_active - data->recout.y - data->recout.height;
97
98 if (right < 0) {
99 BREAK_TO_DEBUGGER();
100 right = 0;
101 }
102 if (bottom < 0) {
103 BREAK_TO_DEBUGGER();
104 bottom = 0;
105 }
106
107 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,
108 EXT_OVERSCAN_LEFT, left,
109 EXT_OVERSCAN_RIGHT, right);
110
111 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,
112 EXT_OVERSCAN_BOTTOM, bottom,
113 EXT_OVERSCAN_TOP, top);
114 }
115
dpp1_dscl_set_otg_blank(struct dcn10_dpp * dpp,const struct scaler_data * data)116 static void dpp1_dscl_set_otg_blank(
117 struct dcn10_dpp *dpp, const struct scaler_data *data)
118 {
119 uint32_t h_blank_start = data->h_active;
120 uint32_t h_blank_end = 0;
121 uint32_t v_blank_start = data->v_active;
122 uint32_t v_blank_end = 0;
123
124 REG_SET_2(OTG_H_BLANK, 0,
125 OTG_H_BLANK_START, h_blank_start,
126 OTG_H_BLANK_END, h_blank_end);
127
128 REG_SET_2(OTG_V_BLANK, 0,
129 OTG_V_BLANK_START, v_blank_start,
130 OTG_V_BLANK_END, v_blank_end);
131 }
132
dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)133 static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)
134 {
135 if (depth == LB_PIXEL_DEPTH_30BPP)
136 return 0; /* 10 bpc */
137 else if (depth == LB_PIXEL_DEPTH_24BPP)
138 return 1; /* 8 bpc */
139 else if (depth == LB_PIXEL_DEPTH_18BPP)
140 return 2; /* 6 bpc */
141 else if (depth == LB_PIXEL_DEPTH_36BPP)
142 return 3; /* 12 bpc */
143 else {
144 ASSERT(0);
145 return -1; /* Unsupported */
146 }
147 }
148
dpp1_dscl_is_video_format(enum pixel_format format)149 static bool dpp1_dscl_is_video_format(enum pixel_format format)
150 {
151 if (format >= PIXEL_FORMAT_VIDEO_BEGIN
152 && format <= PIXEL_FORMAT_VIDEO_END)
153 return true;
154 else
155 return false;
156 }
157
dpp1_dscl_is_420_format(enum pixel_format format)158 static bool dpp1_dscl_is_420_format(enum pixel_format format)
159 {
160 if (format == PIXEL_FORMAT_420BPP8 ||
161 format == PIXEL_FORMAT_420BPP10)
162 return true;
163 else
164 return false;
165 }
166
dpp1_dscl_get_dscl_mode(struct dpp * dpp_base,const struct scaler_data * data,bool dbg_always_scale)167 static enum dscl_mode_sel dpp1_dscl_get_dscl_mode(
168 struct dpp *dpp_base,
169 const struct scaler_data *data,
170 bool dbg_always_scale)
171 {
172 const long long one = dc_fixpt_one.value;
173
174 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
175 /* DSCL is processing data in fixed format */
176 if (data->format == PIXEL_FORMAT_FP16)
177 return DSCL_MODE_DSCL_BYPASS;
178 }
179
180 if (data->ratios.horz.value == one
181 && data->ratios.vert.value == one
182 && data->ratios.horz_c.value == one
183 && data->ratios.vert_c.value == one
184 && !dbg_always_scale)
185 return DSCL_MODE_SCALING_444_BYPASS;
186
187 if (!dpp1_dscl_is_420_format(data->format)) {
188 if (dpp1_dscl_is_video_format(data->format))
189 return DSCL_MODE_SCALING_444_YCBCR_ENABLE;
190 else
191 return DSCL_MODE_SCALING_444_RGB_ENABLE;
192 }
193 if (data->ratios.horz.value == one && data->ratios.vert.value == one)
194 return DSCL_MODE_SCALING_420_LUMA_BYPASS;
195 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one)
196 return DSCL_MODE_SCALING_420_CHROMA_BYPASS;
197
198 return DSCL_MODE_SCALING_420_YCBCR_ENABLE;
199 }
200
dpp1_power_on_dscl(struct dpp * dpp_base,bool power_on)201 static void dpp1_power_on_dscl(
202 struct dpp *dpp_base,
203 bool power_on)
204 {
205 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
206
207 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {
208 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, power_on ? 0 : 3);
209 if (power_on)
210 REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5);
211 }
212 }
213
214
dpp1_dscl_set_lb(struct dcn10_dpp * dpp,const struct line_buffer_params * lb_params,enum lb_memory_config mem_size_config)215 static void dpp1_dscl_set_lb(
216 struct dcn10_dpp *dpp,
217 const struct line_buffer_params *lb_params,
218 enum lb_memory_config mem_size_config)
219 {
220 uint32_t max_partitions = 63; /* Currently hardcoded on all ASICs before DCN 3.2 */
221
222 /* LB */
223 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
224 /* DSCL caps: pixel data processed in fixed format */
225 uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth);
226 uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;
227
228 REG_SET_7(LB_DATA_FORMAT, 0,
229 PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */
230 PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */
231 PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */
232 DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */
233 DITHER_EN, 0, /* Dithering enable: Disabled */
234 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
235 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
236 }
237 else {
238 /* DSCL caps: pixel data processed in float format */
239 REG_SET_2(LB_DATA_FORMAT, 0,
240 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
241 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
242 }
243
244 if (dpp->base.caps->max_lb_partitions == 31)
245 max_partitions = 31;
246
247 REG_SET_2(LB_MEMORY_CTRL, 0,
248 MEMORY_CONFIG, mem_size_config,
249 LB_MAX_PARTITIONS, max_partitions);
250 }
251
dpp1_dscl_get_filter_coeffs_64p(int taps,struct fixed31_32 ratio)252 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
253 {
254 if (taps == 8)
255 return get_filter_8tap_64p(ratio);
256 else if (taps == 7)
257 return get_filter_7tap_64p(ratio);
258 else if (taps == 6)
259 return get_filter_6tap_64p(ratio);
260 else if (taps == 5)
261 return get_filter_5tap_64p(ratio);
262 else if (taps == 4)
263 return get_filter_4tap_64p(ratio);
264 else if (taps == 3)
265 return get_filter_3tap_64p(ratio);
266 else if (taps == 2)
267 return get_filter_2tap_64p();
268 else if (taps == 1)
269 return NULL;
270 else {
271 /* should never happen, bug */
272 BREAK_TO_DEBUGGER();
273 return NULL;
274 }
275 }
276
dpp1_dscl_set_scaler_filter(struct dcn10_dpp * dpp,uint32_t taps,enum dcn10_coef_filter_type_sel filter_type,const uint16_t * filter)277 static void dpp1_dscl_set_scaler_filter(
278 struct dcn10_dpp *dpp,
279 uint32_t taps,
280 enum dcn10_coef_filter_type_sel filter_type,
281 const uint16_t *filter)
282 {
283 const int tap_pairs = (taps + 1) / 2;
284 int phase;
285 int pair;
286 uint16_t odd_coef, even_coef;
287
288 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,
289 SCL_COEF_RAM_TAP_PAIR_IDX, 0,
290 SCL_COEF_RAM_PHASE, 0,
291 SCL_COEF_RAM_FILTER_TYPE, filter_type);
292
293 for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
294 for (pair = 0; pair < tap_pairs; pair++) {
295 even_coef = filter[phase * taps + 2 * pair];
296 if ((pair * 2 + 1) < taps)
297 odd_coef = filter[phase * taps + 2 * pair + 1];
298 else
299 odd_coef = 0;
300
301 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
302 /* Even tap coefficient (bits 1:0 fixed to 0) */
303 SCL_COEF_RAM_EVEN_TAP_COEF, even_coef,
304 /* Write/read control for even coefficient */
305 SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,
306 /* Odd tap coefficient (bits 1:0 fixed to 0) */
307 SCL_COEF_RAM_ODD_TAP_COEF, odd_coef,
308 /* Write/read control for odd coefficient */
309 SCL_COEF_RAM_ODD_TAP_COEF_EN, 1);
310 }
311 }
312
313 }
314
dpp1_dscl_set_scl_filter(struct dcn10_dpp * dpp,const struct scaler_data * scl_data,bool chroma_coef_mode)315 static void dpp1_dscl_set_scl_filter(
316 struct dcn10_dpp *dpp,
317 const struct scaler_data *scl_data,
318 bool chroma_coef_mode)
319 {
320 bool h_2tap_hardcode_coef_en = false;
321 bool v_2tap_hardcode_coef_en = false;
322 bool h_2tap_sharp_en = false;
323 bool v_2tap_sharp_en = false;
324 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;
325 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;
326 bool coef_ram_current;
327 const uint16_t *filter_h = NULL;
328 const uint16_t *filter_v = NULL;
329 const uint16_t *filter_h_c = NULL;
330 const uint16_t *filter_v_c = NULL;
331
332 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
333 && scl_data->taps.h_taps_c < 3
334 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1);
335 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
336 && scl_data->taps.v_taps_c < 3
337 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1);
338
339 h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0;
340 v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0;
341
342 REG_UPDATE_6(DSCL_2TAP_CONTROL,
343 SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,
344 SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en,
345 SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor,
346 SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en,
347 SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en,
348 SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor);
349
350 if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) {
351 bool filter_updated = false;
352
353 filter_h = dpp1_dscl_get_filter_coeffs_64p(
354 scl_data->taps.h_taps, scl_data->ratios.horz);
355 filter_v = dpp1_dscl_get_filter_coeffs_64p(
356 scl_data->taps.v_taps, scl_data->ratios.vert);
357
358 filter_updated = (filter_h && (filter_h != dpp->filter_h))
359 || (filter_v && (filter_v != dpp->filter_v));
360
361 if (chroma_coef_mode) {
362 filter_h_c = dpp1_dscl_get_filter_coeffs_64p(
363 scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
364 filter_v_c = dpp1_dscl_get_filter_coeffs_64p(
365 scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
366 filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))
367 || (filter_v_c && (filter_v_c != dpp->filter_v_c));
368 }
369
370 if (filter_updated) {
371 uint32_t scl_mode = REG_READ(SCL_MODE);
372
373 if (!h_2tap_hardcode_coef_en && filter_h) {
374 dpp1_dscl_set_scaler_filter(
375 dpp, scl_data->taps.h_taps,
376 SCL_COEF_LUMA_HORZ_FILTER, filter_h);
377 }
378 dpp->filter_h = filter_h;
379 if (!v_2tap_hardcode_coef_en && filter_v) {
380 dpp1_dscl_set_scaler_filter(
381 dpp, scl_data->taps.v_taps,
382 SCL_COEF_LUMA_VERT_FILTER, filter_v);
383 }
384 dpp->filter_v = filter_v;
385 if (chroma_coef_mode) {
386 if (!h_2tap_hardcode_coef_en && filter_h_c) {
387 dpp1_dscl_set_scaler_filter(
388 dpp, scl_data->taps.h_taps_c,
389 SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);
390 }
391 if (!v_2tap_hardcode_coef_en && filter_v_c) {
392 dpp1_dscl_set_scaler_filter(
393 dpp, scl_data->taps.v_taps_c,
394 SCL_COEF_CHROMA_VERT_FILTER, filter_v_c);
395 }
396 }
397 dpp->filter_h_c = filter_h_c;
398 dpp->filter_v_c = filter_v_c;
399
400 coef_ram_current = get_reg_field_value_ex(
401 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
402 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
403
404 /* Swap coefficient RAM and set chroma coefficient mode */
405 REG_SET_2(SCL_MODE, scl_mode,
406 SCL_COEF_RAM_SELECT, !coef_ram_current,
407 SCL_CHROMA_COEF_MODE, chroma_coef_mode);
408 }
409 }
410 }
411
dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)412 static int dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)
413 {
414 if (depth == LB_PIXEL_DEPTH_30BPP)
415 return 10;
416 else if (depth == LB_PIXEL_DEPTH_24BPP)
417 return 8;
418 else if (depth == LB_PIXEL_DEPTH_18BPP)
419 return 6;
420 else if (depth == LB_PIXEL_DEPTH_36BPP)
421 return 12;
422 else {
423 BREAK_TO_DEBUGGER();
424 return -1; /* Unsupported */
425 }
426 }
427
dpp1_dscl_calc_lb_num_partitions(const struct scaler_data * scl_data,enum lb_memory_config lb_config,int * num_part_y,int * num_part_c)428 void dpp1_dscl_calc_lb_num_partitions(
429 const struct scaler_data *scl_data,
430 enum lb_memory_config lb_config,
431 int *num_part_y,
432 int *num_part_c)
433 {
434 int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a,
435 lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a;
436
437 int line_size = scl_data->viewport.width < scl_data->recout.width ?
438 scl_data->viewport.width : scl_data->recout.width;
439 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
440 scl_data->viewport_c.width : scl_data->recout.width;
441
442 if (line_size == 0)
443 line_size = 1;
444
445 if (line_size_c == 0)
446 line_size_c = 1;
447
448
449 lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth);
450 memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */
451 memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */
452 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
453
454 if (lb_config == LB_MEMORY_CONFIG_1) {
455 lb_memory_size = 816;
456 lb_memory_size_c = 816;
457 lb_memory_size_a = 984;
458 } else if (lb_config == LB_MEMORY_CONFIG_2) {
459 lb_memory_size = 1088;
460 lb_memory_size_c = 1088;
461 lb_memory_size_a = 1312;
462 } else if (lb_config == LB_MEMORY_CONFIG_3) {
463 /* 420 mode: using 3rd mem from Y, Cr and Cb */
464 lb_memory_size = 816 + 1088 + 848 + 848 + 848;
465 lb_memory_size_c = 816 + 1088;
466 lb_memory_size_a = 984 + 1312 + 456;
467 } else {
468 lb_memory_size = 816 + 1088 + 848;
469 lb_memory_size_c = 816 + 1088 + 848;
470 lb_memory_size_a = 984 + 1312 + 456;
471 }
472 *num_part_y = lb_memory_size / memory_line_size_y;
473 *num_part_c = lb_memory_size_c / memory_line_size_c;
474 num_partitions_a = lb_memory_size_a / memory_line_size_a;
475
476 if (scl_data->lb_params.alpha_en
477 && (num_partitions_a < *num_part_y))
478 *num_part_y = num_partitions_a;
479
480 if (*num_part_y > 64)
481 *num_part_y = 64;
482 if (*num_part_c > 64)
483 *num_part_c = 64;
484
485 }
486
dpp1_dscl_is_lb_conf_valid(int ceil_vratio,int num_partitions,int vtaps)487 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
488 {
489 if (ceil_vratio > 2)
490 return vtaps <= (num_partitions - ceil_vratio + 2);
491 else
492 return vtaps <= num_partitions;
493 }
494
495 /*find first match configuration which meets the min required lb size*/
dpp1_dscl_find_lb_memory_config(struct dcn10_dpp * dpp,const struct scaler_data * scl_data)496 static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,
497 const struct scaler_data *scl_data)
498 {
499 int num_part_y, num_part_c;
500 int vtaps = scl_data->taps.v_taps;
501 int vtaps_c = scl_data->taps.v_taps_c;
502 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert);
503 int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
504
505 if (dpp->base.ctx->dc->debug.use_max_lb) {
506 if (scl_data->format == PIXEL_FORMAT_420BPP8
507 || scl_data->format == PIXEL_FORMAT_420BPP10)
508 return LB_MEMORY_CONFIG_3;
509 return LB_MEMORY_CONFIG_0;
510 }
511
512 dpp->base.caps->dscl_calc_lb_num_partitions(
513 scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c);
514
515 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
516 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
517 return LB_MEMORY_CONFIG_1;
518
519 dpp->base.caps->dscl_calc_lb_num_partitions(
520 scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c);
521
522 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
523 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
524 return LB_MEMORY_CONFIG_2;
525
526 if (scl_data->format == PIXEL_FORMAT_420BPP8
527 || scl_data->format == PIXEL_FORMAT_420BPP10) {
528 dpp->base.caps->dscl_calc_lb_num_partitions(
529 scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c);
530
531 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
532 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
533 return LB_MEMORY_CONFIG_3;
534 }
535
536 dpp->base.caps->dscl_calc_lb_num_partitions(
537 scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c);
538
539 /*Ensure we can support the requested number of vtaps*/
540 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
541 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c));
542
543 return LB_MEMORY_CONFIG_0;
544 }
545
dpp1_dscl_set_scaler_auto_scale(struct dpp * dpp_base,const struct scaler_data * scl_data)546 void dpp1_dscl_set_scaler_auto_scale(
547 struct dpp *dpp_base,
548 const struct scaler_data *scl_data)
549 {
550 enum lb_memory_config lb_config;
551 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
552 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
553 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
554 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
555 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
556
557 dpp1_dscl_set_overscan(dpp, scl_data);
558
559 dpp1_dscl_set_otg_blank(dpp, scl_data);
560
561 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
562
563 if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
564 return;
565
566 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
567 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
568
569 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
570 return;
571
572 /* TODO: v_min */
573 REG_SET_3(DSCL_AUTOCAL, 0,
574 AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE,
575 AUTOCAL_NUM_PIPE, 0,
576 AUTOCAL_PIPE_ID, 0);
577
578 /* Black offsets */
579 if (ycbcr)
580 REG_SET_2(SCL_BLACK_OFFSET, 0,
581 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
582 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
583 else
584
585 REG_SET_2(SCL_BLACK_OFFSET, 0,
586 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
587 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
588
589 REG_SET_4(SCL_TAP_CONTROL, 0,
590 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
591 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
592 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
593 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
594
595 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
596 }
597
598
dpp1_dscl_set_manual_ratio_init(struct dcn10_dpp * dpp,const struct scaler_data * data)599 static void dpp1_dscl_set_manual_ratio_init(
600 struct dcn10_dpp *dpp, const struct scaler_data *data)
601 {
602 uint32_t init_frac = 0;
603 uint32_t init_int = 0;
604
605 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
606 SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5);
607
608 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
609 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5);
610
611 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
612 SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5);
613
614 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
615 SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5);
616
617 /*
618 * 0.24 format for fraction, first five bits zeroed
619 */
620 init_frac = dc_fixpt_u0d19(data->inits.h) << 5;
621 init_int = dc_fixpt_floor(data->inits.h);
622 REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
623 SCL_H_INIT_FRAC, init_frac,
624 SCL_H_INIT_INT, init_int);
625
626 init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5;
627 init_int = dc_fixpt_floor(data->inits.h_c);
628 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,
629 SCL_H_INIT_FRAC_C, init_frac,
630 SCL_H_INIT_INT_C, init_int);
631
632 init_frac = dc_fixpt_u0d19(data->inits.v) << 5;
633 init_int = dc_fixpt_floor(data->inits.v);
634 REG_SET_2(SCL_VERT_FILTER_INIT, 0,
635 SCL_V_INIT_FRAC, init_frac,
636 SCL_V_INIT_INT, init_int);
637
638 if (REG(SCL_VERT_FILTER_INIT_BOT)) {
639 struct fixed31_32 bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
640
641 init_frac = dc_fixpt_u0d19(bot) << 5;
642 init_int = dc_fixpt_floor(bot);
643 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,
644 SCL_V_INIT_FRAC_BOT, init_frac,
645 SCL_V_INIT_INT_BOT, init_int);
646 }
647
648 init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5;
649 init_int = dc_fixpt_floor(data->inits.v_c);
650 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,
651 SCL_V_INIT_FRAC_C, init_frac,
652 SCL_V_INIT_INT_C, init_int);
653
654 if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {
655 struct fixed31_32 bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
656
657 init_frac = dc_fixpt_u0d19(bot) << 5;
658 init_int = dc_fixpt_floor(bot);
659 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,
660 SCL_V_INIT_FRAC_BOT_C, init_frac,
661 SCL_V_INIT_INT_BOT_C, init_int);
662 }
663 }
664
665 /**
666 * dpp1_dscl_set_recout - Set the first pixel of RECOUT in the OTG active area
667 *
668 * @dpp: DPP data struct
669 * @recount: Rectangle information
670 *
671 * This function sets the MPC RECOUT_START and RECOUT_SIZE registers based on
672 * the values specified in the recount parameter.
673 *
674 * Note: This function only have effect if AutoCal is disabled.
675 */
dpp1_dscl_set_recout(struct dcn10_dpp * dpp,const struct rect * recout)676 static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp,
677 const struct rect *recout)
678 {
679 int visual_confirm_on = 0;
680 if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
681 visual_confirm_on = 1;
682
683 REG_SET_2(RECOUT_START, 0,
684 /* First pixel of RECOUT in the active OTG area */
685 RECOUT_START_X, recout->x,
686 /* First line of RECOUT in the active OTG area */
687 RECOUT_START_Y, recout->y);
688
689 REG_SET_2(RECOUT_SIZE, 0,
690 /* Number of RECOUT horizontal pixels */
691 RECOUT_WIDTH, recout->width,
692 /* Number of RECOUT vertical lines */
693 RECOUT_HEIGHT, recout->height
694 - visual_confirm_on * 2 * (dpp->base.inst + 1));
695 }
696
697 /**
698 * dpp1_dscl_set_scaler_manual_scale - Manually program scaler and line buffer
699 *
700 * @dpp_base: High level DPP struct
701 * @scl_data: scalaer_data info
702 *
703 * This is the primary function to program scaler and line buffer in manual
704 * scaling mode. To execute the required operations for manual scale, we need
705 * to disable AutoCal first.
706 */
dpp1_dscl_set_scaler_manual_scale(struct dpp * dpp_base,const struct scaler_data * scl_data)707 void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base,
708 const struct scaler_data *scl_data)
709 {
710 enum lb_memory_config lb_config;
711 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
712 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
713 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
714 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
715 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
716
717 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)
718 return;
719
720 PERF_TRACE();
721
722 dpp->scl_data = *scl_data;
723
724 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {
725 if (dscl_mode != DSCL_MODE_DSCL_BYPASS)
726 dpp1_power_on_dscl(dpp_base, true);
727 }
728
729 /* Autocal off */
730 REG_SET_3(DSCL_AUTOCAL, 0,
731 AUTOCAL_MODE, AUTOCAL_MODE_OFF,
732 AUTOCAL_NUM_PIPE, 0,
733 AUTOCAL_PIPE_ID, 0);
734
735 /* Recout */
736 dpp1_dscl_set_recout(dpp, &scl_data->recout);
737
738 /* MPC Size */
739 REG_SET_2(MPC_SIZE, 0,
740 /* Number of horizontal pixels of MPC */
741 MPC_WIDTH, scl_data->h_active,
742 /* Number of vertical lines of MPC */
743 MPC_HEIGHT, scl_data->v_active);
744
745 /* SCL mode */
746 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
747
748 if (dscl_mode == DSCL_MODE_DSCL_BYPASS) {
749 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)
750 dpp1_power_on_dscl(dpp_base, false);
751 return;
752 }
753
754 /* LB */
755 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
756 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
757
758 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
759 return;
760
761 /* Black offsets */
762 if (REG(SCL_BLACK_OFFSET)) {
763 if (ycbcr)
764 REG_SET_2(SCL_BLACK_OFFSET, 0,
765 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
766 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR);
767 else
768
769 REG_SET_2(SCL_BLACK_OFFSET, 0,
770 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,
771 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y);
772 }
773
774 /* Manually calculate scale ratio and init values */
775 dpp1_dscl_set_manual_ratio_init(dpp, scl_data);
776
777 /* HTaps/VTaps */
778 REG_SET_4(SCL_TAP_CONTROL, 0,
779 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,
780 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,
781 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,
782 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
783
784 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
785 PERF_TRACE();
786 }
787
