1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_ucode.h"
30
amdgpu_ucode_print_common_hdr(const struct common_firmware_header * hdr)31 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
32 {
33 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
34 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
35 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
36 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
37 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
38 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
39 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
40 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
41 DRM_DEBUG("ucode_array_offset_bytes: %u\n",
42 le32_to_cpu(hdr->ucode_array_offset_bytes));
43 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
44 }
45
amdgpu_ucode_print_mc_hdr(const struct common_firmware_header * hdr)46 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
47 {
48 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
49 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
50
51 DRM_DEBUG("MC\n");
52 amdgpu_ucode_print_common_hdr(hdr);
53
54 if (version_major == 1) {
55 const struct mc_firmware_header_v1_0 *mc_hdr =
56 container_of(hdr, struct mc_firmware_header_v1_0, header);
57
58 DRM_DEBUG("io_debug_size_bytes: %u\n",
59 le32_to_cpu(mc_hdr->io_debug_size_bytes));
60 DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
61 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
62 } else {
63 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
64 }
65 }
66
amdgpu_ucode_print_smc_hdr(const struct common_firmware_header * hdr)67 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
68 {
69 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
70 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
71 const struct smc_firmware_header_v1_0 *v1_0_hdr;
72 const struct smc_firmware_header_v2_0 *v2_0_hdr;
73 const struct smc_firmware_header_v2_1 *v2_1_hdr;
74
75 DRM_DEBUG("SMC\n");
76 amdgpu_ucode_print_common_hdr(hdr);
77
78 if (version_major == 1) {
79 v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
80 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
81 } else if (version_major == 2) {
82 switch (version_minor) {
83 case 0:
84 v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
85 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
86 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
87 break;
88 case 1:
89 v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
90 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
91 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
92 break;
93 default:
94 break;
95 }
96
97 } else {
98 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
99 }
100 }
101
amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header * hdr)102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
103 {
104 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
105 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
106
107 DRM_DEBUG("GFX\n");
108 amdgpu_ucode_print_common_hdr(hdr);
109
110 if (version_major == 1) {
111 const struct gfx_firmware_header_v1_0 *gfx_hdr =
112 container_of(hdr, struct gfx_firmware_header_v1_0, header);
113
114 DRM_DEBUG("ucode_feature_version: %u\n",
115 le32_to_cpu(gfx_hdr->ucode_feature_version));
116 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
117 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
118 } else {
119 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
120 }
121 }
122
amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header * hdr)123 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
124 {
125 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
126 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
127
128 DRM_DEBUG("RLC\n");
129 amdgpu_ucode_print_common_hdr(hdr);
130
131 if (version_major == 1) {
132 const struct rlc_firmware_header_v1_0 *rlc_hdr =
133 container_of(hdr, struct rlc_firmware_header_v1_0, header);
134
135 DRM_DEBUG("ucode_feature_version: %u\n",
136 le32_to_cpu(rlc_hdr->ucode_feature_version));
137 DRM_DEBUG("save_and_restore_offset: %u\n",
138 le32_to_cpu(rlc_hdr->save_and_restore_offset));
139 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
140 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
141 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
142 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
143 DRM_DEBUG("master_pkt_description_offset: %u\n",
144 le32_to_cpu(rlc_hdr->master_pkt_description_offset));
145 } else if (version_major == 2) {
146 const struct rlc_firmware_header_v2_0 *rlc_hdr =
147 container_of(hdr, struct rlc_firmware_header_v2_0, header);
148
149 DRM_DEBUG("ucode_feature_version: %u\n",
150 le32_to_cpu(rlc_hdr->ucode_feature_version));
151 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
152 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
153 DRM_DEBUG("save_and_restore_offset: %u\n",
154 le32_to_cpu(rlc_hdr->save_and_restore_offset));
155 DRM_DEBUG("clear_state_descriptor_offset: %u\n",
156 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
157 DRM_DEBUG("avail_scratch_ram_locations: %u\n",
158 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
159 DRM_DEBUG("reg_restore_list_size: %u\n",
160 le32_to_cpu(rlc_hdr->reg_restore_list_size));
161 DRM_DEBUG("reg_list_format_start: %u\n",
162 le32_to_cpu(rlc_hdr->reg_list_format_start));
163 DRM_DEBUG("reg_list_format_separate_start: %u\n",
164 le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
165 DRM_DEBUG("starting_offsets_start: %u\n",
166 le32_to_cpu(rlc_hdr->starting_offsets_start));
167 DRM_DEBUG("reg_list_format_size_bytes: %u\n",
168 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
169 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
170 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
171 DRM_DEBUG("reg_list_size_bytes: %u\n",
172 le32_to_cpu(rlc_hdr->reg_list_size_bytes));
173 DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
174 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
175 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
176 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
177 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
178 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
179 DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
180 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
181 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
182 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
183 if (version_minor == 1) {
184 const struct rlc_firmware_header_v2_1 *v2_1 =
185 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
186 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
187 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
188 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
189 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
190 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
191 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
192 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
193 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
194 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
195 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
196 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
197 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
198 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
199 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
200 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
201 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
202 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
203 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
204 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
205 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
206 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
207 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
208 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
209 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
210 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
211 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
212 }
213 } else {
214 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
215 }
216 }
217
amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header * hdr)218 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
219 {
220 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
221 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
222
223 DRM_DEBUG("SDMA\n");
224 amdgpu_ucode_print_common_hdr(hdr);
225
226 if (version_major == 1) {
227 const struct sdma_firmware_header_v1_0 *sdma_hdr =
228 container_of(hdr, struct sdma_firmware_header_v1_0, header);
229
230 DRM_DEBUG("ucode_feature_version: %u\n",
231 le32_to_cpu(sdma_hdr->ucode_feature_version));
232 DRM_DEBUG("ucode_change_version: %u\n",
233 le32_to_cpu(sdma_hdr->ucode_change_version));
234 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
235 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
236 if (version_minor >= 1) {
237 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
238 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
239 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
240 }
241 } else {
242 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
243 version_major, version_minor);
244 }
245 }
246
amdgpu_ucode_print_psp_hdr(const struct common_firmware_header * hdr)247 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
248 {
249 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
250 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
251
252 DRM_DEBUG("PSP\n");
253 amdgpu_ucode_print_common_hdr(hdr);
254
255 if (version_major == 1) {
256 const struct psp_firmware_header_v1_0 *psp_hdr =
257 container_of(hdr, struct psp_firmware_header_v1_0, header);
258
259 DRM_DEBUG("ucode_feature_version: %u\n",
260 le32_to_cpu(psp_hdr->sos.fw_version));
261 DRM_DEBUG("sos_offset_bytes: %u\n",
262 le32_to_cpu(psp_hdr->sos.offset_bytes));
263 DRM_DEBUG("sos_size_bytes: %u\n",
264 le32_to_cpu(psp_hdr->sos.size_bytes));
265 if (version_minor == 1) {
266 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
267 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
268 DRM_DEBUG("toc_header_version: %u\n",
269 le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
270 DRM_DEBUG("toc_offset_bytes: %u\n",
271 le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
272 DRM_DEBUG("toc_size_bytes: %u\n",
273 le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
274 DRM_DEBUG("kdb_header_version: %u\n",
275 le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
276 DRM_DEBUG("kdb_offset_bytes: %u\n",
277 le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
278 DRM_DEBUG("kdb_size_bytes: %u\n",
279 le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
280 }
281 if (version_minor == 2) {
282 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
283 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
284 DRM_DEBUG("kdb_header_version: %u\n",
285 le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
286 DRM_DEBUG("kdb_offset_bytes: %u\n",
287 le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
288 DRM_DEBUG("kdb_size_bytes: %u\n",
289 le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
290 }
291 if (version_minor == 3) {
292 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
293 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
294 const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
295 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
296 DRM_DEBUG("toc_header_version: %u\n",
297 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
298 DRM_DEBUG("toc_offset_bytes: %u\n",
299 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
300 DRM_DEBUG("toc_size_bytes: %u\n",
301 le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
302 DRM_DEBUG("kdb_header_version: %u\n",
303 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
304 DRM_DEBUG("kdb_offset_bytes: %u\n",
305 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
306 DRM_DEBUG("kdb_size_bytes: %u\n",
307 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
308 DRM_DEBUG("spl_header_version: %u\n",
309 le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
310 DRM_DEBUG("spl_offset_bytes: %u\n",
311 le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
312 DRM_DEBUG("spl_size_bytes: %u\n",
313 le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
314 }
315 } else {
316 DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
317 version_major, version_minor);
318 }
319 }
320
amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header * hdr)321 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
322 {
323 uint16_t version_major = le16_to_cpu(hdr->header_version_major);
324 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
325
326 DRM_DEBUG("GPU_INFO\n");
327 amdgpu_ucode_print_common_hdr(hdr);
328
329 if (version_major == 1) {
330 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
331 container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
332
333 DRM_DEBUG("version_major: %u\n",
334 le16_to_cpu(gpu_info_hdr->version_major));
335 DRM_DEBUG("version_minor: %u\n",
336 le16_to_cpu(gpu_info_hdr->version_minor));
337 } else {
338 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
339 }
340 }
341
amdgpu_ucode_validate(const struct firmware * fw)342 int amdgpu_ucode_validate(const struct firmware *fw)
343 {
344 const struct common_firmware_header *hdr =
345 (const struct common_firmware_header *)fw->data;
346
347 if (fw->size == le32_to_cpu(hdr->size_bytes))
348 return 0;
349
350 return -EINVAL;
351 }
352
amdgpu_ucode_hdr_version(union amdgpu_firmware_header * hdr,uint16_t hdr_major,uint16_t hdr_minor)353 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
354 uint16_t hdr_major, uint16_t hdr_minor)
355 {
356 if ((hdr->common.header_version_major == hdr_major) &&
357 (hdr->common.header_version_minor == hdr_minor))
358 return false;
359 return true;
360 }
361
362 enum amdgpu_firmware_load_type
amdgpu_ucode_get_load_type(struct amdgpu_device * adev,int load_type)363 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
364 {
365 switch (adev->asic_type) {
366 #ifdef CONFIG_DRM_AMDGPU_SI
367 case CHIP_TAHITI:
368 case CHIP_PITCAIRN:
369 case CHIP_VERDE:
370 case CHIP_OLAND:
371 case CHIP_HAINAN:
372 return AMDGPU_FW_LOAD_DIRECT;
373 #endif
374 #ifdef CONFIG_DRM_AMDGPU_CIK
375 case CHIP_BONAIRE:
376 case CHIP_KAVERI:
377 case CHIP_KABINI:
378 case CHIP_HAWAII:
379 case CHIP_MULLINS:
380 return AMDGPU_FW_LOAD_DIRECT;
381 #endif
382 case CHIP_TOPAZ:
383 case CHIP_TONGA:
384 case CHIP_FIJI:
385 case CHIP_CARRIZO:
386 case CHIP_STONEY:
387 case CHIP_POLARIS10:
388 case CHIP_POLARIS11:
389 case CHIP_POLARIS12:
390 case CHIP_VEGAM:
391 return AMDGPU_FW_LOAD_SMU;
392 case CHIP_VEGA10:
393 case CHIP_RAVEN:
394 case CHIP_VEGA12:
395 case CHIP_VEGA20:
396 case CHIP_ARCTURUS:
397 case CHIP_RENOIR:
398 case CHIP_NAVI10:
399 case CHIP_NAVI14:
400 case CHIP_NAVI12:
401 case CHIP_SIENNA_CICHLID:
402 case CHIP_NAVY_FLOUNDER:
403 case CHIP_VANGOGH:
404 case CHIP_DIMGREY_CAVEFISH:
405 case CHIP_ALDEBARAN:
406 case CHIP_BEIGE_GOBY:
407 case CHIP_YELLOW_CARP:
408 if (!load_type)
409 return AMDGPU_FW_LOAD_DIRECT;
410 else
411 return AMDGPU_FW_LOAD_PSP;
412 case CHIP_CYAN_SKILLFISH:
413 if (!(load_type &&
414 adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
415 return AMDGPU_FW_LOAD_DIRECT;
416 else
417 return AMDGPU_FW_LOAD_PSP;
418 default:
419 DRM_ERROR("Unknown firmware load type\n");
420 }
421
422 return AMDGPU_FW_LOAD_DIRECT;
423 }
424
amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)425 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
426 {
427 switch (ucode_id) {
428 case AMDGPU_UCODE_ID_SDMA0:
429 return "SDMA0";
430 case AMDGPU_UCODE_ID_SDMA1:
431 return "SDMA1";
432 case AMDGPU_UCODE_ID_SDMA2:
433 return "SDMA2";
434 case AMDGPU_UCODE_ID_SDMA3:
435 return "SDMA3";
436 case AMDGPU_UCODE_ID_SDMA4:
437 return "SDMA4";
438 case AMDGPU_UCODE_ID_SDMA5:
439 return "SDMA5";
440 case AMDGPU_UCODE_ID_SDMA6:
441 return "SDMA6";
442 case AMDGPU_UCODE_ID_SDMA7:
443 return "SDMA7";
444 case AMDGPU_UCODE_ID_CP_CE:
445 return "CP_CE";
446 case AMDGPU_UCODE_ID_CP_PFP:
447 return "CP_PFP";
448 case AMDGPU_UCODE_ID_CP_ME:
449 return "CP_ME";
450 case AMDGPU_UCODE_ID_CP_MEC1:
451 return "CP_MEC1";
452 case AMDGPU_UCODE_ID_CP_MEC1_JT:
453 return "CP_MEC1_JT";
454 case AMDGPU_UCODE_ID_CP_MEC2:
455 return "CP_MEC2";
456 case AMDGPU_UCODE_ID_CP_MEC2_JT:
457 return "CP_MEC2_JT";
458 case AMDGPU_UCODE_ID_CP_MES:
459 return "CP_MES";
460 case AMDGPU_UCODE_ID_CP_MES_DATA:
461 return "CP_MES_DATA";
462 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
463 return "RLC_RESTORE_LIST_CNTL";
464 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
465 return "RLC_RESTORE_LIST_GPM_MEM";
466 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
467 return "RLC_RESTORE_LIST_SRM_MEM";
468 case AMDGPU_UCODE_ID_RLC_IRAM:
469 return "RLC_IRAM";
470 case AMDGPU_UCODE_ID_RLC_DRAM:
471 return "RLC_DRAM";
472 case AMDGPU_UCODE_ID_RLC_G:
473 return "RLC_G";
474 case AMDGPU_UCODE_ID_STORAGE:
475 return "STORAGE";
476 case AMDGPU_UCODE_ID_SMC:
477 return "SMC";
478 case AMDGPU_UCODE_ID_UVD:
479 return "UVD";
480 case AMDGPU_UCODE_ID_UVD1:
481 return "UVD1";
482 case AMDGPU_UCODE_ID_VCE:
483 return "VCE";
484 case AMDGPU_UCODE_ID_VCN:
485 return "VCN";
486 case AMDGPU_UCODE_ID_VCN1:
487 return "VCN1";
488 case AMDGPU_UCODE_ID_DMCU_ERAM:
489 return "DMCU_ERAM";
490 case AMDGPU_UCODE_ID_DMCU_INTV:
491 return "DMCU_INTV";
492 case AMDGPU_UCODE_ID_VCN0_RAM:
493 return "VCN0_RAM";
494 case AMDGPU_UCODE_ID_VCN1_RAM:
495 return "VCN1_RAM";
496 case AMDGPU_UCODE_ID_DMCUB:
497 return "DMCUB";
498 default:
499 return "UNKNOWN UCODE";
500 }
501 }
502
503 #define FW_VERSION_ATTR(name, mode, field) \
504 static ssize_t show_##name(struct device *dev, \
505 struct device_attribute *attr, \
506 char *buf) \
507 { \
508 struct drm_device *ddev = dev_get_drvdata(dev); \
509 struct amdgpu_device *adev = drm_to_adev(ddev); \
510 \
511 return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field); \
512 } \
513 static DEVICE_ATTR(name, mode, show_##name, NULL)
514
515 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
516 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
517 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
518 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
519 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
520 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
521 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
522 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
523 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
524 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
525 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
526 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
527 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
528 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd.fw_version);
529 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras.feature_version);
530 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi.feature_version);
531 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
532 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
533 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
534 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
535 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
536
537 static struct attribute *fw_attrs[] = {
538 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
539 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
540 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
541 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
542 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
543 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
544 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
545 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
546 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
547 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
548 &dev_attr_dmcu_fw_version.attr, NULL
549 };
550
551 static const struct attribute_group fw_attr_group = {
552 .name = "fw_version",
553 .attrs = fw_attrs
554 };
555
amdgpu_ucode_sysfs_init(struct amdgpu_device * adev)556 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
557 {
558 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
559 }
560
amdgpu_ucode_sysfs_fini(struct amdgpu_device * adev)561 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
562 {
563 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
564 }
565
amdgpu_ucode_init_single_fw(struct amdgpu_device * adev,struct amdgpu_firmware_info * ucode,uint64_t mc_addr,void * kptr)566 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
567 struct amdgpu_firmware_info *ucode,
568 uint64_t mc_addr, void *kptr)
569 {
570 const struct common_firmware_header *header = NULL;
571 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
572 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
573 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
574 const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
575
576 if (NULL == ucode->fw)
577 return 0;
578
579 ucode->mc_addr = mc_addr;
580 ucode->kaddr = kptr;
581
582 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
583 return 0;
584
585 header = (const struct common_firmware_header *)ucode->fw->data;
586 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
587 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
588 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
589 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
590
591 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP ||
592 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 &&
593 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 &&
594 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT &&
595 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT &&
596 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES &&
597 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES_DATA &&
598 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL &&
599 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM &&
600 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM &&
601 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM &&
602 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM &&
603 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM &&
604 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV &&
605 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) {
606 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
607
608 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
609 le32_to_cpu(header->ucode_array_offset_bytes)),
610 ucode->ucode_size);
611 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 ||
612 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) {
613 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
614 le32_to_cpu(cp_hdr->jt_size) * 4;
615
616 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
617 le32_to_cpu(header->ucode_array_offset_bytes)),
618 ucode->ucode_size);
619 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
620 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) {
621 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
622
623 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
624 le32_to_cpu(header->ucode_array_offset_bytes) +
625 le32_to_cpu(cp_hdr->jt_offset) * 4),
626 ucode->ucode_size);
627 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) {
628 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
629 le32_to_cpu(dmcu_hdr->intv_size_bytes);
630
631 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
632 le32_to_cpu(header->ucode_array_offset_bytes)),
633 ucode->ucode_size);
634 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) {
635 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
636
637 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data +
638 le32_to_cpu(header->ucode_array_offset_bytes) +
639 le32_to_cpu(dmcu_hdr->intv_offset_bytes)),
640 ucode->ucode_size);
641 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) {
642 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
643 memcpy(ucode->kaddr,
644 (void *)((uint8_t *)ucode->fw->data +
645 le32_to_cpu(header->ucode_array_offset_bytes)),
646 ucode->ucode_size);
647 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) {
648 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
649 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl,
650 ucode->ucode_size);
651 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) {
652 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
653 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm,
654 ucode->ucode_size);
655 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
656 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
657 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm,
658 ucode->ucode_size);
659 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) {
660 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
661 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode,
662 ucode->ucode_size);
663 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) {
664 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
665 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode,
666 ucode->ucode_size);
667 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) {
668 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
669 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
670 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)),
671 ucode->ucode_size);
672 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA) {
673 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
674 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data +
675 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)),
676 ucode->ucode_size);
677 }
678
679 return 0;
680 }
681
amdgpu_ucode_patch_jt(struct amdgpu_firmware_info * ucode,uint64_t mc_addr,void * kptr)682 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
683 uint64_t mc_addr, void *kptr)
684 {
685 const struct gfx_firmware_header_v1_0 *header = NULL;
686 const struct common_firmware_header *comm_hdr = NULL;
687 uint8_t *src_addr = NULL;
688 uint8_t *dst_addr = NULL;
689
690 if (NULL == ucode->fw)
691 return 0;
692
693 comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
694 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
695 dst_addr = ucode->kaddr +
696 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
697 PAGE_SIZE);
698 src_addr = (uint8_t *)ucode->fw->data +
699 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
700 (le32_to_cpu(header->jt_offset) * 4);
701 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
702
703 return 0;
704 }
705
amdgpu_ucode_create_bo(struct amdgpu_device * adev)706 int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
707 {
708 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
709 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
710 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
711 &adev->firmware.fw_buf,
712 &adev->firmware.fw_buf_mc,
713 &adev->firmware.fw_buf_ptr);
714 if (!adev->firmware.fw_buf) {
715 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
716 return -ENOMEM;
717 } else if (amdgpu_sriov_vf(adev)) {
718 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
719 }
720 }
721 return 0;
722 }
723
amdgpu_ucode_free_bo(struct amdgpu_device * adev)724 void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
725 {
726 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT)
727 amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
728 &adev->firmware.fw_buf_mc,
729 &adev->firmware.fw_buf_ptr);
730 }
731
amdgpu_ucode_init_bo(struct amdgpu_device * adev)732 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
733 {
734 uint64_t fw_offset = 0;
735 int i;
736 struct amdgpu_firmware_info *ucode = NULL;
737
738 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
739 if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
740 return 0;
741 /*
742 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
743 * ucode info here
744 */
745 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
746 if (amdgpu_sriov_vf(adev))
747 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
748 else
749 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
750 } else {
751 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
752 }
753
754 for (i = 0; i < adev->firmware.max_ucodes; i++) {
755 ucode = &adev->firmware.ucode[i];
756 if (ucode->fw) {
757 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
758 adev->firmware.fw_buf_ptr + fw_offset);
759 if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
760 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
761 const struct gfx_firmware_header_v1_0 *cp_hdr;
762 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
763 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset,
764 adev->firmware.fw_buf_ptr + fw_offset);
765 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
766 }
767 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
768 }
769 }
770 return 0;
771 }
772
