1 /*
2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 #include "amdgpu.h"
23 #include "amdgpu_ras.h"
24
amdgpu_nbio_ras_late_init(struct amdgpu_device * adev)25 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev)
26 {
27 int r;
28 struct ras_ih_if ih_info = {
29 .cb = NULL,
30 };
31 struct ras_fs_if fs_info = {
32 .sysfs_name = "pcie_bif_err_count",
33 };
34
35 if (!adev->nbio.ras_if) {
36 adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
37 if (!adev->nbio.ras_if)
38 return -ENOMEM;
39 adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
40 adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
41 adev->nbio.ras_if->sub_block_index = 0;
42 }
43 ih_info.head = fs_info.head = *adev->nbio.ras_if;
44 r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
45 &fs_info, &ih_info);
46 if (r)
47 goto free;
48
49 if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {
50 r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
51 if (r)
52 goto late_fini;
53 r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
54 if (r)
55 goto late_fini;
56 } else {
57 r = 0;
58 goto free;
59 }
60
61 return 0;
62 late_fini:
63 amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);
64 free:
65 kfree(adev->nbio.ras_if);
66 adev->nbio.ras_if = NULL;
67 return r;
68 }
69
amdgpu_nbio_ras_fini(struct amdgpu_device * adev)70 void amdgpu_nbio_ras_fini(struct amdgpu_device *adev)
71 {
72 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF) &&
73 adev->nbio.ras_if) {
74 struct ras_common_if *ras_if = adev->nbio.ras_if;
75 struct ras_ih_if ih_info = {
76 .cb = NULL,
77 };
78
79 amdgpu_ras_late_fini(adev, ras_if, &ih_info);
80 kfree(ras_if);
81 }
82 }
83
