1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Generic EP93xx GPIO handling
4 *
5 * Copyright (c) 2008 Ryan Mallon
6 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
7 *
8 * Based on code originally from:
9 * linux/arch/arm/mach-ep93xx/core.c
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/io.h>
16 #include <linux/irq.h>
17 #include <linux/slab.h>
18 #include <linux/gpio/driver.h>
19 #include <linux/bitops.h>
20
21 #define EP93XX_GPIO_F_INT_STATUS 0x5c
22 #define EP93XX_GPIO_A_INT_STATUS 0xa0
23 #define EP93XX_GPIO_B_INT_STATUS 0xbc
24
25 /* Maximum value for gpio line identifiers */
26 #define EP93XX_GPIO_LINE_MAX 63
27
28 /* Number of GPIO chips in EP93XX */
29 #define EP93XX_GPIO_CHIP_NUM 8
30
31 /* Maximum value for irq capable line identifiers */
32 #define EP93XX_GPIO_LINE_MAX_IRQ 23
33
34 #define EP93XX_GPIO_A_IRQ_BASE 64
35 #define EP93XX_GPIO_B_IRQ_BASE 72
36 /*
37 * Static mapping of GPIO bank F IRQS:
38 * F0..F7 (16..24) to irq 80..87.
39 */
40 #define EP93XX_GPIO_F_IRQ_BASE 80
41
42 struct ep93xx_gpio_irq_chip {
43 struct irq_chip ic;
44 u8 irq_offset;
45 u8 int_unmasked;
46 u8 int_enabled;
47 u8 int_type1;
48 u8 int_type2;
49 u8 int_debounce;
50 };
51
52 struct ep93xx_gpio_chip {
53 struct gpio_chip gc;
54 struct ep93xx_gpio_irq_chip *eic;
55 };
56
57 struct ep93xx_gpio {
58 void __iomem *base;
59 struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM];
60 };
61
62 #define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
63
to_ep93xx_gpio_irq_chip(struct gpio_chip * gc)64 static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
65 {
66 struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
67
68 return egc->eic;
69 }
70
71 /*************************************************************************
72 * Interrupt handling for EP93xx on-chip GPIOs
73 *************************************************************************/
74 #define EP93XX_INT_TYPE1_OFFSET 0x00
75 #define EP93XX_INT_TYPE2_OFFSET 0x04
76 #define EP93XX_INT_EOI_OFFSET 0x08
77 #define EP93XX_INT_EN_OFFSET 0x0c
78 #define EP93XX_INT_STATUS_OFFSET 0x10
79 #define EP93XX_INT_RAW_STATUS_OFFSET 0x14
80 #define EP93XX_INT_DEBOUNCE_OFFSET 0x18
81
ep93xx_gpio_update_int_params(struct ep93xx_gpio * epg,struct ep93xx_gpio_irq_chip * eic)82 static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
83 struct ep93xx_gpio_irq_chip *eic)
84 {
85 writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
86
87 writeb_relaxed(eic->int_type2,
88 epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
89
90 writeb_relaxed(eic->int_type1,
91 epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
92
93 writeb_relaxed(eic->int_unmasked & eic->int_enabled,
94 epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
95 }
96
ep93xx_gpio_int_debounce(struct gpio_chip * gc,unsigned int offset,bool enable)97 static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
98 unsigned int offset, bool enable)
99 {
100 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
101 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
102 int port_mask = BIT(offset);
103
104 if (enable)
105 eic->int_debounce |= port_mask;
106 else
107 eic->int_debounce &= ~port_mask;
108
109 writeb(eic->int_debounce,
110 epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
111 }
112
ep93xx_gpio_ab_irq_handler(struct irq_desc * desc)113 static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
114 {
115 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
116 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
117 struct irq_chip *irqchip = irq_desc_get_chip(desc);
118 unsigned long stat;
119 int offset;
120
121 chained_irq_enter(irqchip, desc);
122
123 /*
124 * Dispatch the IRQs to the irqdomain of each A and B
125 * gpiochip irqdomains depending on what has fired.
126 * The tricky part is that the IRQ line is shared
127 * between bank A and B and each has their own gpiochip.
128 */
129 stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
130 for_each_set_bit(offset, &stat, 8)
131 generic_handle_domain_irq(epg->gc[0].gc.irq.domain,
132 offset);
133
134 stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
135 for_each_set_bit(offset, &stat, 8)
136 generic_handle_domain_irq(epg->gc[1].gc.irq.domain,
137 offset);
138
139 chained_irq_exit(irqchip, desc);
140 }
141
ep93xx_gpio_f_irq_handler(struct irq_desc * desc)142 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
143 {
144 /*
145 * map discontiguous hw irq range to continuous sw irq range:
146 *
147 * IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
148 */
149 struct irq_chip *irqchip = irq_desc_get_chip(desc);
150 unsigned int irq = irq_desc_get_irq(desc);
151 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
152 int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
153
154 chained_irq_enter(irqchip, desc);
155 generic_handle_irq(gpio_irq);
156 chained_irq_exit(irqchip, desc);
157 }
158
ep93xx_gpio_irq_ack(struct irq_data * d)159 static void ep93xx_gpio_irq_ack(struct irq_data *d)
160 {
161 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
162 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
163 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
164 int port_mask = BIT(d->irq & 7);
165
166 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
167 eic->int_type2 ^= port_mask; /* switch edge direction */
168 ep93xx_gpio_update_int_params(epg, eic);
169 }
170
171 writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
172 }
173
ep93xx_gpio_irq_mask_ack(struct irq_data * d)174 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
175 {
176 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
177 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
178 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
179 int port_mask = BIT(d->irq & 7);
180
181 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
182 eic->int_type2 ^= port_mask; /* switch edge direction */
183
184 eic->int_unmasked &= ~port_mask;
185 ep93xx_gpio_update_int_params(epg, eic);
186
187 writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
188 }
189
ep93xx_gpio_irq_mask(struct irq_data * d)190 static void ep93xx_gpio_irq_mask(struct irq_data *d)
191 {
192 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
193 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
194 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
195
196 eic->int_unmasked &= ~BIT(d->irq & 7);
197 ep93xx_gpio_update_int_params(epg, eic);
198 }
199
ep93xx_gpio_irq_unmask(struct irq_data * d)200 static void ep93xx_gpio_irq_unmask(struct irq_data *d)
201 {
202 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
203 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
204 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
205
206 eic->int_unmasked |= BIT(d->irq & 7);
207 ep93xx_gpio_update_int_params(epg, eic);
208 }
209
210 /*
211 * gpio_int_type1 controls whether the interrupt is level (0) or
212 * edge (1) triggered, while gpio_int_type2 controls whether it
213 * triggers on low/falling (0) or high/rising (1).
214 */
ep93xx_gpio_irq_type(struct irq_data * d,unsigned int type)215 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
216 {
217 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
218 struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
219 struct ep93xx_gpio *epg = gpiochip_get_data(gc);
220 int offset = d->irq & 7;
221 int port_mask = BIT(offset);
222 irq_flow_handler_t handler;
223
224 gc->direction_input(gc, offset);
225
226 switch (type) {
227 case IRQ_TYPE_EDGE_RISING:
228 eic->int_type1 |= port_mask;
229 eic->int_type2 |= port_mask;
230 handler = handle_edge_irq;
231 break;
232 case IRQ_TYPE_EDGE_FALLING:
233 eic->int_type1 |= port_mask;
234 eic->int_type2 &= ~port_mask;
235 handler = handle_edge_irq;
236 break;
237 case IRQ_TYPE_LEVEL_HIGH:
238 eic->int_type1 &= ~port_mask;
239 eic->int_type2 |= port_mask;
240 handler = handle_level_irq;
241 break;
242 case IRQ_TYPE_LEVEL_LOW:
243 eic->int_type1 &= ~port_mask;
244 eic->int_type2 &= ~port_mask;
245 handler = handle_level_irq;
246 break;
247 case IRQ_TYPE_EDGE_BOTH:
248 eic->int_type1 |= port_mask;
249 /* set initial polarity based on current input level */
250 if (gc->get(gc, offset))
251 eic->int_type2 &= ~port_mask; /* falling */
252 else
253 eic->int_type2 |= port_mask; /* rising */
254 handler = handle_edge_irq;
255 break;
256 default:
257 return -EINVAL;
258 }
259
260 irq_set_handler_locked(d, handler);
261
262 eic->int_enabled |= port_mask;
263
264 ep93xx_gpio_update_int_params(epg, eic);
265
266 return 0;
267 }
268
269 /*************************************************************************
270 * gpiolib interface for EP93xx on-chip GPIOs
271 *************************************************************************/
272 struct ep93xx_gpio_bank {
273 const char *label;
274 int data;
275 int dir;
276 int irq;
277 int base;
278 bool has_irq;
279 bool has_hierarchical_irq;
280 unsigned int irq_base;
281 };
282
283 #define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
284 { \
285 .label = _label, \
286 .data = _data, \
287 .dir = _dir, \
288 .irq = _irq, \
289 .base = _base, \
290 .has_irq = _has_irq, \
291 .has_hierarchical_irq = _has_hier, \
292 .irq_base = _irq_base, \
293 }
294
295 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
296 /* Bank A has 8 IRQs */
297 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, EP93XX_GPIO_A_IRQ_BASE),
298 /* Bank B has 8 IRQs */
299 EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, EP93XX_GPIO_B_IRQ_BASE),
300 EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
301 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
302 EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
303 /* Bank F has 8 IRQs */
304 EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, EP93XX_GPIO_F_IRQ_BASE),
305 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
306 EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
307 };
308
ep93xx_gpio_set_config(struct gpio_chip * gc,unsigned offset,unsigned long config)309 static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
310 unsigned long config)
311 {
312 u32 debounce;
313
314 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
315 return -ENOTSUPP;
316
317 debounce = pinconf_to_config_argument(config);
318 ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
319
320 return 0;
321 }
322
ep93xx_init_irq_chip(struct device * dev,struct irq_chip * ic)323 static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic)
324 {
325 ic->irq_ack = ep93xx_gpio_irq_ack;
326 ic->irq_mask_ack = ep93xx_gpio_irq_mask_ack;
327 ic->irq_mask = ep93xx_gpio_irq_mask;
328 ic->irq_unmask = ep93xx_gpio_irq_unmask;
329 ic->irq_set_type = ep93xx_gpio_irq_type;
330 }
331
ep93xx_gpio_add_bank(struct ep93xx_gpio_chip * egc,struct platform_device * pdev,struct ep93xx_gpio * epg,struct ep93xx_gpio_bank * bank)332 static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
333 struct platform_device *pdev,
334 struct ep93xx_gpio *epg,
335 struct ep93xx_gpio_bank *bank)
336 {
337 void __iomem *data = epg->base + bank->data;
338 void __iomem *dir = epg->base + bank->dir;
339 struct gpio_chip *gc = &egc->gc;
340 struct device *dev = &pdev->dev;
341 struct gpio_irq_chip *girq;
342 int err;
343
344 err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
345 if (err)
346 return err;
347
348 gc->label = bank->label;
349 gc->base = bank->base;
350
351 girq = &gc->irq;
352 if (bank->has_irq || bank->has_hierarchical_irq) {
353 struct irq_chip *ic;
354
355 gc->set_config = ep93xx_gpio_set_config;
356 egc->eic = devm_kcalloc(dev, 1,
357 sizeof(*egc->eic),
358 GFP_KERNEL);
359 if (!egc->eic)
360 return -ENOMEM;
361 egc->eic->irq_offset = bank->irq;
362 ic = &egc->eic->ic;
363 ic->name = devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", bank->label);
364 if (!ic->name)
365 return -ENOMEM;
366 ep93xx_init_irq_chip(dev, ic);
367 girq->chip = ic;
368 }
369
370 if (bank->has_irq) {
371 int ab_parent_irq = platform_get_irq(pdev, 0);
372
373 girq->parent_handler = ep93xx_gpio_ab_irq_handler;
374 girq->num_parents = 1;
375 girq->parents = devm_kcalloc(dev, girq->num_parents,
376 sizeof(*girq->parents),
377 GFP_KERNEL);
378 if (!girq->parents)
379 return -ENOMEM;
380 girq->default_type = IRQ_TYPE_NONE;
381 girq->handler = handle_level_irq;
382 girq->parents[0] = ab_parent_irq;
383 girq->first = bank->irq_base;
384 }
385
386 /* Only bank F has especially funky IRQ handling */
387 if (bank->has_hierarchical_irq) {
388 int gpio_irq;
389 int i;
390
391 /*
392 * FIXME: convert this to use hierarchical IRQ support!
393 * this requires fixing the root irqchip to be hierarchical.
394 */
395 girq->parent_handler = ep93xx_gpio_f_irq_handler;
396 girq->num_parents = 8;
397 girq->parents = devm_kcalloc(dev, girq->num_parents,
398 sizeof(*girq->parents),
399 GFP_KERNEL);
400 if (!girq->parents)
401 return -ENOMEM;
402 /* Pick resources 1..8 for these IRQs */
403 for (i = 0; i < girq->num_parents; i++) {
404 girq->parents[i] = platform_get_irq(pdev, i + 1);
405 gpio_irq = bank->irq_base + i;
406 irq_set_chip_data(gpio_irq, &epg->gc[5]);
407 irq_set_chip_and_handler(gpio_irq,
408 girq->chip,
409 handle_level_irq);
410 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
411 }
412 girq->default_type = IRQ_TYPE_NONE;
413 girq->handler = handle_level_irq;
414 girq->first = bank->irq_base;
415 }
416
417 return devm_gpiochip_add_data(dev, gc, epg);
418 }
419
ep93xx_gpio_probe(struct platform_device * pdev)420 static int ep93xx_gpio_probe(struct platform_device *pdev)
421 {
422 struct ep93xx_gpio *epg;
423 int i;
424
425 epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
426 if (!epg)
427 return -ENOMEM;
428
429 epg->base = devm_platform_ioremap_resource(pdev, 0);
430 if (IS_ERR(epg->base))
431 return PTR_ERR(epg->base);
432
433 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
434 struct ep93xx_gpio_chip *gc = &epg->gc[i];
435 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
436
437 if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
438 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
439 bank->label);
440 }
441
442 return 0;
443 }
444
445 static struct platform_driver ep93xx_gpio_driver = {
446 .driver = {
447 .name = "gpio-ep93xx",
448 },
449 .probe = ep93xx_gpio_probe,
450 };
451
ep93xx_gpio_init(void)452 static int __init ep93xx_gpio_init(void)
453 {
454 return platform_driver_register(&ep93xx_gpio_driver);
455 }
456 postcore_initcall(ep93xx_gpio_init);
457
458 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
459 "H Hartley Sweeten <hsweeten@visionengravers.com>");
460 MODULE_DESCRIPTION("EP93XX GPIO driver");
461 MODULE_LICENSE("GPL");
462
