1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * IXP4 timer driver
4 * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
5 *
6 * Based on arch/arm/mach-ixp4xx/common.c
7 * Copyright 2002 (C) Intel Corporation
8 * Copyright 2003-2004 (C) MontaVista, Software, Inc.
9 * Copyright (C) Deepak Saxena <dsaxena@plexity.net>
10 */
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/clockchips.h>
14 #include <linux/clocksource.h>
15 #include <linux/sched_clock.h>
16 #include <linux/slab.h>
17 #include <linux/bitops.h>
18 #include <linux/delay.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/platform_device.h>
22 /* Goes away with OF conversion */
23 #include <linux/platform_data/timer-ixp4xx.h>
24
25 /*
26 * Constants to make it easy to access Timer Control/Status registers
27 */
28 #define IXP4XX_OSTS_OFFSET 0x00 /* Continuous Timestamp */
29 #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
30 #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
31 #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
32 #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
33 #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
34
35 /*
36 * Timer register values and bit definitions
37 */
38 #define IXP4XX_OST_ENABLE 0x00000001
39 #define IXP4XX_OST_ONE_SHOT 0x00000002
40 /* Low order bits of reload value ignored */
41 #define IXP4XX_OST_RELOAD_MASK 0x00000003
42 #define IXP4XX_OST_DISABLED 0x00000000
43 #define IXP4XX_OSST_TIMER_1_PEND 0x00000001
44 #define IXP4XX_OSST_TIMER_2_PEND 0x00000002
45 #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
46 /* Remaining registers are for the watchdog and defined in the watchdog driver */
47
48 struct ixp4xx_timer {
49 void __iomem *base;
50 u32 latch;
51 struct clock_event_device clkevt;
52 #ifdef CONFIG_ARM
53 struct delay_timer delay_timer;
54 #endif
55 };
56
57 /*
58 * A local singleton used by sched_clock and delay timer reads, which are
59 * fast and stateless
60 */
61 static struct ixp4xx_timer *local_ixp4xx_timer;
62
63 static inline struct ixp4xx_timer *
to_ixp4xx_timer(struct clock_event_device * evt)64 to_ixp4xx_timer(struct clock_event_device *evt)
65 {
66 return container_of(evt, struct ixp4xx_timer, clkevt);
67 }
68
ixp4xx_read_timer(void)69 static unsigned long ixp4xx_read_timer(void)
70 {
71 return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
72 }
73
ixp4xx_read_sched_clock(void)74 static u64 notrace ixp4xx_read_sched_clock(void)
75 {
76 return ixp4xx_read_timer();
77 }
78
ixp4xx_clocksource_read(struct clocksource * c)79 static u64 ixp4xx_clocksource_read(struct clocksource *c)
80 {
81 return ixp4xx_read_timer();
82 }
83
ixp4xx_timer_interrupt(int irq,void * dev_id)84 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
85 {
86 struct ixp4xx_timer *tmr = dev_id;
87 struct clock_event_device *evt = &tmr->clkevt;
88
89 /* Clear Pending Interrupt */
90 __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
91 tmr->base + IXP4XX_OSST_OFFSET);
92
93 evt->event_handler(evt);
94
95 return IRQ_HANDLED;
96 }
97
ixp4xx_set_next_event(unsigned long cycles,struct clock_event_device * evt)98 static int ixp4xx_set_next_event(unsigned long cycles,
99 struct clock_event_device *evt)
100 {
101 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
102 u32 val;
103
104 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
105 /* Keep enable/oneshot bits */
106 val &= IXP4XX_OST_RELOAD_MASK;
107 __raw_writel((cycles & ~IXP4XX_OST_RELOAD_MASK) | val,
108 tmr->base + IXP4XX_OSRT1_OFFSET);
109
110 return 0;
111 }
112
ixp4xx_shutdown(struct clock_event_device * evt)113 static int ixp4xx_shutdown(struct clock_event_device *evt)
114 {
115 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
116 u32 val;
117
118 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
119 val &= ~IXP4XX_OST_ENABLE;
120 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
121
122 return 0;
123 }
124
ixp4xx_set_oneshot(struct clock_event_device * evt)125 static int ixp4xx_set_oneshot(struct clock_event_device *evt)
126 {
127 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
128
129 __raw_writel(IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT,
130 tmr->base + IXP4XX_OSRT1_OFFSET);
131
132 return 0;
133 }
134
ixp4xx_set_periodic(struct clock_event_device * evt)135 static int ixp4xx_set_periodic(struct clock_event_device *evt)
136 {
137 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
138 u32 val;
139
140 val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK;
141 val |= IXP4XX_OST_ENABLE;
142 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
143
144 return 0;
145 }
146
ixp4xx_resume(struct clock_event_device * evt)147 static int ixp4xx_resume(struct clock_event_device *evt)
148 {
149 struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
150 u32 val;
151
152 val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
153 val |= IXP4XX_OST_ENABLE;
154 __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
155
156 return 0;
157 }
158
159 /*
160 * IXP4xx timer tick
161 * We use OS timer1 on the CPU for the timer tick and the timestamp
162 * counter as a source of real clock ticks to account for missed jiffies.
163 */
ixp4xx_timer_register(void __iomem * base,int timer_irq,unsigned int timer_freq)164 static __init int ixp4xx_timer_register(void __iomem *base,
165 int timer_irq,
166 unsigned int timer_freq)
167 {
168 struct ixp4xx_timer *tmr;
169 int ret;
170
171 tmr = kzalloc(sizeof(*tmr), GFP_KERNEL);
172 if (!tmr)
173 return -ENOMEM;
174 tmr->base = base;
175
176 /*
177 * The timer register doesn't allow to specify the two least
178 * significant bits of the timeout value and assumes them being zero.
179 * So make sure the latch is the best value with the two least
180 * significant bits unset.
181 */
182 tmr->latch = DIV_ROUND_CLOSEST(timer_freq,
183 (IXP4XX_OST_RELOAD_MASK + 1) * HZ)
184 * (IXP4XX_OST_RELOAD_MASK + 1);
185
186 local_ixp4xx_timer = tmr;
187
188 /* Reset/disable counter */
189 __raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET);
190
191 /* Clear any pending interrupt on timer 1 */
192 __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
193 tmr->base + IXP4XX_OSST_OFFSET);
194
195 /* Reset time-stamp counter */
196 __raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET);
197
198 clocksource_mmio_init(NULL, "OSTS", timer_freq, 200, 32,
199 ixp4xx_clocksource_read);
200
201 tmr->clkevt.name = "ixp4xx timer1";
202 tmr->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
203 tmr->clkevt.rating = 200;
204 tmr->clkevt.set_state_shutdown = ixp4xx_shutdown;
205 tmr->clkevt.set_state_periodic = ixp4xx_set_periodic;
206 tmr->clkevt.set_state_oneshot = ixp4xx_set_oneshot;
207 tmr->clkevt.tick_resume = ixp4xx_resume;
208 tmr->clkevt.set_next_event = ixp4xx_set_next_event;
209 tmr->clkevt.cpumask = cpumask_of(0);
210 tmr->clkevt.irq = timer_irq;
211 ret = request_irq(timer_irq, ixp4xx_timer_interrupt,
212 IRQF_TIMER, "IXP4XX-TIMER1", tmr);
213 if (ret) {
214 pr_crit("no timer IRQ\n");
215 return -ENODEV;
216 }
217 clockevents_config_and_register(&tmr->clkevt, timer_freq,
218 0xf, 0xfffffffe);
219
220 sched_clock_register(ixp4xx_read_sched_clock, 32, timer_freq);
221
222 #ifdef CONFIG_ARM
223 /* Also use this timer for delays */
224 tmr->delay_timer.read_current_timer = ixp4xx_read_timer;
225 tmr->delay_timer.freq = timer_freq;
226 register_current_timer_delay(&tmr->delay_timer);
227 #endif
228
229 return 0;
230 }
231
232 static struct platform_device ixp4xx_watchdog_device = {
233 .name = "ixp4xx-watchdog",
234 .id = -1,
235 };
236
237 /*
238 * This probe gets called after the timer is already up and running. The main
239 * function on this platform is to spawn the watchdog device as a child.
240 */
ixp4xx_timer_probe(struct platform_device * pdev)241 static int ixp4xx_timer_probe(struct platform_device *pdev)
242 {
243 struct device *dev = &pdev->dev;
244
245 /* Pass the base address as platform data and nothing else */
246 ixp4xx_watchdog_device.dev.platform_data = local_ixp4xx_timer->base;
247 ixp4xx_watchdog_device.dev.parent = dev;
248 return platform_device_register(&ixp4xx_watchdog_device);
249 }
250
251 static const struct of_device_id ixp4xx_timer_dt_id[] = {
252 { .compatible = "intel,ixp4xx-timer", },
253 { /* sentinel */ },
254 };
255
256 static struct platform_driver ixp4xx_timer_driver = {
257 .probe = ixp4xx_timer_probe,
258 .driver = {
259 .name = "ixp4xx-timer",
260 .of_match_table = ixp4xx_timer_dt_id,
261 .suppress_bind_attrs = true,
262 },
263 };
264 builtin_platform_driver(ixp4xx_timer_driver);
265
266 /**
267 * ixp4xx_timer_setup() - Timer setup function to be called from boardfiles
268 * @timerbase: physical base of timer block
269 * @timer_irq: Linux IRQ number for the timer
270 * @timer_freq: Fixed frequency of the timer
271 */
ixp4xx_timer_setup(resource_size_t timerbase,int timer_irq,unsigned int timer_freq)272 void __init ixp4xx_timer_setup(resource_size_t timerbase,
273 int timer_irq,
274 unsigned int timer_freq)
275 {
276 void __iomem *base;
277
278 base = ioremap(timerbase, 0x100);
279 if (!base) {
280 pr_crit("IXP4xx: can't remap timer\n");
281 return;
282 }
283 ixp4xx_timer_register(base, timer_irq, timer_freq);
284 }
285 EXPORT_SYMBOL_GPL(ixp4xx_timer_setup);
286
287 #ifdef CONFIG_OF
ixp4xx_of_timer_init(struct device_node * np)288 static __init int ixp4xx_of_timer_init(struct device_node *np)
289 {
290 void __iomem *base;
291 int irq;
292 int ret;
293
294 base = of_iomap(np, 0);
295 if (!base) {
296 pr_crit("IXP4xx: can't remap timer\n");
297 return -ENODEV;
298 }
299
300 irq = irq_of_parse_and_map(np, 0);
301 if (irq <= 0) {
302 pr_err("Can't parse IRQ\n");
303 ret = -EINVAL;
304 goto out_unmap;
305 }
306
307 /* TODO: get some fixed clocks into the device tree */
308 ret = ixp4xx_timer_register(base, irq, 66666000);
309 if (ret)
310 goto out_unmap;
311 return 0;
312
313 out_unmap:
314 iounmap(base);
315 return ret;
316 }
317 TIMER_OF_DECLARE(ixp4xx, "intel,ixp4xx-timer", ixp4xx_of_timer_init);
318 #endif
319
