1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3/*
4 * Copyright 2019-2021 MNT Research GmbH
5 * Copyright 2021 Lucas Stach <dev@lynxeye.de>
6 */
7
8/dts-v1/;
9
10#include "imx8mq-nitrogen-som.dtsi"
11
12/ {
13	model = "MNT Reform 2";
14	compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
15
16	pcie1_refclk: clock-pcie1-refclk {
17		compatible = "fixed-clock";
18		#clock-cells = <0>;
19		clock-frequency = <100000000>;
20	};
21
22	reg_main_5v: regulator-main-5v {
23		compatible = "regulator-fixed";
24		regulator-name = "5V";
25		regulator-min-microvolt = <5000000>;
26		regulator-max-microvolt = <5000000>;
27	};
28
29	reg_main_3v3: regulator-main-3v3 {
30		compatible = "regulator-fixed";
31		regulator-name = "3V3";
32		regulator-min-microvolt = <3300000>;
33		regulator-max-microvolt = <3300000>;
34	};
35
36	reg_main_usb: regulator-main-usb {
37		compatible = "regulator-fixed";
38		regulator-name = "USB_PWR";
39		regulator-min-microvolt = <5000000>;
40		regulator-max-microvolt = <5000000>;
41		vin-supply = <&reg_main_5v>;
42	};
43
44	sound {
45		compatible = "fsl,imx-audio-wm8960";
46		audio-cpu = <&sai2>;
47		audio-codec = <&wm8960>;
48		audio-routing =
49			"Headphone Jack", "HP_L",
50			"Headphone Jack", "HP_R",
51			"Ext Spk", "SPK_LP",
52			"Ext Spk", "SPK_LN",
53			"Ext Spk", "SPK_RP",
54			"Ext Spk", "SPK_RN",
55			"LINPUT1", "Mic Jack",
56			"Mic Jack", "MICB",
57			"LINPUT2", "Line In Jack",
58			"RINPUT2", "Line In Jack";
59		model = "wm8960-audio";
60	};
61};
62
63&fec1 {
64	status = "okay";
65};
66
67&i2c3 {
68	pinctrl-names = "default";
69	pinctrl-0 = <&pinctrl_i2c3>;
70	status = "okay";
71
72	wm8960: codec@1a {
73		compatible = "wlf,wm8960";
74		reg = <0x1a>;
75		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
76		clock-names = "mclk";
77		#sound-dai-cells = <0>;
78	};
79
80	rtc@68 {
81		compatible = "nxp,pcf8523";
82		reg = <0x68>;
83	};
84};
85
86&pcie1 {
87	pinctrl-names = "default";
88	pinctrl-0 = <&pinctrl_pcie1>;
89	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
90	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
91		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
92		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
93		 <&pcie1_refclk>;
94	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
95	status = "okay";
96};
97
98&reg_1p8v {
99	vin-supply = <&reg_main_5v>;
100};
101
102&reg_snvs {
103	vin-supply = <&reg_main_5v>;
104};
105
106&reg_arm_dram {
107	vin-supply = <&reg_main_5v>;
108};
109
110&reg_dram_1p1v {
111	vin-supply = <&reg_main_5v>;
112};
113
114&reg_soc_gpu_vpu {
115	vin-supply = <&reg_main_5v>;
116};
117
118&sai2 {
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_sai2>;
121	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
122	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
123	assigned-clock-rates = <25000000>;
124	fsl,sai-mclk-direction-output;
125	fsl,sai-asynchronous;
126	status = "okay";
127};
128
129&snvs_rtc {
130	status = "disabled";
131};
132
133&uart2 {
134	pinctrl-names = "default";
135	pinctrl-0 = <&pinctrl_uart2>;
136	status = "okay";
137};
138
139&usb3_phy0 {
140	vbus-supply = <&reg_main_usb>;
141	status = "okay";
142};
143
144&usb3_phy1 {
145	vbus-supply = <&reg_main_usb>;
146	status = "okay";
147};
148
149&usb_dwc3_0 {
150	dr_mode = "host";
151	status = "okay";
152};
153
154&usb_dwc3_1 {
155	dr_mode = "host";
156	status = "okay";
157};
158
159&usdhc2 {
160	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
161	assigned-clock-rates = <200000000>;
162	pinctrl-names = "default";
163	pinctrl-0 = <&pinctrl_usdhc2>;
164	vqmmc-supply = <&reg_main_3v3>;
165	vmmc-supply = <&reg_main_3v3>;
166	bus-width = <4>;
167	status = "okay";
168};
169
170&iomuxc {
171	pinctrl_i2c3: i2c3grp {
172		fsl,pins = <
173			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
174			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
175		>;
176	};
177
178	pinctrl_pcie1: pcie1grp {
179		fsl,pins = <
180			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16
181		>;
182	};
183
184	pinctrl_sai2: sai2grp {
185		fsl,pins = <
186			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6
187			MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC		0xd6
188			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6
189			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6
190			MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK		0xd6
191			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6
192			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6
193		>;
194	};
195
196	pinctrl_uart2: uart2grp {
197		fsl,pins = <
198			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45
199			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x45
200		>;
201	};
202
203	pinctrl_usdhc2: usdhc2grp {
204		fsl,pins = <
205			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
206			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
207			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
208			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
209			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
210			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
211		>;
212	};
213};
214