1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (C) 2019 Kontron Electronics GmbH
4 */
5
6#include "imx8mm.dtsi"
7
8/ {
9	model = "Kontron i.MX8MM N801X SoM";
10	compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
11
12	memory@40000000 {
13		device_type = "memory";
14		/*
15		 * There are multiple SoM flavors with different DDR sizes.
16		 * The smallest is 1GB. For larger sizes the bootloader will
17		 * update the reg property.
18		 */
19		reg = <0x0 0x40000000 0 0x80000000>;
20	};
21
22	chosen {
23		stdout-path = &uart3;
24	};
25};
26
27&A53_0 {
28	cpu-supply = <&reg_vdd_arm>;
29};
30
31&A53_1 {
32	cpu-supply = <&reg_vdd_arm>;
33};
34
35&A53_2 {
36	cpu-supply = <&reg_vdd_arm>;
37};
38
39&A53_3 {
40	cpu-supply = <&reg_vdd_arm>;
41};
42
43&ddrc {
44	operating-points-v2 = <&ddrc_opp_table>;
45
46	ddrc_opp_table: opp-table {
47		compatible = "operating-points-v2";
48
49		opp-25M {
50			opp-hz = /bits/ 64 <25000000>;
51		};
52
53		opp-100M {
54			opp-hz = /bits/ 64 <100000000>;
55		};
56
57		opp-750M {
58			opp-hz = /bits/ 64 <750000000>;
59		};
60	};
61};
62
63&ecspi1 {
64	pinctrl-names = "default";
65	pinctrl-0 = <&pinctrl_ecspi1>;
66	cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
67	status = "okay";
68
69	spi-flash@0 {
70		compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
71		spi-max-frequency = <80000000>;
72		reg = <0>;
73	};
74};
75
76&i2c1 {
77	clock-frequency = <400000>;
78	pinctrl-names = "default";
79	pinctrl-0 = <&pinctrl_i2c1>;
80	status = "okay";
81
82	pca9450: pmic@25 {
83		compatible = "nxp,pca9450a";
84		reg = <0x25>;
85		pinctrl-names = "default";
86		pinctrl-0 = <&pinctrl_pmic>;
87		interrupt-parent = <&gpio1>;
88		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
89
90		regulators {
91			reg_vdd_soc: BUCK1 {
92				regulator-name = "buck1";
93				regulator-min-microvolt = <800000>;
94				regulator-max-microvolt = <850000>;
95				regulator-boot-on;
96				regulator-always-on;
97				regulator-ramp-delay = <3125>;
98				nxp,dvs-run-voltage = <850000>;
99				nxp,dvs-standby-voltage = <800000>;
100			};
101
102			reg_vdd_arm: BUCK2 {
103				regulator-name = "buck2";
104				regulator-min-microvolt = <850000>;
105				regulator-max-microvolt = <950000>;
106				regulator-boot-on;
107				regulator-always-on;
108				regulator-ramp-delay = <3125>;
109				nxp,dvs-run-voltage = <950000>;
110				nxp,dvs-standby-voltage = <850000>;
111			};
112
113			reg_vdd_dram: BUCK3 {
114				regulator-name = "buck3";
115				regulator-min-microvolt = <850000>;
116				regulator-max-microvolt = <950000>;
117				regulator-boot-on;
118				regulator-always-on;
119			};
120
121			reg_vdd_3v3: BUCK4 {
122				regulator-name = "buck4";
123				regulator-min-microvolt = <3300000>;
124				regulator-max-microvolt = <3300000>;
125				regulator-boot-on;
126				regulator-always-on;
127			};
128
129			reg_vdd_1v8: BUCK5 {
130				regulator-name = "buck5";
131				regulator-min-microvolt = <1800000>;
132				regulator-max-microvolt = <1800000>;
133				regulator-boot-on;
134				regulator-always-on;
135			};
136
137			reg_nvcc_dram: BUCK6 {
138				regulator-name = "buck6";
139				regulator-min-microvolt = <1100000>;
140				regulator-max-microvolt = <1100000>;
141				regulator-boot-on;
142				regulator-always-on;
143			};
144
145			reg_nvcc_snvs: LDO1 {
146				regulator-name = "ldo1";
147				regulator-min-microvolt = <1800000>;
148				regulator-max-microvolt = <1800000>;
149				regulator-boot-on;
150				regulator-always-on;
151			};
152
153			reg_vdd_snvs: LDO2 {
154				regulator-name = "ldo2";
155				regulator-min-microvolt = <800000>;
156				regulator-max-microvolt = <900000>;
157				regulator-boot-on;
158				regulator-always-on;
159			};
160
161			reg_vdda: LDO3 {
162				regulator-name = "ldo3";
163				regulator-min-microvolt = <1800000>;
164				regulator-max-microvolt = <1800000>;
165				regulator-boot-on;
166				regulator-always-on;
167			};
168
169			reg_vdd_phy: LDO4 {
170				regulator-name = "ldo4";
171				regulator-min-microvolt = <900000>;
172				regulator-max-microvolt = <900000>;
173				regulator-boot-on;
174				regulator-always-on;
175			};
176
177			reg_nvcc_sd: LDO5 {
178				regulator-name = "ldo5";
179				regulator-min-microvolt = <1800000>;
180				regulator-max-microvolt = <3300000>;
181			};
182		};
183	};
184};
185
186&uart3 { /* console */
187	pinctrl-names = "default";
188	pinctrl-0 = <&pinctrl_uart3>;
189	status = "okay";
190};
191
192&usdhc1 {
193	pinctrl-names = "default", "state_100mhz", "state_200mhz";
194	pinctrl-0 = <&pinctrl_usdhc1>;
195	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
196	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
197	vmmc-supply = <&reg_vdd_3v3>;
198	vqmmc-supply = <&reg_vdd_1v8>;
199	bus-width = <8>;
200	non-removable;
201	status = "okay";
202};
203
204&wdog1 {
205	pinctrl-names = "default";
206	pinctrl-0 = <&pinctrl_wdog>;
207	fsl,ext-reset-output;
208	status = "okay";
209};
210
211&iomuxc {
212	pinctrl_ecspi1: ecspi1grp {
213		fsl,pins = <
214			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82
215			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82
216			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82
217			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x19
218		>;
219	};
220
221	pinctrl_i2c1: i2c1grp {
222		fsl,pins = <
223			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
224			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
225		>;
226	};
227
228	pinctrl_pmic: pmicgrp {
229		fsl,pins = <
230			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x141
231		>;
232	};
233
234	pinctrl_uart3: uart3grp {
235		fsl,pins = <
236			MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x140
237			MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x140
238		>;
239	};
240
241	pinctrl_usdhc1: usdhc1grp {
242		fsl,pins = <
243			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x190
244			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d0
245			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d0
246			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d0
247			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d0
248			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d0
249			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d0
250			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d0
251			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d0
252			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d0
253			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019
254			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x190
255		>;
256	};
257
258	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
259		fsl,pins = <
260			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x194
261			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d4
262			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d4
263			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d4
264			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d4
265			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d4
266			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d4
267			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d4
268			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d4
269			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d4
270			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019
271			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x194
272		>;
273	};
274
275	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
276		fsl,pins = <
277			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK			0x196
278			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD			0x1d6
279			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0		0x1d6
280			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1		0x1d6
281			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2		0x1d6
282			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3		0x1d6
283			MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4		0x1d6
284			MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5		0x1d6
285			MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6		0x1d6
286			MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7		0x1d6
287			MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0x019
288			MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE		0x196
289		>;
290	};
291
292	pinctrl_wdog: wdoggrp {
293		fsl,pins = <
294			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
295		>;
296	};
297};
298