1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SDX55 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2020, Linaro Ltd. 7 */ 8 9#include <dt-bindings/clock/qcom,gcc-sdx55.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interconnect/qcom,sdx55.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; 20 interrupt-parent = <&intc>; 21 22 memory { 23 device_type = "memory"; 24 reg = <0 0>; 25 }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32000>; 39 }; 40 41 nand_clk_dummy: nand-clk-dummy { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <32000>; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a7"; 55 reg = <0x0>; 56 enable-method = "psci"; 57 clocks = <&apcs>; 58 power-domains = <&rpmhpd SDX55_CX>; 59 power-domain-names = "rpmhpd"; 60 operating-points-v2 = <&cpu_opp_table>; 61 }; 62 }; 63 64 cpu_opp_table: cpu-opp-table { 65 compatible = "operating-points-v2"; 66 opp-shared; 67 68 opp-345600000 { 69 opp-hz = /bits/ 64 <345600000>; 70 required-opps = <&rpmhpd_opp_low_svs>; 71 }; 72 73 opp-576000000 { 74 opp-hz = /bits/ 64 <576000000>; 75 required-opps = <&rpmhpd_opp_svs>; 76 }; 77 78 opp-1094400000 { 79 opp-hz = /bits/ 64 <1094400000>; 80 required-opps = <&rpmhpd_opp_nom>; 81 }; 82 83 opp-1555200000 { 84 opp-hz = /bits/ 64 <1555200000>; 85 required-opps = <&rpmhpd_opp_turbo>; 86 }; 87 }; 88 89 firmware { 90 scm { 91 compatible = "qcom,scm-sdx55", "qcom,scm"; 92 }; 93 }; 94 95 psci { 96 compatible = "arm,psci-1.0"; 97 method = "smc"; 98 }; 99 100 reserved-memory { 101 #address-cells = <1>; 102 #size-cells = <1>; 103 ranges; 104 105 hyp_mem: memory@8fc00000 { 106 no-map; 107 reg = <0x8fc00000 0x80000>; 108 }; 109 110 ac_db_mem: memory@8fc80000 { 111 no-map; 112 reg = <0x8fc80000 0x40000>; 113 }; 114 115 secdata_mem: memory@8fcfd000 { 116 no-map; 117 reg = <0x8fcfd000 0x1000>; 118 }; 119 120 sbl_mem: memory@8fd00000 { 121 no-map; 122 reg = <0x8fd00000 0x100000>; 123 }; 124 125 aop_image: memory@8fe00000 { 126 no-map; 127 reg = <0x8fe00000 0x20000>; 128 }; 129 130 aop_cmd_db: memory@8fe20000 { 131 compatible = "qcom,cmd-db"; 132 reg = <0x8fe20000 0x20000>; 133 no-map; 134 }; 135 136 smem_mem: memory@8fe40000 { 137 no-map; 138 reg = <0x8fe40000 0xc0000>; 139 }; 140 141 tz_mem: memory@8ff00000 { 142 no-map; 143 reg = <0x8ff00000 0x100000>; 144 }; 145 146 tz_apps_mem: memory@90000000 { 147 no-map; 148 reg = <0x90000000 0x500000>; 149 }; 150 }; 151 152 smem { 153 compatible = "qcom,smem"; 154 memory-region = <&smem_mem>; 155 hwlocks = <&tcsr_mutex 3>; 156 }; 157 158 smp2p-mpss { 159 compatible = "qcom,smp2p"; 160 qcom,smem = <435>, <428>; 161 interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; 162 mboxes = <&apcs 14>; 163 qcom,local-pid = <0>; 164 qcom,remote-pid = <1>; 165 166 modem_smp2p_out: master-kernel { 167 qcom,entry-name = "master-kernel"; 168 #qcom,smem-state-cells = <1>; 169 }; 170 171 modem_smp2p_in: slave-kernel { 172 qcom,entry-name = "slave-kernel"; 173 interrupt-controller; 174 #interrupt-cells = <2>; 175 }; 176 177 ipa_smp2p_out: ipa-ap-to-modem { 178 qcom,entry-name = "ipa"; 179 #qcom,smem-state-cells = <1>; 180 }; 181 182 ipa_smp2p_in: ipa-modem-to-ap { 183 qcom,entry-name = "ipa"; 184 interrupt-controller; 185 #interrupt-cells = <2>; 186 }; 187 }; 188 189 soc: soc { 190 #address-cells = <1>; 191 #size-cells = <1>; 192 ranges; 193 compatible = "simple-bus"; 194 195 gcc: clock-controller@100000 { 196 compatible = "qcom,gcc-sdx55"; 197 reg = <0x100000 0x1f0000>; 198 #clock-cells = <1>; 199 #reset-cells = <1>; 200 #power-domain-cells = <1>; 201 clock-names = "bi_tcxo", "sleep_clk"; 202 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 203 }; 204 205 blsp1_uart3: serial@831000 { 206 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 207 reg = <0x00831000 0x200>; 208 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>; 209 clocks = <&gcc 30>, 210 <&gcc 9>; 211 clock-names = "core", "iface"; 212 status = "disabled"; 213 }; 214 215 usb_hsphy: phy@ff4000 { 216 compatible = "qcom,usb-snps-hs-7nm-phy"; 217 reg = <0x00ff4000 0x114>; 218 status = "disabled"; 219 #phy-cells = <0>; 220 221 clocks = <&rpmhcc RPMH_CXO_CLK>; 222 clock-names = "ref"; 223 224 resets = <&gcc GCC_QUSB2PHY_BCR>; 225 }; 226 227 usb_qmpphy: phy@ff6000 { 228 compatible = "qcom,sdx55-qmp-usb3-uni-phy"; 229 reg = <0x00ff6000 0x1c0>; 230 status = "disabled"; 231 #clock-cells = <1>; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 ranges; 235 236 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 237 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 238 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 239 clock-names = "aux", "cfg_ahb", "ref"; 240 241 resets = <&gcc GCC_USB3PHY_PHY_BCR>, 242 <&gcc GCC_USB3_PHY_BCR>; 243 reset-names = "phy", "common"; 244 245 usb_ssphy: phy@ff6200 { 246 reg = <0x00ff6200 0x170>, 247 <0x00ff6400 0x200>, 248 <0x00ff6800 0x800>; 249 #phy-cells = <0>; 250 #clock-cells = <0>; 251 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 252 clock-names = "pipe0"; 253 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 254 }; 255 }; 256 257 mc_virt: interconnect@1100000 { 258 compatible = "qcom,sdx55-mc-virt"; 259 reg = <0x01100000 0x400000>; 260 #interconnect-cells = <1>; 261 qcom,bcm-voters = <&apps_bcm_voter>; 262 }; 263 264 mem_noc: interconnect@9680000 { 265 compatible = "qcom,sdx55-mem-noc"; 266 reg = <0x09680000 0x40000>; 267 #interconnect-cells = <1>; 268 qcom,bcm-voters = <&apps_bcm_voter>; 269 }; 270 271 system_noc: interconnect@162c000 { 272 compatible = "qcom,sdx55-system-noc"; 273 reg = <0x0162c000 0x31200>; 274 #interconnect-cells = <1>; 275 qcom,bcm-voters = <&apps_bcm_voter>; 276 }; 277 278 ipa_virt: interconnect@1e00000 { 279 compatible = "qcom,sdx55-ipa-virt"; 280 reg = <0x01e00000 0x100000>; 281 #interconnect-cells = <1>; 282 qcom,bcm-voters = <&apps_bcm_voter>; 283 }; 284 285 qpic_bam: dma-controller@1b04000 { 286 compatible = "qcom,bam-v1.7.0"; 287 reg = <0x01b04000 0x1c000>; 288 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&rpmhcc RPMH_QPIC_CLK>; 290 clock-names = "bam_clk"; 291 #dma-cells = <1>; 292 qcom,ee = <0>; 293 qcom,controlled-remotely; 294 status = "disabled"; 295 }; 296 297 qpic_nand: nand-controller@1b30000 { 298 compatible = "qcom,sdx55-nand"; 299 reg = <0x01b30000 0x10000>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 clocks = <&rpmhcc RPMH_QPIC_CLK>, 303 <&nand_clk_dummy>; 304 clock-names = "core", "aon"; 305 306 dmas = <&qpic_bam 0>, 307 <&qpic_bam 1>, 308 <&qpic_bam 2>; 309 dma-names = "tx", "rx", "cmd"; 310 status = "disabled"; 311 }; 312 313 ipa: ipa@1e40000 { 314 compatible = "qcom,sdx55-ipa"; 315 316 iommus = <&apps_smmu 0x5e0 0x0>, 317 <&apps_smmu 0x5e2 0x0>; 318 reg = <0x1e40000 0x7000>, 319 <0x1e50000 0x4b20>, 320 <0x1e04000 0x2c000>; 321 reg-names = "ipa-reg", 322 "ipa-shared", 323 "gsi"; 324 325 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 326 <&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 327 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 328 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 329 interrupt-names = "ipa", 330 "gsi", 331 "ipa-clock-query", 332 "ipa-setup-ready"; 333 334 clocks = <&rpmhcc RPMH_IPA_CLK>; 335 clock-names = "core"; 336 337 interconnects = <&system_noc MASTER_IPA &system_noc SLAVE_SNOC_MEM_NOC_GC>, 338 <&mem_noc MASTER_SNOC_GC_MEM_NOC &mc_virt SLAVE_EBI_CH0>, 339 <&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>, 340 <&mem_noc MASTER_AMPSS_M0 &system_noc SLAVE_IPA_CFG>; 341 interconnect-names = "memory-a", 342 "memory-b", 343 "imem", 344 "config"; 345 346 qcom,smem-states = <&ipa_smp2p_out 0>, 347 <&ipa_smp2p_out 1>; 348 qcom,smem-state-names = "ipa-clock-enabled-valid", 349 "ipa-clock-enabled"; 350 351 status = "disabled"; 352 }; 353 354 tcsr_mutex: hwlock@1f40000 { 355 compatible = "qcom,tcsr-mutex"; 356 reg = <0x01f40000 0x40000>; 357 #hwlock-cells = <1>; 358 }; 359 360 sdhc_1: sdhci@8804000 { 361 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; 362 reg = <0x08804000 0x1000>; 363 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 365 interrupt-names = "hc_irq", "pwr_irq"; 366 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 367 <&gcc GCC_SDCC1_APPS_CLK>; 368 clock-names = "iface", "core"; 369 status = "disabled"; 370 }; 371 372 remoteproc_mpss: remoteproc@4080000 { 373 compatible = "qcom,sdx55-mpss-pas"; 374 reg = <0x04080000 0x4040>; 375 376 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 377 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 378 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 379 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 380 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 381 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 382 interrupt-names = "wdog", "fatal", "ready", "handover", 383 "stop-ack", "shutdown-ack"; 384 385 clocks = <&rpmhcc RPMH_CXO_CLK>; 386 clock-names = "xo"; 387 388 power-domains = <&rpmhpd SDX55_CX>, 389 <&rpmhpd SDX55_MSS>; 390 power-domain-names = "cx", "mss"; 391 392 qcom,smem-states = <&modem_smp2p_out 0>; 393 qcom,smem-state-names = "stop"; 394 395 status = "disabled"; 396 397 glink-edge { 398 interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>; 399 label = "mpss"; 400 qcom,remote-pid = <1>; 401 mboxes = <&apcs 15>; 402 }; 403 }; 404 405 usb: usb@a6f8800 { 406 compatible = "qcom,sdx55-dwc3", "qcom,dwc3"; 407 reg = <0x0a6f8800 0x400>; 408 status = "disabled"; 409 #address-cells = <1>; 410 #size-cells = <1>; 411 ranges; 412 413 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, 414 <&gcc GCC_USB30_MASTER_CLK>, 415 <&gcc GCC_USB30_MSTR_AXI_CLK>, 416 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 417 <&gcc GCC_USB30_SLEEP_CLK>; 418 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 419 "sleep"; 420 421 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 422 <&gcc GCC_USB30_MASTER_CLK>; 423 assigned-clock-rates = <19200000>, <200000000>; 424 425 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "hs_phy_irq", "ss_phy_irq", 430 "dm_hs_phy_irq", "dp_hs_phy_irq"; 431 432 power-domains = <&gcc USB30_GDSC>; 433 434 resets = <&gcc GCC_USB30_BCR>; 435 436 usb_dwc3: dwc3@a600000 { 437 compatible = "snps,dwc3"; 438 reg = <0x0a600000 0xcd00>; 439 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 440 iommus = <&apps_smmu 0x1a0 0x0>; 441 snps,dis_u2_susphy_quirk; 442 snps,dis_enblslpm_quirk; 443 phys = <&usb_hsphy>, <&usb_ssphy>; 444 phy-names = "usb2-phy", "usb3-phy"; 445 }; 446 }; 447 448 pdc: interrupt-controller@b210000 { 449 compatible = "qcom,sdx55-pdc", "qcom,pdc"; 450 reg = <0x0b210000 0x30000>; 451 qcom,pdc-ranges = <0 179 52>; 452 #interrupt-cells = <3>; 453 interrupt-parent = <&intc>; 454 interrupt-controller; 455 }; 456 457 restart@c264000 { 458 compatible = "qcom,pshold"; 459 reg = <0x0c264000 0x1000>; 460 }; 461 462 spmi_bus: qcom,spmi@c440000 { 463 compatible = "qcom,spmi-pmic-arb"; 464 reg = <0x0c440000 0x0000d00>, 465 <0x0c600000 0x2000000>, 466 <0x0e600000 0x0100000>, 467 <0x0e700000 0x00a0000>, 468 <0x0c40a000 0x0000700>; 469 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 470 interrupt-names = "periph_irq"; 471 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 472 qcom,ee = <0>; 473 qcom,channel = <0>; 474 #address-cells = <2>; 475 #size-cells = <0>; 476 interrupt-controller; 477 #interrupt-cells = <4>; 478 cell-index = <0>; 479 }; 480 481 tlmm: pinctrl@f100000 { 482 compatible = "qcom,sdx55-pinctrl"; 483 reg = <0xf100000 0x300000>; 484 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 485 gpio-controller; 486 #gpio-cells = <2>; 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 }; 490 491 imem@1468f000 { 492 compatible = "simple-mfd"; 493 reg = <0x1468f000 0x1000>; 494 495 #address-cells = <1>; 496 #size-cells = <1>; 497 498 ranges = <0x0 0x1468f000 0x1000>; 499 500 pil-reloc@94c { 501 compatible = "qcom,pil-reloc-info"; 502 reg = <0x94c 0x200>; 503 }; 504 }; 505 506 apps_smmu: iommu@15000000 { 507 compatible = "qcom,sdx55-smmu-500", "arm,mmu-500"; 508 reg = <0x15000000 0x20000>; 509 #iommu-cells = <2>; 510 #global-interrupts = <1>; 511 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 528 }; 529 530 intc: interrupt-controller@17800000 { 531 compatible = "qcom,msm-qgic2"; 532 interrupt-controller; 533 interrupt-parent = <&intc>; 534 #interrupt-cells = <3>; 535 reg = <0x17800000 0x1000>, 536 <0x17802000 0x1000>; 537 }; 538 539 a7pll: clock@17808000 { 540 compatible = "qcom,sdx55-a7pll"; 541 reg = <0x17808000 0x1000>; 542 clocks = <&rpmhcc RPMH_CXO_CLK>; 543 clock-names = "bi_tcxo"; 544 #clock-cells = <0>; 545 }; 546 547 apcs: mailbox@17810000 { 548 compatible = "qcom,sdx55-apcs-gcc", "syscon"; 549 reg = <0x17810000 0x2000>; 550 #mbox-cells = <1>; 551 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>; 552 clock-names = "ref", "pll", "aux"; 553 #clock-cells = <0>; 554 }; 555 556 watchdog@17817000 { 557 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt"; 558 reg = <0x17817000 0x1000>; 559 clocks = <&sleep_clk>; 560 }; 561 562 timer@17820000 { 563 #address-cells = <1>; 564 #size-cells = <1>; 565 ranges; 566 compatible = "arm,armv7-timer-mem"; 567 reg = <0x17820000 0x1000>; 568 clock-frequency = <19200000>; 569 570 frame@17821000 { 571 frame-number = <0>; 572 interrupts = <GIC_SPI 7 0x4>, 573 <GIC_SPI 6 0x4>; 574 reg = <0x17821000 0x1000>, 575 <0x17822000 0x1000>; 576 }; 577 578 frame@17823000 { 579 frame-number = <1>; 580 interrupts = <GIC_SPI 8 0x4>; 581 reg = <0x17823000 0x1000>; 582 status = "disabled"; 583 }; 584 585 frame@17824000 { 586 frame-number = <2>; 587 interrupts = <GIC_SPI 9 0x4>; 588 reg = <0x17824000 0x1000>; 589 status = "disabled"; 590 }; 591 592 frame@17825000 { 593 frame-number = <3>; 594 interrupts = <GIC_SPI 10 0x4>; 595 reg = <0x17825000 0x1000>; 596 status = "disabled"; 597 }; 598 599 frame@17826000 { 600 frame-number = <4>; 601 interrupts = <GIC_SPI 11 0x4>; 602 reg = <0x17826000 0x1000>; 603 status = "disabled"; 604 }; 605 606 frame@17827000 { 607 frame-number = <5>; 608 interrupts = <GIC_SPI 12 0x4>; 609 reg = <0x17827000 0x1000>; 610 status = "disabled"; 611 }; 612 613 frame@17828000 { 614 frame-number = <6>; 615 interrupts = <GIC_SPI 13 0x4>; 616 reg = <0x17828000 0x1000>; 617 status = "disabled"; 618 }; 619 620 frame@17829000 { 621 frame-number = <7>; 622 interrupts = <GIC_SPI 14 0x4>; 623 reg = <0x17829000 0x1000>; 624 status = "disabled"; 625 }; 626 }; 627 628 apps_rsc: rsc@17840000 { 629 compatible = "qcom,rpmh-rsc"; 630 reg = <0x17830000 0x10000>, <0x17840000 0x10000>; 631 reg-names = "drv-0", "drv-1"; 632 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 634 qcom,tcs-offset = <0xd00>; 635 qcom,drv-id = <1>; 636 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>, 637 <WAKE_TCS 2>, <CONTROL_TCS 1>; 638 639 rpmhcc: clock-controller { 640 compatible = "qcom,sdx55-rpmh-clk"; 641 #clock-cells = <1>; 642 clock-names = "xo"; 643 clocks = <&xo_board>; 644 }; 645 646 rpmhpd: power-controller { 647 compatible = "qcom,sdx55-rpmhpd"; 648 #power-domain-cells = <1>; 649 operating-points-v2 = <&rpmhpd_opp_table>; 650 651 rpmhpd_opp_table: opp-table { 652 compatible = "operating-points-v2"; 653 654 rpmhpd_opp_ret: opp1 { 655 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 656 }; 657 658 rpmhpd_opp_min_svs: opp2 { 659 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 660 }; 661 662 rpmhpd_opp_low_svs: opp3 { 663 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 664 }; 665 666 rpmhpd_opp_svs: opp4 { 667 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 668 }; 669 670 rpmhpd_opp_svs_l1: opp5 { 671 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 672 }; 673 674 rpmhpd_opp_nom: opp6 { 675 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 676 }; 677 678 rpmhpd_opp_nom_l1: opp7 { 679 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 680 }; 681 682 rpmhpd_opp_nom_l2: opp8 { 683 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 684 }; 685 686 rpmhpd_opp_turbo: opp9 { 687 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 688 }; 689 690 rpmhpd_opp_turbo_l1: opp10 { 691 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 692 }; 693 }; 694 }; 695 696 apps_bcm_voter: bcm_voter { 697 compatible = "qcom,bcm-voter"; 698 }; 699 }; 700 }; 701 702 timer { 703 compatible = "arm,armv7-timer"; 704 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 705 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 706 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 707 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 708 clock-frequency = <19200000>; 709 }; 710}; 711
