1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mfd/qcom-rpm.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 8#include <dt-bindings/clock/qcom,lcc-ipq806x.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/reset/qcom,gcc-ipq806x.h> 11#include <dt-bindings/soc/qcom,gsbi.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Qualcomm IPQ8064"; 18 compatible = "qcom,ipq8064"; 19 interrupt-parent = <&intc>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "qcom,krait"; 27 enable-method = "qcom,kpss-acc-v1"; 28 device_type = "cpu"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 qcom,acc = <&acc0>; 32 qcom,saw = <&saw0>; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "qcom,krait"; 37 enable-method = "qcom,kpss-acc-v1"; 38 device_type = "cpu"; 39 reg = <1>; 40 next-level-cache = <&L2>; 41 qcom,acc = <&acc1>; 42 qcom,saw = <&saw1>; 43 }; 44 45 L2: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 }; 49 }; 50 51 thermal-zones { 52 tsens_tz_sensor0 { 53 polling-delay-passive = <0>; 54 polling-delay = <0>; 55 thermal-sensors = <&tsens 0>; 56 57 trips { 58 cpu-critical { 59 temperature = <105000>; 60 hysteresis = <2000>; 61 type = "critical"; 62 }; 63 64 cpu-hot { 65 temperature = <95000>; 66 hysteresis = <2000>; 67 type = "hot"; 68 }; 69 }; 70 }; 71 72 tsens_tz_sensor1 { 73 polling-delay-passive = <0>; 74 polling-delay = <0>; 75 thermal-sensors = <&tsens 1>; 76 77 trips { 78 cpu-critical { 79 temperature = <105000>; 80 hysteresis = <2000>; 81 type = "critical"; 82 }; 83 84 cpu-hot { 85 temperature = <95000>; 86 hysteresis = <2000>; 87 type = "hot"; 88 }; 89 }; 90 }; 91 92 tsens_tz_sensor2 { 93 polling-delay-passive = <0>; 94 polling-delay = <0>; 95 thermal-sensors = <&tsens 2>; 96 97 trips { 98 cpu-critical { 99 temperature = <105000>; 100 hysteresis = <2000>; 101 type = "critical"; 102 }; 103 104 cpu-hot { 105 temperature = <95000>; 106 hysteresis = <2000>; 107 type = "hot"; 108 }; 109 }; 110 }; 111 112 tsens_tz_sensor3 { 113 polling-delay-passive = <0>; 114 polling-delay = <0>; 115 thermal-sensors = <&tsens 3>; 116 117 trips { 118 cpu-critical { 119 temperature = <105000>; 120 hysteresis = <2000>; 121 type = "critical"; 122 }; 123 124 cpu-hot { 125 temperature = <95000>; 126 hysteresis = <2000>; 127 type = "hot"; 128 }; 129 }; 130 }; 131 132 tsens_tz_sensor4 { 133 polling-delay-passive = <0>; 134 polling-delay = <0>; 135 thermal-sensors = <&tsens 4>; 136 137 trips { 138 cpu-critical { 139 temperature = <105000>; 140 hysteresis = <2000>; 141 type = "critical"; 142 }; 143 144 cpu-hot { 145 temperature = <95000>; 146 hysteresis = <2000>; 147 type = "hot"; 148 }; 149 }; 150 }; 151 152 tsens_tz_sensor5 { 153 polling-delay-passive = <0>; 154 polling-delay = <0>; 155 thermal-sensors = <&tsens 5>; 156 157 trips { 158 cpu-critical { 159 temperature = <105000>; 160 hysteresis = <2000>; 161 type = "critical"; 162 }; 163 164 cpu-hot { 165 temperature = <95000>; 166 hysteresis = <2000>; 167 type = "hot"; 168 }; 169 }; 170 }; 171 172 tsens_tz_sensor6 { 173 polling-delay-passive = <0>; 174 polling-delay = <0>; 175 thermal-sensors = <&tsens 6>; 176 177 trips { 178 cpu-critical { 179 temperature = <105000>; 180 hysteresis = <2000>; 181 type = "critical"; 182 }; 183 184 cpu-hot { 185 temperature = <95000>; 186 hysteresis = <2000>; 187 type = "hot"; 188 }; 189 }; 190 }; 191 192 tsens_tz_sensor7 { 193 polling-delay-passive = <0>; 194 polling-delay = <0>; 195 thermal-sensors = <&tsens 7>; 196 197 trips { 198 cpu-critical { 199 temperature = <105000>; 200 hysteresis = <2000>; 201 type = "critical"; 202 }; 203 204 cpu-hot { 205 temperature = <95000>; 206 hysteresis = <2000>; 207 type = "hot"; 208 }; 209 }; 210 }; 211 212 tsens_tz_sensor8 { 213 polling-delay-passive = <0>; 214 polling-delay = <0>; 215 thermal-sensors = <&tsens 8>; 216 217 trips { 218 cpu-critical { 219 temperature = <105000>; 220 hysteresis = <2000>; 221 type = "critical"; 222 }; 223 224 cpu-hot { 225 temperature = <95000>; 226 hysteresis = <2000>; 227 type = "hot"; 228 }; 229 }; 230 }; 231 232 tsens_tz_sensor9 { 233 polling-delay-passive = <0>; 234 polling-delay = <0>; 235 thermal-sensors = <&tsens 9>; 236 237 trips { 238 cpu-critical { 239 temperature = <105000>; 240 hysteresis = <2000>; 241 type = "critical"; 242 }; 243 244 cpu-hot { 245 temperature = <95000>; 246 hysteresis = <2000>; 247 type = "hot"; 248 }; 249 }; 250 }; 251 252 tsens_tz_sensor10 { 253 polling-delay-passive = <0>; 254 polling-delay = <0>; 255 thermal-sensors = <&tsens 10>; 256 257 trips { 258 cpu-critical { 259 temperature = <105000>; 260 hysteresis = <2000>; 261 type = "critical"; 262 }; 263 264 cpu-hot { 265 temperature = <95000>; 266 hysteresis = <2000>; 267 type = "hot"; 268 }; 269 }; 270 }; 271 }; 272 273 memory { 274 device_type = "memory"; 275 reg = <0x0 0x0>; 276 }; 277 278 cpu-pmu { 279 compatible = "qcom,krait-pmu"; 280 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 281 IRQ_TYPE_LEVEL_HIGH)>; 282 }; 283 284 reserved-memory { 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges; 288 289 nss@40000000 { 290 reg = <0x40000000 0x1000000>; 291 no-map; 292 }; 293 294 smem: smem@41000000 { 295 reg = <0x41000000 0x200000>; 296 no-map; 297 }; 298 }; 299 300 clocks { 301 cxo_board { 302 compatible = "fixed-clock"; 303 #clock-cells = <0>; 304 clock-frequency = <25000000>; 305 }; 306 307 pxo_board { 308 compatible = "fixed-clock"; 309 #clock-cells = <0>; 310 clock-frequency = <25000000>; 311 }; 312 313 sleep_clk: sleep_clk { 314 compatible = "fixed-clock"; 315 clock-frequency = <32768>; 316 #clock-cells = <0>; 317 }; 318 }; 319 320 firmware { 321 scm { 322 compatible = "qcom,scm-ipq806x", "qcom,scm"; 323 }; 324 }; 325 326 soc: soc { 327 #address-cells = <1>; 328 #size-cells = <1>; 329 ranges; 330 compatible = "simple-bus"; 331 332 lpass@28100000 { 333 compatible = "qcom,lpass-cpu"; 334 status = "disabled"; 335 clocks = <&lcc AHBIX_CLK>, 336 <&lcc MI2S_OSR_CLK>, 337 <&lcc MI2S_BIT_CLK>; 338 clock-names = "ahbix-clk", 339 "mi2s-osr-clk", 340 "mi2s-bit-clk"; 341 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 342 interrupt-names = "lpass-irq-lpaif"; 343 reg = <0x28100000 0x10000>; 344 reg-names = "lpass-lpaif"; 345 }; 346 347 qcom_pinmux: pinmux@800000 { 348 compatible = "qcom,ipq8064-pinctrl"; 349 reg = <0x800000 0x4000>; 350 351 gpio-controller; 352 gpio-ranges = <&qcom_pinmux 0 0 69>; 353 #gpio-cells = <2>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 357 358 pcie0_pins: pcie0_pinmux { 359 mux { 360 pins = "gpio3"; 361 function = "pcie1_rst"; 362 drive-strength = <12>; 363 bias-disable; 364 }; 365 }; 366 367 pcie1_pins: pcie1_pinmux { 368 mux { 369 pins = "gpio48"; 370 function = "pcie2_rst"; 371 drive-strength = <12>; 372 bias-disable; 373 }; 374 }; 375 376 pcie2_pins: pcie2_pinmux { 377 mux { 378 pins = "gpio63"; 379 function = "pcie3_rst"; 380 drive-strength = <12>; 381 bias-disable; 382 }; 383 }; 384 385 spi_pins: spi_pins { 386 mux { 387 pins = "gpio18", "gpio19", "gpio21"; 388 function = "gsbi5"; 389 drive-strength = <10>; 390 bias-none; 391 }; 392 }; 393 394 leds_pins: leds_pins { 395 mux { 396 pins = "gpio7", "gpio8", "gpio9", 397 "gpio26", "gpio53"; 398 function = "gpio"; 399 drive-strength = <2>; 400 bias-pull-down; 401 output-low; 402 }; 403 }; 404 405 buttons_pins: buttons_pins { 406 mux { 407 pins = "gpio54"; 408 drive-strength = <2>; 409 bias-pull-up; 410 }; 411 }; 412 413 nand_pins: nand_pins { 414 mux { 415 pins = "gpio34", "gpio35", "gpio36", 416 "gpio37", "gpio38", "gpio39", 417 "gpio40", "gpio41", "gpio42", 418 "gpio43", "gpio44", "gpio45", 419 "gpio46", "gpio47"; 420 function = "nand"; 421 drive-strength = <10>; 422 bias-disable; 423 }; 424 425 pullups { 426 pins = "gpio39"; 427 bias-pull-up; 428 }; 429 430 hold { 431 pins = "gpio40", "gpio41", "gpio42", 432 "gpio43", "gpio44", "gpio45", 433 "gpio46", "gpio47"; 434 bias-bus-hold; 435 }; 436 }; 437 }; 438 439 intc: interrupt-controller@2000000 { 440 compatible = "qcom,msm-qgic2"; 441 interrupt-controller; 442 #interrupt-cells = <3>; 443 reg = <0x02000000 0x1000>, 444 <0x02002000 0x1000>; 445 }; 446 447 timer@200a000 { 448 compatible = "qcom,kpss-timer", 449 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; 450 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | 451 IRQ_TYPE_EDGE_RISING)>, 452 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | 453 IRQ_TYPE_EDGE_RISING)>, 454 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | 455 IRQ_TYPE_EDGE_RISING)>, 456 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | 457 IRQ_TYPE_EDGE_RISING)>, 458 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | 459 IRQ_TYPE_EDGE_RISING)>; 460 reg = <0x0200a000 0x100>; 461 clock-frequency = <25000000>, 462 <32768>; 463 clocks = <&sleep_clk>; 464 clock-names = "sleep"; 465 cpu-offset = <0x80000>; 466 }; 467 468 acc0: clock-controller@2088000 { 469 compatible = "qcom,kpss-acc-v1"; 470 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 471 }; 472 473 acc1: clock-controller@2098000 { 474 compatible = "qcom,kpss-acc-v1"; 475 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 476 }; 477 478 adm_dma: dma-controller@18300000 { 479 compatible = "qcom,adm"; 480 reg = <0x18300000 0x100000>; 481 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 482 #dma-cells = <1>; 483 484 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; 485 clock-names = "core", "iface"; 486 487 resets = <&gcc ADM0_RESET>, 488 <&gcc ADM0_PBUS_RESET>, 489 <&gcc ADM0_C0_RESET>, 490 <&gcc ADM0_C1_RESET>, 491 <&gcc ADM0_C2_RESET>; 492 reset-names = "clk", "pbus", "c0", "c1", "c2"; 493 qcom,ee = <0>; 494 495 status = "disabled"; 496 }; 497 498 saw0: regulator@2089000 { 499 compatible = "qcom,saw2"; 500 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 501 regulator; 502 }; 503 504 saw1: regulator@2099000 { 505 compatible = "qcom,saw2"; 506 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 507 regulator; 508 }; 509 510 gsbi2: gsbi@12480000 { 511 compatible = "qcom,gsbi-v1.0.0"; 512 cell-index = <2>; 513 reg = <0x12480000 0x100>; 514 clocks = <&gcc GSBI2_H_CLK>; 515 clock-names = "iface"; 516 #address-cells = <1>; 517 #size-cells = <1>; 518 ranges; 519 status = "disabled"; 520 521 syscon-tcsr = <&tcsr>; 522 523 gsbi2_serial: serial@12490000 { 524 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 525 reg = <0x12490000 0x1000>, 526 <0x12480000 0x1000>; 527 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; 529 clock-names = "core", "iface"; 530 status = "disabled"; 531 }; 532 533 i2c@124a0000 { 534 compatible = "qcom,i2c-qup-v1.1.1"; 535 reg = <0x124a0000 0x1000>; 536 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 537 538 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 539 clock-names = "core", "iface"; 540 status = "disabled"; 541 542 #address-cells = <1>; 543 #size-cells = <0>; 544 }; 545 }; 546 547 gsbi4: gsbi@16300000 { 548 compatible = "qcom,gsbi-v1.0.0"; 549 cell-index = <4>; 550 reg = <0x16300000 0x100>; 551 clocks = <&gcc GSBI4_H_CLK>; 552 clock-names = "iface"; 553 #address-cells = <1>; 554 #size-cells = <1>; 555 ranges; 556 status = "disabled"; 557 558 syscon-tcsr = <&tcsr>; 559 560 gsbi4_serial: serial@16340000 { 561 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 562 reg = <0x16340000 0x1000>, 563 <0x16300000 0x1000>; 564 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 566 clock-names = "core", "iface"; 567 status = "disabled"; 568 }; 569 570 i2c@16380000 { 571 compatible = "qcom,i2c-qup-v1.1.1"; 572 reg = <0x16380000 0x1000>; 573 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 574 575 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; 576 clock-names = "core", "iface"; 577 status = "disabled"; 578 579 #address-cells = <1>; 580 #size-cells = <0>; 581 }; 582 }; 583 584 gsbi5: gsbi@1a200000 { 585 compatible = "qcom,gsbi-v1.0.0"; 586 cell-index = <5>; 587 reg = <0x1a200000 0x100>; 588 clocks = <&gcc GSBI5_H_CLK>; 589 clock-names = "iface"; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 ranges; 593 status = "disabled"; 594 595 syscon-tcsr = <&tcsr>; 596 597 gsbi5_serial: serial@1a240000 { 598 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 599 reg = <0x1a240000 0x1000>, 600 <0x1a200000 0x1000>; 601 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 603 clock-names = "core", "iface"; 604 status = "disabled"; 605 }; 606 607 i2c@1a280000 { 608 compatible = "qcom,i2c-qup-v1.1.1"; 609 reg = <0x1a280000 0x1000>; 610 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 611 612 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 613 clock-names = "core", "iface"; 614 status = "disabled"; 615 616 #address-cells = <1>; 617 #size-cells = <0>; 618 }; 619 620 spi@1a280000 { 621 compatible = "qcom,spi-qup-v1.1.1"; 622 reg = <0x1a280000 0x1000>; 623 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 624 625 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 626 clock-names = "core", "iface"; 627 status = "disabled"; 628 629 #address-cells = <1>; 630 #size-cells = <0>; 631 }; 632 }; 633 634 gsbi7: gsbi@16600000 { 635 status = "disabled"; 636 compatible = "qcom,gsbi-v1.0.0"; 637 cell-index = <7>; 638 reg = <0x16600000 0x100>; 639 clocks = <&gcc GSBI7_H_CLK>; 640 clock-names = "iface"; 641 #address-cells = <1>; 642 #size-cells = <1>; 643 ranges; 644 syscon-tcsr = <&tcsr>; 645 646 gsbi7_serial: serial@16640000 { 647 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 648 reg = <0x16640000 0x1000>, 649 <0x16600000 0x1000>; 650 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 651 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 652 clock-names = "core", "iface"; 653 status = "disabled"; 654 }; 655 }; 656 657 rng@1a500000 { 658 compatible = "qcom,prng"; 659 reg = <0x1a500000 0x200>; 660 clocks = <&gcc PRNG_CLK>; 661 clock-names = "core"; 662 }; 663 664 sata_phy: sata-phy@1b400000 { 665 compatible = "qcom,ipq806x-sata-phy"; 666 reg = <0x1b400000 0x200>; 667 668 clocks = <&gcc SATA_PHY_CFG_CLK>; 669 clock-names = "cfg"; 670 671 #phy-cells = <0>; 672 status = "disabled"; 673 }; 674 675 nand: nand-controller@1ac00000 { 676 compatible = "qcom,ipq806x-nand"; 677 reg = <0x1ac00000 0x800>; 678 679 pinctrl-0 = <&nand_pins>; 680 pinctrl-names = "default"; 681 682 clocks = <&gcc EBI2_CLK>, 683 <&gcc EBI2_AON_CLK>; 684 clock-names = "core", "aon"; 685 686 dmas = <&adm_dma 3>; 687 dma-names = "rxtx"; 688 qcom,cmd-crci = <15>; 689 qcom,data-crci = <3>; 690 691 #address-cells = <1>; 692 #size-cells = <0>; 693 694 status = "disabled"; 695 }; 696 697 sata: sata@29000000 { 698 compatible = "qcom,ipq806x-ahci", "generic-ahci"; 699 reg = <0x29000000 0x180>; 700 701 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 702 703 clocks = <&gcc SFAB_SATA_S_H_CLK>, 704 <&gcc SATA_H_CLK>, 705 <&gcc SATA_A_CLK>, 706 <&gcc SATA_RXOOB_CLK>, 707 <&gcc SATA_PMALIVE_CLK>; 708 clock-names = "slave_face", "iface", "core", 709 "rxoob", "pmalive"; 710 711 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; 712 assigned-clock-rates = <100000000>, <100000000>; 713 714 phys = <&sata_phy>; 715 phy-names = "sata-phy"; 716 status = "disabled"; 717 }; 718 719 qcom,ssbi@500000 { 720 compatible = "qcom,ssbi"; 721 reg = <0x00500000 0x1000>; 722 qcom,controller-type = "pmic-arbiter"; 723 }; 724 725 qfprom: qfprom@700000 { 726 compatible = "qcom,qfprom"; 727 reg = <0x00700000 0x1000>; 728 #address-cells = <1>; 729 #size-cells = <1>; 730 tsens_calib: calib@400 { 731 reg = <0x400 0xb>; 732 }; 733 tsens_calib_backup: calib_backup@410 { 734 reg = <0x410 0xb>; 735 }; 736 }; 737 738 gcc: clock-controller@900000 { 739 compatible = "qcom,gcc-ipq8064"; 740 reg = <0x00900000 0x4000>; 741 #clock-cells = <1>; 742 #reset-cells = <1>; 743 #power-domain-cells = <1>; 744 745 tsens: thermal-sensor@900000 { 746 compatible = "qcom,ipq8064-tsens"; 747 748 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 749 nvmem-cell-names = "calib", "calib_backup"; 750 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 751 interrupt-names = "uplow"; 752 753 #qcom,sensors = <11>; 754 #thermal-sensor-cells = <1>; 755 }; 756 }; 757 758 rpm: rpm@108000 { 759 compatible = "qcom,rpm-ipq8064"; 760 reg = <0x108000 0x1000>; 761 qcom,ipc = <&l2cc 0x8 2>; 762 763 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 766 interrupt-names = "ack", "err", "wakeup"; 767 768 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 769 clock-names = "ram"; 770 771 rpmcc: clock-controller { 772 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; 773 #clock-cells = <1>; 774 }; 775 }; 776 777 tcsr: syscon@1a400000 { 778 compatible = "qcom,tcsr-ipq8064", "syscon"; 779 reg = <0x1a400000 0x100>; 780 }; 781 782 l2cc: clock-controller@2011000 { 783 compatible = "qcom,kpss-gcc", "syscon"; 784 reg = <0x2011000 0x1000>; 785 clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; 786 clock-names = "pll8_vote", "pxo"; 787 clock-output-names = "acpu_l2_aux"; 788 }; 789 790 lcc: clock-controller@28000000 { 791 compatible = "qcom,lcc-ipq8064"; 792 reg = <0x28000000 0x1000>; 793 #clock-cells = <1>; 794 #reset-cells = <1>; 795 }; 796 797 pcie0: pci@1b500000 { 798 compatible = "qcom,pcie-ipq8064"; 799 reg = <0x1b500000 0x1000 800 0x1b502000 0x80 801 0x1b600000 0x100 802 0x0ff00000 0x100000>; 803 reg-names = "dbi", "elbi", "parf", "config"; 804 device_type = "pci"; 805 linux,pci-domain = <0>; 806 bus-range = <0x00 0xff>; 807 num-lanes = <1>; 808 #address-cells = <3>; 809 #size-cells = <2>; 810 811 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */ 812 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ 813 814 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 815 interrupt-names = "msi"; 816 #interrupt-cells = <1>; 817 interrupt-map-mask = <0 0 0 0x7>; 818 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 819 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 820 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 821 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 822 823 clocks = <&gcc PCIE_A_CLK>, 824 <&gcc PCIE_H_CLK>, 825 <&gcc PCIE_PHY_CLK>, 826 <&gcc PCIE_AUX_CLK>, 827 <&gcc PCIE_ALT_REF_CLK>; 828 clock-names = "core", "iface", "phy", "aux", "ref"; 829 830 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; 831 assigned-clock-rates = <100000000>; 832 833 resets = <&gcc PCIE_ACLK_RESET>, 834 <&gcc PCIE_HCLK_RESET>, 835 <&gcc PCIE_POR_RESET>, 836 <&gcc PCIE_PCI_RESET>, 837 <&gcc PCIE_PHY_RESET>, 838 <&gcc PCIE_EXT_RESET>; 839 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 840 841 pinctrl-0 = <&pcie0_pins>; 842 pinctrl-names = "default"; 843 844 status = "disabled"; 845 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; 846 }; 847 848 pcie1: pci@1b700000 { 849 compatible = "qcom,pcie-ipq8064"; 850 reg = <0x1b700000 0x1000 851 0x1b702000 0x80 852 0x1b800000 0x100 853 0x31f00000 0x100000>; 854 reg-names = "dbi", "elbi", "parf", "config"; 855 device_type = "pci"; 856 linux,pci-domain = <1>; 857 bus-range = <0x00 0xff>; 858 num-lanes = <1>; 859 #address-cells = <3>; 860 #size-cells = <2>; 861 862 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */ 863 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ 864 865 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 866 interrupt-names = "msi"; 867 #interrupt-cells = <1>; 868 interrupt-map-mask = <0 0 0 0x7>; 869 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 870 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 871 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 872 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 873 874 clocks = <&gcc PCIE_1_A_CLK>, 875 <&gcc PCIE_1_H_CLK>, 876 <&gcc PCIE_1_PHY_CLK>, 877 <&gcc PCIE_1_AUX_CLK>, 878 <&gcc PCIE_1_ALT_REF_CLK>; 879 clock-names = "core", "iface", "phy", "aux", "ref"; 880 881 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; 882 assigned-clock-rates = <100000000>; 883 884 resets = <&gcc PCIE_1_ACLK_RESET>, 885 <&gcc PCIE_1_HCLK_RESET>, 886 <&gcc PCIE_1_POR_RESET>, 887 <&gcc PCIE_1_PCI_RESET>, 888 <&gcc PCIE_1_PHY_RESET>, 889 <&gcc PCIE_1_EXT_RESET>; 890 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 891 892 pinctrl-0 = <&pcie1_pins>; 893 pinctrl-names = "default"; 894 895 status = "disabled"; 896 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; 897 }; 898 899 pcie2: pci@1b900000 { 900 compatible = "qcom,pcie-ipq8064"; 901 reg = <0x1b900000 0x1000 902 0x1b902000 0x80 903 0x1ba00000 0x100 904 0x35f00000 0x100000>; 905 reg-names = "dbi", "elbi", "parf", "config"; 906 device_type = "pci"; 907 linux,pci-domain = <2>; 908 bus-range = <0x00 0xff>; 909 num-lanes = <1>; 910 #address-cells = <3>; 911 #size-cells = <2>; 912 913 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */ 914 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ 915 916 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-names = "msi"; 918 #interrupt-cells = <1>; 919 interrupt-map-mask = <0 0 0 0x7>; 920 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 921 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 922 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 923 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 924 925 clocks = <&gcc PCIE_2_A_CLK>, 926 <&gcc PCIE_2_H_CLK>, 927 <&gcc PCIE_2_PHY_CLK>, 928 <&gcc PCIE_2_AUX_CLK>, 929 <&gcc PCIE_2_ALT_REF_CLK>; 930 clock-names = "core", "iface", "phy", "aux", "ref"; 931 932 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; 933 assigned-clock-rates = <100000000>; 934 935 resets = <&gcc PCIE_2_ACLK_RESET>, 936 <&gcc PCIE_2_HCLK_RESET>, 937 <&gcc PCIE_2_POR_RESET>, 938 <&gcc PCIE_2_PCI_RESET>, 939 <&gcc PCIE_2_PHY_RESET>, 940 <&gcc PCIE_2_EXT_RESET>; 941 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 942 943 pinctrl-0 = <&pcie2_pins>; 944 pinctrl-names = "default"; 945 946 status = "disabled"; 947 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; 948 }; 949 950 nss_common: syscon@03000000 { 951 compatible = "syscon"; 952 reg = <0x03000000 0x0000FFFF>; 953 }; 954 955 qsgmii_csr: syscon@1bb00000 { 956 compatible = "syscon"; 957 reg = <0x1bb00000 0x000001FF>; 958 }; 959 960 stmmac_axi_setup: stmmac-axi-config { 961 snps,wr_osr_lmt = <7>; 962 snps,rd_osr_lmt = <7>; 963 snps,blen = <16 0 0 0 0 0 0>; 964 }; 965 966 gmac0: ethernet@37000000 { 967 device_type = "network"; 968 compatible = "qcom,ipq806x-gmac"; 969 reg = <0x37000000 0x200000>; 970 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 971 interrupt-names = "macirq"; 972 973 snps,axi-config = <&stmmac_axi_setup>; 974 snps,pbl = <32>; 975 snps,aal = <1>; 976 977 qcom,nss-common = <&nss_common>; 978 qcom,qsgmii-csr = <&qsgmii_csr>; 979 980 clocks = <&gcc GMAC_CORE1_CLK>; 981 clock-names = "stmmaceth"; 982 983 resets = <&gcc GMAC_CORE1_RESET>, 984 <&gcc GMAC_AHB_RESET>; 985 reset-names = "stmmaceth", "ahb"; 986 987 status = "disabled"; 988 }; 989 990 gmac1: ethernet@37200000 { 991 device_type = "network"; 992 compatible = "qcom,ipq806x-gmac"; 993 reg = <0x37200000 0x200000>; 994 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 995 interrupt-names = "macirq"; 996 997 snps,axi-config = <&stmmac_axi_setup>; 998 snps,pbl = <32>; 999 snps,aal = <1>; 1000 1001 qcom,nss-common = <&nss_common>; 1002 qcom,qsgmii-csr = <&qsgmii_csr>; 1003 1004 clocks = <&gcc GMAC_CORE2_CLK>; 1005 clock-names = "stmmaceth"; 1006 1007 resets = <&gcc GMAC_CORE2_RESET>, 1008 <&gcc GMAC_AHB_RESET>; 1009 reset-names = "stmmaceth", "ahb"; 1010 1011 status = "disabled"; 1012 }; 1013 1014 gmac2: ethernet@37400000 { 1015 device_type = "network"; 1016 compatible = "qcom,ipq806x-gmac"; 1017 reg = <0x37400000 0x200000>; 1018 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1019 interrupt-names = "macirq"; 1020 1021 snps,axi-config = <&stmmac_axi_setup>; 1022 snps,pbl = <32>; 1023 snps,aal = <1>; 1024 1025 qcom,nss-common = <&nss_common>; 1026 qcom,qsgmii-csr = <&qsgmii_csr>; 1027 1028 clocks = <&gcc GMAC_CORE3_CLK>; 1029 clock-names = "stmmaceth"; 1030 1031 resets = <&gcc GMAC_CORE3_RESET>, 1032 <&gcc GMAC_AHB_RESET>; 1033 reset-names = "stmmaceth", "ahb"; 1034 1035 status = "disabled"; 1036 }; 1037 1038 gmac3: ethernet@37600000 { 1039 device_type = "network"; 1040 compatible = "qcom,ipq806x-gmac"; 1041 reg = <0x37600000 0x200000>; 1042 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1043 interrupt-names = "macirq"; 1044 1045 snps,axi-config = <&stmmac_axi_setup>; 1046 snps,pbl = <32>; 1047 snps,aal = <1>; 1048 1049 qcom,nss-common = <&nss_common>; 1050 qcom,qsgmii-csr = <&qsgmii_csr>; 1051 1052 clocks = <&gcc GMAC_CORE4_CLK>; 1053 clock-names = "stmmaceth"; 1054 1055 resets = <&gcc GMAC_CORE4_RESET>, 1056 <&gcc GMAC_AHB_RESET>; 1057 reset-names = "stmmaceth", "ahb"; 1058 1059 status = "disabled"; 1060 }; 1061 1062 hs_phy_0: phy@100f8800 { 1063 compatible = "qcom,ipq806x-usb-phy-hs"; 1064 reg = <0x100f8800 0x30>; 1065 clocks = <&gcc USB30_0_UTMI_CLK>; 1066 clock-names = "ref"; 1067 #phy-cells = <0>; 1068 1069 status = "disabled"; 1070 }; 1071 1072 ss_phy_0: phy@100f8830 { 1073 compatible = "qcom,ipq806x-usb-phy-ss"; 1074 reg = <0x100f8830 0x30>; 1075 clocks = <&gcc USB30_0_MASTER_CLK>; 1076 clock-names = "ref"; 1077 #phy-cells = <0>; 1078 1079 status = "disabled"; 1080 }; 1081 1082 usb3_0: usb3@100f8800 { 1083 compatible = "qcom,dwc3", "syscon"; 1084 #address-cells = <1>; 1085 #size-cells = <1>; 1086 reg = <0x100f8800 0x8000>; 1087 clocks = <&gcc USB30_0_MASTER_CLK>; 1088 clock-names = "core"; 1089 1090 ranges; 1091 1092 resets = <&gcc USB30_0_MASTER_RESET>; 1093 reset-names = "master"; 1094 1095 status = "disabled"; 1096 1097 dwc3_0: dwc3@10000000 { 1098 compatible = "snps,dwc3"; 1099 reg = <0x10000000 0xcd00>; 1100 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1101 phys = <&hs_phy_0>, <&ss_phy_0>; 1102 phy-names = "usb2-phy", "usb3-phy"; 1103 dr_mode = "host"; 1104 snps,dis_u3_susphy_quirk; 1105 }; 1106 }; 1107 1108 hs_phy_1: phy@110f8800 { 1109 compatible = "qcom,ipq806x-usb-phy-hs"; 1110 reg = <0x110f8800 0x30>; 1111 clocks = <&gcc USB30_1_UTMI_CLK>; 1112 clock-names = "ref"; 1113 #phy-cells = <0>; 1114 }; 1115 1116 ss_phy_1: phy@110f8830 { 1117 compatible = "qcom,ipq806x-usb-phy-ss"; 1118 reg = <0x110f8830 0x30>; 1119 clocks = <&gcc USB30_1_MASTER_CLK>; 1120 clock-names = "ref"; 1121 #phy-cells = <0>; 1122 }; 1123 1124 usb3_1: usb3@110f8800 { 1125 compatible = "qcom,dwc3", "syscon"; 1126 #address-cells = <1>; 1127 #size-cells = <1>; 1128 reg = <0x110f8800 0x8000>; 1129 clocks = <&gcc USB30_1_MASTER_CLK>; 1130 clock-names = "core"; 1131 1132 ranges; 1133 1134 resets = <&gcc USB30_1_MASTER_RESET>; 1135 reset-names = "master"; 1136 1137 status = "disabled"; 1138 1139 dwc3_1: dwc3@11000000 { 1140 compatible = "snps,dwc3"; 1141 reg = <0x11000000 0xcd00>; 1142 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 1143 phys = <&hs_phy_1>, <&ss_phy_1>; 1144 phy-names = "usb2-phy", "usb3-phy"; 1145 dr_mode = "host"; 1146 snps,dis_u3_susphy_quirk; 1147 }; 1148 }; 1149 1150 vsdcc_fixed: vsdcc-regulator { 1151 compatible = "regulator-fixed"; 1152 regulator-name = "SDCC Power"; 1153 regulator-min-microvolt = <3300000>; 1154 regulator-max-microvolt = <3300000>; 1155 regulator-always-on; 1156 }; 1157 1158 sdcc1bam: dma@12402000 { 1159 compatible = "qcom,bam-v1.3.0"; 1160 reg = <0x12402000 0x8000>; 1161 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&gcc SDC1_H_CLK>; 1163 clock-names = "bam_clk"; 1164 #dma-cells = <1>; 1165 qcom,ee = <0>; 1166 }; 1167 1168 sdcc3bam: dma@12182000 { 1169 compatible = "qcom,bam-v1.3.0"; 1170 reg = <0x12182000 0x8000>; 1171 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&gcc SDC3_H_CLK>; 1173 clock-names = "bam_clk"; 1174 #dma-cells = <1>; 1175 qcom,ee = <0>; 1176 }; 1177 1178 amba: amba { 1179 compatible = "simple-bus"; 1180 #address-cells = <1>; 1181 #size-cells = <1>; 1182 ranges; 1183 1184 sdcc1: sdcc@12400000 { 1185 status = "disabled"; 1186 compatible = "arm,pl18x", "arm,primecell"; 1187 arm,primecell-periphid = <0x00051180>; 1188 reg = <0x12400000 0x2000>; 1189 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1190 interrupt-names = "cmd_irq"; 1191 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1192 clock-names = "mclk", "apb_pclk"; 1193 bus-width = <8>; 1194 max-frequency = <96000000>; 1195 non-removable; 1196 cap-sd-highspeed; 1197 cap-mmc-highspeed; 1198 mmc-ddr-1_8v; 1199 vmmc-supply = <&vsdcc_fixed>; 1200 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1201 dma-names = "tx", "rx"; 1202 }; 1203 1204 sdcc3: sdcc@12180000 { 1205 compatible = "arm,pl18x", "arm,primecell"; 1206 arm,primecell-periphid = <0x00051180>; 1207 status = "disabled"; 1208 reg = <0x12180000 0x2000>; 1209 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1210 interrupt-names = "cmd_irq"; 1211 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1212 clock-names = "mclk", "apb_pclk"; 1213 bus-width = <8>; 1214 cap-sd-highspeed; 1215 cap-mmc-highspeed; 1216 max-frequency = <192000000>; 1217 sd-uhs-sdr104; 1218 sd-uhs-ddr50; 1219 vqmmc-supply = <&vsdcc_fixed>; 1220 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 1221 dma-names = "tx", "rx"; 1222 }; 1223 }; 1224 }; 1225}; 1226
