1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * intel_hdmi_audio.c - Intel HDMI audio driver
4 *
5 * Copyright (C) 2016 Intel Corp
6 * Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
7 * Ramesh Babu K V <ramesh.babu@intel.com>
8 * Vaibhav Agarwal <vaibhav.agarwal@intel.com>
9 * Jerome Anand <jerome.anand@intel.com>
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
11 *
12 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13 * ALSA driver for Intel HDMI audio
14 */
15
16 #include <linux/types.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/interrupt.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/delay.h>
25 #include <sound/core.h>
26 #include <sound/asoundef.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/initval.h>
30 #include <sound/control.h>
31 #include <sound/jack.h>
32 #include <drm/drm_edid.h>
33 #include <drm/intel_lpe_audio.h>
34 #include "intel_hdmi_audio.h"
35
36 #define for_each_pipe(card_ctx, pipe) \
37 for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++)
38 #define for_each_port(card_ctx, port) \
39 for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++)
40
41 /*standard module options for ALSA. This module supports only one card*/
42 static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
43 static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
44 static bool single_port;
45
46 module_param_named(index, hdmi_card_index, int, 0444);
47 MODULE_PARM_DESC(index,
48 "Index value for INTEL Intel HDMI Audio controller.");
49 module_param_named(id, hdmi_card_id, charp, 0444);
50 MODULE_PARM_DESC(id,
51 "ID string for INTEL Intel HDMI Audio controller.");
52 module_param(single_port, bool, 0444);
53 MODULE_PARM_DESC(single_port,
54 "Single-port mode (for compatibility)");
55
56 /*
57 * ELD SA bits in the CEA Speaker Allocation data block
58 */
59 static const int eld_speaker_allocation_bits[] = {
60 [0] = FL | FR,
61 [1] = LFE,
62 [2] = FC,
63 [3] = RL | RR,
64 [4] = RC,
65 [5] = FLC | FRC,
66 [6] = RLC | RRC,
67 /* the following are not defined in ELD yet */
68 [7] = 0,
69 };
70
71 /*
72 * This is an ordered list!
73 *
74 * The preceding ones have better chances to be selected by
75 * hdmi_channel_allocation().
76 */
77 static struct cea_channel_speaker_allocation channel_allocations[] = {
78 /* channel: 7 6 5 4 3 2 1 0 */
79 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
80 /* 2.1 */
81 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
82 /* Dolby Surround */
83 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
84 /* surround40 */
85 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
86 /* surround41 */
87 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
88 /* surround50 */
89 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
90 /* surround51 */
91 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
92 /* 6.1 */
93 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
94 /* surround71 */
95 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
96
97 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
98 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
99 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
100 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
101 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
102 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
103 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
104 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
105 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
106 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
107 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
108 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
109 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
110 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
111 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
112 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
113 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
114 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
115 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
116 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
117 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
118 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
119 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
120 };
121
122 static const struct channel_map_table map_tables[] = {
123 { SNDRV_CHMAP_FL, 0x00, FL },
124 { SNDRV_CHMAP_FR, 0x01, FR },
125 { SNDRV_CHMAP_RL, 0x04, RL },
126 { SNDRV_CHMAP_RR, 0x05, RR },
127 { SNDRV_CHMAP_LFE, 0x02, LFE },
128 { SNDRV_CHMAP_FC, 0x03, FC },
129 { SNDRV_CHMAP_RLC, 0x06, RLC },
130 { SNDRV_CHMAP_RRC, 0x07, RRC },
131 {} /* terminator */
132 };
133
134 /* hardware capability structure */
135 static const struct snd_pcm_hardware had_pcm_hardware = {
136 .info = (SNDRV_PCM_INFO_INTERLEAVED |
137 SNDRV_PCM_INFO_MMAP |
138 SNDRV_PCM_INFO_MMAP_VALID |
139 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
140 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
141 SNDRV_PCM_FMTBIT_S24_LE |
142 SNDRV_PCM_FMTBIT_S32_LE),
143 .rates = SNDRV_PCM_RATE_32000 |
144 SNDRV_PCM_RATE_44100 |
145 SNDRV_PCM_RATE_48000 |
146 SNDRV_PCM_RATE_88200 |
147 SNDRV_PCM_RATE_96000 |
148 SNDRV_PCM_RATE_176400 |
149 SNDRV_PCM_RATE_192000,
150 .rate_min = HAD_MIN_RATE,
151 .rate_max = HAD_MAX_RATE,
152 .channels_min = HAD_MIN_CHANNEL,
153 .channels_max = HAD_MAX_CHANNEL,
154 .buffer_bytes_max = HAD_MAX_BUFFER,
155 .period_bytes_min = HAD_MIN_PERIOD_BYTES,
156 .period_bytes_max = HAD_MAX_PERIOD_BYTES,
157 .periods_min = HAD_MIN_PERIODS,
158 .periods_max = HAD_MAX_PERIODS,
159 .fifo_size = HAD_FIFO_SIZE,
160 };
161
162 /* Get the active PCM substream;
163 * Call had_substream_put() for unreferecing.
164 * Don't call this inside had_spinlock, as it takes by itself
165 */
166 static struct snd_pcm_substream *
had_substream_get(struct snd_intelhad * intelhaddata)167 had_substream_get(struct snd_intelhad *intelhaddata)
168 {
169 struct snd_pcm_substream *substream;
170 unsigned long flags;
171
172 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
173 substream = intelhaddata->stream_info.substream;
174 if (substream)
175 intelhaddata->stream_info.substream_refcount++;
176 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
177 return substream;
178 }
179
180 /* Unref the active PCM substream;
181 * Don't call this inside had_spinlock, as it takes by itself
182 */
had_substream_put(struct snd_intelhad * intelhaddata)183 static void had_substream_put(struct snd_intelhad *intelhaddata)
184 {
185 unsigned long flags;
186
187 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
188 intelhaddata->stream_info.substream_refcount--;
189 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
190 }
191
had_config_offset(int pipe)192 static u32 had_config_offset(int pipe)
193 {
194 switch (pipe) {
195 default:
196 case 0:
197 return AUDIO_HDMI_CONFIG_A;
198 case 1:
199 return AUDIO_HDMI_CONFIG_B;
200 case 2:
201 return AUDIO_HDMI_CONFIG_C;
202 }
203 }
204
205 /* Register access functions */
had_read_register_raw(struct snd_intelhad_card * card_ctx,int pipe,u32 reg)206 static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx,
207 int pipe, u32 reg)
208 {
209 return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg);
210 }
211
had_write_register_raw(struct snd_intelhad_card * card_ctx,int pipe,u32 reg,u32 val)212 static void had_write_register_raw(struct snd_intelhad_card *card_ctx,
213 int pipe, u32 reg, u32 val)
214 {
215 iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg);
216 }
217
had_read_register(struct snd_intelhad * ctx,u32 reg,u32 * val)218 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
219 {
220 if (!ctx->connected)
221 *val = 0;
222 else
223 *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg);
224 }
225
had_write_register(struct snd_intelhad * ctx,u32 reg,u32 val)226 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
227 {
228 if (ctx->connected)
229 had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val);
230 }
231
232 /*
233 * enable / disable audio configuration
234 *
235 * The normal read/modify should not directly be used on VLV2 for
236 * updating AUD_CONFIG register.
237 * This is because:
238 * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
239 * HDMI IP. As a result a read-modify of AUD_CONFIG regiter will always
240 * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
241 * register. This field should be 1xy binary for configuration with 6 or
242 * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
243 * causes the "channels" field to be updated as 0xy binary resulting in
244 * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
245 * appropriate value when doing read-modify of AUD_CONFIG register.
246 */
had_enable_audio(struct snd_intelhad * intelhaddata,bool enable)247 static void had_enable_audio(struct snd_intelhad *intelhaddata,
248 bool enable)
249 {
250 /* update the cached value */
251 intelhaddata->aud_config.regx.aud_en = enable;
252 had_write_register(intelhaddata, AUD_CONFIG,
253 intelhaddata->aud_config.regval);
254 }
255
256 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */
had_ack_irqs(struct snd_intelhad * ctx)257 static void had_ack_irqs(struct snd_intelhad *ctx)
258 {
259 u32 status_reg;
260
261 if (!ctx->connected)
262 return;
263 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
264 status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
265 had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
266 had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
267 }
268
269 /* Reset buffer pointers */
had_reset_audio(struct snd_intelhad * intelhaddata)270 static void had_reset_audio(struct snd_intelhad *intelhaddata)
271 {
272 had_write_register(intelhaddata, AUD_HDMI_STATUS,
273 AUD_HDMI_STATUSG_MASK_FUNCRST);
274 had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
275 }
276
277 /*
278 * initialize audio channel status registers
279 * This function is called in the prepare callback
280 */
had_prog_status_reg(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)281 static int had_prog_status_reg(struct snd_pcm_substream *substream,
282 struct snd_intelhad *intelhaddata)
283 {
284 union aud_ch_status_0 ch_stat0 = {.regval = 0};
285 union aud_ch_status_1 ch_stat1 = {.regval = 0};
286
287 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
288 IEC958_AES0_NONAUDIO) >> 1;
289 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
290 IEC958_AES3_CON_CLOCK) >> 4;
291
292 switch (substream->runtime->rate) {
293 case AUD_SAMPLE_RATE_32:
294 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
295 break;
296
297 case AUD_SAMPLE_RATE_44_1:
298 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
299 break;
300 case AUD_SAMPLE_RATE_48:
301 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
302 break;
303 case AUD_SAMPLE_RATE_88_2:
304 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
305 break;
306 case AUD_SAMPLE_RATE_96:
307 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
308 break;
309 case AUD_SAMPLE_RATE_176_4:
310 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
311 break;
312 case AUD_SAMPLE_RATE_192:
313 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
314 break;
315
316 default:
317 /* control should never come here */
318 return -EINVAL;
319 }
320
321 had_write_register(intelhaddata,
322 AUD_CH_STATUS_0, ch_stat0.regval);
323
324 switch (substream->runtime->format) {
325 case SNDRV_PCM_FORMAT_S16_LE:
326 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
327 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
328 break;
329 case SNDRV_PCM_FORMAT_S24_LE:
330 case SNDRV_PCM_FORMAT_S32_LE:
331 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
332 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
333 break;
334 default:
335 return -EINVAL;
336 }
337
338 had_write_register(intelhaddata,
339 AUD_CH_STATUS_1, ch_stat1.regval);
340 return 0;
341 }
342
343 /*
344 * function to initialize audio
345 * registers and buffer confgiuration registers
346 * This function is called in the prepare callback
347 */
had_init_audio_ctrl(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)348 static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
349 struct snd_intelhad *intelhaddata)
350 {
351 union aud_cfg cfg_val = {.regval = 0};
352 union aud_buf_config buf_cfg = {.regval = 0};
353 u8 channels;
354
355 had_prog_status_reg(substream, intelhaddata);
356
357 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
358 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
359 buf_cfg.regx.aud_delay = 0;
360 had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
361
362 channels = substream->runtime->channels;
363 cfg_val.regx.num_ch = channels - 2;
364 if (channels <= 2)
365 cfg_val.regx.layout = LAYOUT0;
366 else
367 cfg_val.regx.layout = LAYOUT1;
368
369 if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
370 cfg_val.regx.packet_mode = 1;
371
372 if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE)
373 cfg_val.regx.left_align = 1;
374
375 cfg_val.regx.val_bit = 1;
376
377 /* fix up the DP bits */
378 if (intelhaddata->dp_output) {
379 cfg_val.regx.dp_modei = 1;
380 cfg_val.regx.set = 1;
381 }
382
383 had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
384 intelhaddata->aud_config = cfg_val;
385 return 0;
386 }
387
388 /*
389 * Compute derived values in channel_allocations[].
390 */
init_channel_allocations(void)391 static void init_channel_allocations(void)
392 {
393 int i, j;
394 struct cea_channel_speaker_allocation *p;
395
396 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
397 p = channel_allocations + i;
398 p->channels = 0;
399 p->spk_mask = 0;
400 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
401 if (p->speakers[j]) {
402 p->channels++;
403 p->spk_mask |= p->speakers[j];
404 }
405 }
406 }
407
408 /*
409 * The transformation takes two steps:
410 *
411 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
412 * spk_mask => (channel_allocations[]) => ai->CA
413 *
414 * TODO: it could select the wrong CA from multiple candidates.
415 */
had_channel_allocation(struct snd_intelhad * intelhaddata,int channels)416 static int had_channel_allocation(struct snd_intelhad *intelhaddata,
417 int channels)
418 {
419 int i;
420 int ca = 0;
421 int spk_mask = 0;
422
423 /*
424 * CA defaults to 0 for basic stereo audio
425 */
426 if (channels <= 2)
427 return 0;
428
429 /*
430 * expand ELD's speaker allocation mask
431 *
432 * ELD tells the speaker mask in a compact(paired) form,
433 * expand ELD's notions to match the ones used by Audio InfoFrame.
434 */
435
436 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
437 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
438 spk_mask |= eld_speaker_allocation_bits[i];
439 }
440
441 /* search for the first working match in the CA table */
442 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
443 if (channels == channel_allocations[i].channels &&
444 (spk_mask & channel_allocations[i].spk_mask) ==
445 channel_allocations[i].spk_mask) {
446 ca = channel_allocations[i].ca_index;
447 break;
448 }
449 }
450
451 dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
452
453 return ca;
454 }
455
456 /* from speaker bit mask to ALSA API channel position */
spk_to_chmap(int spk)457 static int spk_to_chmap(int spk)
458 {
459 const struct channel_map_table *t = map_tables;
460
461 for (; t->map; t++) {
462 if (t->spk_mask == spk)
463 return t->map;
464 }
465 return 0;
466 }
467
had_build_channel_allocation_map(struct snd_intelhad * intelhaddata)468 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
469 {
470 int i, c;
471 int spk_mask = 0;
472 struct snd_pcm_chmap_elem *chmap;
473 u8 eld_high, eld_high_mask = 0xF0;
474 u8 high_msb;
475
476 kfree(intelhaddata->chmap->chmap);
477 intelhaddata->chmap->chmap = NULL;
478
479 chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
480 if (!chmap)
481 return;
482
483 dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
484 intelhaddata->eld[DRM_ELD_SPEAKER]);
485
486 /* WA: Fix the max channel supported to 8 */
487
488 /*
489 * Sink may support more than 8 channels, if eld_high has more than
490 * one bit set. SOC supports max 8 channels.
491 * Refer eld_speaker_allocation_bits, for sink speaker allocation
492 */
493
494 /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
495 eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
496 if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
497 /* eld_high & (eld_high-1): if more than 1 bit set */
498 /* 0x1F: 7 channels */
499 for (i = 1; i < 4; i++) {
500 high_msb = eld_high & (0x80 >> i);
501 if (high_msb) {
502 intelhaddata->eld[DRM_ELD_SPEAKER] &=
503 high_msb | 0xF;
504 break;
505 }
506 }
507 }
508
509 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
510 if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
511 spk_mask |= eld_speaker_allocation_bits[i];
512 }
513
514 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
515 if (spk_mask == channel_allocations[i].spk_mask) {
516 for (c = 0; c < channel_allocations[i].channels; c++) {
517 chmap->map[c] = spk_to_chmap(
518 channel_allocations[i].speakers[
519 (MAX_SPEAKERS - 1) - c]);
520 }
521 chmap->channels = channel_allocations[i].channels;
522 intelhaddata->chmap->chmap = chmap;
523 break;
524 }
525 }
526 if (i >= ARRAY_SIZE(channel_allocations))
527 kfree(chmap);
528 }
529
530 /*
531 * ALSA API channel-map control callbacks
532 */
had_chmap_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)533 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
534 struct snd_ctl_elem_info *uinfo)
535 {
536 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
537 uinfo->count = HAD_MAX_CHANNEL;
538 uinfo->value.integer.min = 0;
539 uinfo->value.integer.max = SNDRV_CHMAP_LAST;
540 return 0;
541 }
542
had_chmap_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)543 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
544 struct snd_ctl_elem_value *ucontrol)
545 {
546 struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
547 struct snd_intelhad *intelhaddata = info->private_data;
548 int i;
549 const struct snd_pcm_chmap_elem *chmap;
550
551 memset(ucontrol->value.integer.value, 0,
552 sizeof(long) * HAD_MAX_CHANNEL);
553 mutex_lock(&intelhaddata->mutex);
554 if (!intelhaddata->chmap->chmap) {
555 mutex_unlock(&intelhaddata->mutex);
556 return 0;
557 }
558
559 chmap = intelhaddata->chmap->chmap;
560 for (i = 0; i < chmap->channels; i++)
561 ucontrol->value.integer.value[i] = chmap->map[i];
562 mutex_unlock(&intelhaddata->mutex);
563
564 return 0;
565 }
566
had_register_chmap_ctls(struct snd_intelhad * intelhaddata,struct snd_pcm * pcm)567 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
568 struct snd_pcm *pcm)
569 {
570 int err;
571
572 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
573 NULL, 0, (unsigned long)intelhaddata,
574 &intelhaddata->chmap);
575 if (err < 0)
576 return err;
577
578 intelhaddata->chmap->private_data = intelhaddata;
579 intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
580 intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
581 intelhaddata->chmap->chmap = NULL;
582 return 0;
583 }
584
585 /*
586 * Initialize Data Island Packets registers
587 * This function is called in the prepare callback
588 */
had_prog_dip(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)589 static void had_prog_dip(struct snd_pcm_substream *substream,
590 struct snd_intelhad *intelhaddata)
591 {
592 int i;
593 union aud_ctrl_st ctrl_state = {.regval = 0};
594 union aud_info_frame2 frame2 = {.regval = 0};
595 union aud_info_frame3 frame3 = {.regval = 0};
596 u8 checksum = 0;
597 u32 info_frame;
598 int channels;
599 int ca;
600
601 channels = substream->runtime->channels;
602
603 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
604
605 ca = had_channel_allocation(intelhaddata, channels);
606 if (intelhaddata->dp_output) {
607 info_frame = DP_INFO_FRAME_WORD1;
608 frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
609 } else {
610 info_frame = HDMI_INFO_FRAME_WORD1;
611 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
612 frame3.regx.chnl_alloc = ca;
613
614 /* Calculte the byte wide checksum for all valid DIP words */
615 for (i = 0; i < BYTES_PER_WORD; i++)
616 checksum += (info_frame >> (i * 8)) & 0xff;
617 for (i = 0; i < BYTES_PER_WORD; i++)
618 checksum += (frame2.regval >> (i * 8)) & 0xff;
619 for (i = 0; i < BYTES_PER_WORD; i++)
620 checksum += (frame3.regval >> (i * 8)) & 0xff;
621
622 frame2.regx.chksum = -(checksum);
623 }
624
625 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
626 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
627 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
628
629 /* program remaining DIP words with zero */
630 for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
631 had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
632
633 ctrl_state.regx.dip_freq = 1;
634 ctrl_state.regx.dip_en_sta = 1;
635 had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
636 }
637
had_calculate_maud_value(u32 aud_samp_freq,u32 link_rate)638 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
639 {
640 u32 maud_val;
641
642 /* Select maud according to DP 1.2 spec */
643 if (link_rate == DP_2_7_GHZ) {
644 switch (aud_samp_freq) {
645 case AUD_SAMPLE_RATE_32:
646 maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
647 break;
648
649 case AUD_SAMPLE_RATE_44_1:
650 maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
651 break;
652
653 case AUD_SAMPLE_RATE_48:
654 maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
655 break;
656
657 case AUD_SAMPLE_RATE_88_2:
658 maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
659 break;
660
661 case AUD_SAMPLE_RATE_96:
662 maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
663 break;
664
665 case AUD_SAMPLE_RATE_176_4:
666 maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
667 break;
668
669 case HAD_MAX_RATE:
670 maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
671 break;
672
673 default:
674 maud_val = -EINVAL;
675 break;
676 }
677 } else if (link_rate == DP_1_62_GHZ) {
678 switch (aud_samp_freq) {
679 case AUD_SAMPLE_RATE_32:
680 maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
681 break;
682
683 case AUD_SAMPLE_RATE_44_1:
684 maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
685 break;
686
687 case AUD_SAMPLE_RATE_48:
688 maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
689 break;
690
691 case AUD_SAMPLE_RATE_88_2:
692 maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
693 break;
694
695 case AUD_SAMPLE_RATE_96:
696 maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
697 break;
698
699 case AUD_SAMPLE_RATE_176_4:
700 maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
701 break;
702
703 case HAD_MAX_RATE:
704 maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
705 break;
706
707 default:
708 maud_val = -EINVAL;
709 break;
710 }
711 } else
712 maud_val = -EINVAL;
713
714 return maud_val;
715 }
716
717 /*
718 * Program HDMI audio CTS value
719 *
720 * @aud_samp_freq: sampling frequency of audio data
721 * @tmds: sampling frequency of the display data
722 * @link_rate: DP link rate
723 * @n_param: N value, depends on aud_samp_freq
724 * @intelhaddata: substream private data
725 *
726 * Program CTS register based on the audio and display sampling frequency
727 */
had_prog_cts(u32 aud_samp_freq,u32 tmds,u32 link_rate,u32 n_param,struct snd_intelhad * intelhaddata)728 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
729 u32 n_param, struct snd_intelhad *intelhaddata)
730 {
731 u32 cts_val;
732 u64 dividend, divisor;
733
734 if (intelhaddata->dp_output) {
735 /* Substitute cts_val with Maud according to DP 1.2 spec*/
736 cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
737 } else {
738 /* Calculate CTS according to HDMI 1.3a spec*/
739 dividend = (u64)tmds * n_param*1000;
740 divisor = 128 * aud_samp_freq;
741 cts_val = div64_u64(dividend, divisor);
742 }
743 dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
744 tmds, n_param, cts_val);
745 had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
746 }
747
had_calculate_n_value(u32 aud_samp_freq)748 static int had_calculate_n_value(u32 aud_samp_freq)
749 {
750 int n_val;
751
752 /* Select N according to HDMI 1.3a spec*/
753 switch (aud_samp_freq) {
754 case AUD_SAMPLE_RATE_32:
755 n_val = 4096;
756 break;
757
758 case AUD_SAMPLE_RATE_44_1:
759 n_val = 6272;
760 break;
761
762 case AUD_SAMPLE_RATE_48:
763 n_val = 6144;
764 break;
765
766 case AUD_SAMPLE_RATE_88_2:
767 n_val = 12544;
768 break;
769
770 case AUD_SAMPLE_RATE_96:
771 n_val = 12288;
772 break;
773
774 case AUD_SAMPLE_RATE_176_4:
775 n_val = 25088;
776 break;
777
778 case HAD_MAX_RATE:
779 n_val = 24576;
780 break;
781
782 default:
783 n_val = -EINVAL;
784 break;
785 }
786 return n_val;
787 }
788
789 /*
790 * Program HDMI audio N value
791 *
792 * @aud_samp_freq: sampling frequency of audio data
793 * @n_param: N value, depends on aud_samp_freq
794 * @intelhaddata: substream private data
795 *
796 * This function is called in the prepare callback.
797 * It programs based on the audio and display sampling frequency
798 */
had_prog_n(u32 aud_samp_freq,u32 * n_param,struct snd_intelhad * intelhaddata)799 static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
800 struct snd_intelhad *intelhaddata)
801 {
802 int n_val;
803
804 if (intelhaddata->dp_output) {
805 /*
806 * According to DP specs, Maud and Naud values hold
807 * a relationship, which is stated as:
808 * Maud/Naud = 512 * fs / f_LS_Clk
809 * where, fs is the sampling frequency of the audio stream
810 * and Naud is 32768 for Async clock.
811 */
812
813 n_val = DP_NAUD_VAL;
814 } else
815 n_val = had_calculate_n_value(aud_samp_freq);
816
817 if (n_val < 0)
818 return n_val;
819
820 had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
821 *n_param = n_val;
822 return 0;
823 }
824
825 /*
826 * PCM ring buffer handling
827 *
828 * The hardware provides a ring buffer with the fixed 4 buffer descriptors
829 * (BDs). The driver maps these 4 BDs onto the PCM ring buffer. The mapping
830 * moves at each period elapsed. The below illustrates how it works:
831 *
832 * At time=0
833 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
834 * BD | 0 | 1 | 2 | 3 |
835 *
836 * At time=1 (period elapsed)
837 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
838 * BD | 1 | 2 | 3 | 0 |
839 *
840 * At time=2 (second period elapsed)
841 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
842 * BD | 2 | 3 | 0 | 1 |
843 *
844 * The bd_head field points to the index of the BD to be read. It's also the
845 * position to be filled at next. The pcm_head and the pcm_filled fields
846 * point to the indices of the current position and of the next position to
847 * be filled, respectively. For PCM buffer there are both _head and _filled
848 * because they may be difference when nperiods > 4. For example, in the
849 * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5:
850 *
851 * pcm_head (=1) --v v-- pcm_filled (=5)
852 * PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
853 * BD | 1 | 2 | 3 | 0 |
854 * bd_head (=1) --^ ^-- next to fill (= bd_head)
855 *
856 * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that
857 * the hardware skips those BDs in the loop.
858 *
859 * An exceptional setup is the case with nperiods=1. Since we have to update
860 * BDs after finishing one BD processing, we'd need at least two BDs, where
861 * both BDs point to the same content, the same address, the same size of the
862 * whole PCM buffer.
863 */
864
865 #define AUD_BUF_ADDR(x) (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
866 #define AUD_BUF_LEN(x) (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
867
868 /* Set up a buffer descriptor at the "filled" position */
had_prog_bd(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)869 static void had_prog_bd(struct snd_pcm_substream *substream,
870 struct snd_intelhad *intelhaddata)
871 {
872 int idx = intelhaddata->bd_head;
873 int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
874 u32 addr = substream->runtime->dma_addr + ofs;
875
876 addr |= AUD_BUF_VALID;
877 if (!substream->runtime->no_period_wakeup)
878 addr |= AUD_BUF_INTR_EN;
879 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
880 had_write_register(intelhaddata, AUD_BUF_LEN(idx),
881 intelhaddata->period_bytes);
882
883 /* advance the indices to the next */
884 intelhaddata->bd_head++;
885 intelhaddata->bd_head %= intelhaddata->num_bds;
886 intelhaddata->pcmbuf_filled++;
887 intelhaddata->pcmbuf_filled %= substream->runtime->periods;
888 }
889
890 /* invalidate a buffer descriptor with the given index */
had_invalidate_bd(struct snd_intelhad * intelhaddata,int idx)891 static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
892 int idx)
893 {
894 had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
895 had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
896 }
897
898 /* Initial programming of ring buffer */
had_init_ringbuf(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)899 static void had_init_ringbuf(struct snd_pcm_substream *substream,
900 struct snd_intelhad *intelhaddata)
901 {
902 struct snd_pcm_runtime *runtime = substream->runtime;
903 int i, num_periods;
904
905 num_periods = runtime->periods;
906 intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
907 /* set the minimum 2 BDs for num_periods=1 */
908 intelhaddata->num_bds = max(intelhaddata->num_bds, 2U);
909 intelhaddata->period_bytes =
910 frames_to_bytes(runtime, runtime->period_size);
911 WARN_ON(intelhaddata->period_bytes & 0x3f);
912
913 intelhaddata->bd_head = 0;
914 intelhaddata->pcmbuf_head = 0;
915 intelhaddata->pcmbuf_filled = 0;
916
917 for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
918 if (i < intelhaddata->num_bds)
919 had_prog_bd(substream, intelhaddata);
920 else /* invalidate the rest */
921 had_invalidate_bd(intelhaddata, i);
922 }
923
924 intelhaddata->bd_head = 0; /* reset at head again before starting */
925 }
926
927 /* process a bd, advance to the next */
had_advance_ringbuf(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)928 static void had_advance_ringbuf(struct snd_pcm_substream *substream,
929 struct snd_intelhad *intelhaddata)
930 {
931 int num_periods = substream->runtime->periods;
932
933 /* reprogram the next buffer */
934 had_prog_bd(substream, intelhaddata);
935
936 /* proceed to next */
937 intelhaddata->pcmbuf_head++;
938 intelhaddata->pcmbuf_head %= num_periods;
939 }
940
941 /* process the current BD(s);
942 * returns the current PCM buffer byte position, or -EPIPE for underrun.
943 */
had_process_ringbuf(struct snd_pcm_substream * substream,struct snd_intelhad * intelhaddata)944 static int had_process_ringbuf(struct snd_pcm_substream *substream,
945 struct snd_intelhad *intelhaddata)
946 {
947 int len, processed;
948 unsigned long flags;
949
950 processed = 0;
951 spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
952 for (;;) {
953 /* get the remaining bytes on the buffer */
954 had_read_register(intelhaddata,
955 AUD_BUF_LEN(intelhaddata->bd_head),
956 &len);
957 if (len < 0 || len > intelhaddata->period_bytes) {
958 dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
959 len);
960 len = -EPIPE;
961 goto out;
962 }
963
964 if (len > 0) /* OK, this is the current buffer */
965 break;
966
967 /* len=0 => already empty, check the next buffer */
968 if (++processed >= intelhaddata->num_bds) {
969 len = -EPIPE; /* all empty? - report underrun */
970 goto out;
971 }
972 had_advance_ringbuf(substream, intelhaddata);
973 }
974
975 len = intelhaddata->period_bytes - len;
976 len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
977 out:
978 spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
979 return len;
980 }
981
982 /* called from irq handler */
had_process_buffer_done(struct snd_intelhad * intelhaddata)983 static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
984 {
985 struct snd_pcm_substream *substream;
986
987 substream = had_substream_get(intelhaddata);
988 if (!substream)
989 return; /* no stream? - bail out */
990
991 if (!intelhaddata->connected) {
992 snd_pcm_stop_xrun(substream);
993 goto out; /* disconnected? - bail out */
994 }
995
996 /* process or stop the stream */
997 if (had_process_ringbuf(substream, intelhaddata) < 0)
998 snd_pcm_stop_xrun(substream);
999 else
1000 snd_pcm_period_elapsed(substream);
1001
1002 out:
1003 had_substream_put(intelhaddata);
1004 }
1005
1006 /*
1007 * The interrupt status 'sticky' bits might not be cleared by
1008 * setting '1' to that bit once...
1009 */
wait_clear_underrun_bit(struct snd_intelhad * intelhaddata)1010 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
1011 {
1012 int i;
1013 u32 val;
1014
1015 for (i = 0; i < 100; i++) {
1016 /* clear bit30, 31 AUD_HDMI_STATUS */
1017 had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
1018 if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN))
1019 return;
1020 udelay(100);
1021 cond_resched();
1022 had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
1023 }
1024 dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
1025 }
1026
1027 /* Perform some reset procedure but only when need_reset is set;
1028 * this is called from prepare or hw_free callbacks once after trigger STOP
1029 * or underrun has been processed in order to settle down the h/w state.
1030 */
had_do_reset(struct snd_intelhad * intelhaddata)1031 static void had_do_reset(struct snd_intelhad *intelhaddata)
1032 {
1033 if (!intelhaddata->need_reset || !intelhaddata->connected)
1034 return;
1035
1036 /* Reset buffer pointers */
1037 had_reset_audio(intelhaddata);
1038 wait_clear_underrun_bit(intelhaddata);
1039 intelhaddata->need_reset = false;
1040 }
1041
1042 /* called from irq handler */
had_process_buffer_underrun(struct snd_intelhad * intelhaddata)1043 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1044 {
1045 struct snd_pcm_substream *substream;
1046
1047 /* Report UNDERRUN error to above layers */
1048 substream = had_substream_get(intelhaddata);
1049 if (substream) {
1050 snd_pcm_stop_xrun(substream);
1051 had_substream_put(intelhaddata);
1052 }
1053 intelhaddata->need_reset = true;
1054 }
1055
1056 /*
1057 * ALSA PCM open callback
1058 */
had_pcm_open(struct snd_pcm_substream * substream)1059 static int had_pcm_open(struct snd_pcm_substream *substream)
1060 {
1061 struct snd_intelhad *intelhaddata;
1062 struct snd_pcm_runtime *runtime;
1063 int retval;
1064
1065 intelhaddata = snd_pcm_substream_chip(substream);
1066 runtime = substream->runtime;
1067
1068 pm_runtime_get_sync(intelhaddata->dev);
1069
1070 /* set the runtime hw parameter with local snd_pcm_hardware struct */
1071 runtime->hw = had_pcm_hardware;
1072
1073 retval = snd_pcm_hw_constraint_integer(runtime,
1074 SNDRV_PCM_HW_PARAM_PERIODS);
1075 if (retval < 0)
1076 goto error;
1077
1078 /* Make sure, that the period size is always aligned
1079 * 64byte boundary
1080 */
1081 retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1082 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1083 if (retval < 0)
1084 goto error;
1085
1086 retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1087 if (retval < 0)
1088 goto error;
1089
1090 /* expose PCM substream */
1091 spin_lock_irq(&intelhaddata->had_spinlock);
1092 intelhaddata->stream_info.substream = substream;
1093 intelhaddata->stream_info.substream_refcount++;
1094 spin_unlock_irq(&intelhaddata->had_spinlock);
1095
1096 return retval;
1097 error:
1098 pm_runtime_mark_last_busy(intelhaddata->dev);
1099 pm_runtime_put_autosuspend(intelhaddata->dev);
1100 return retval;
1101 }
1102
1103 /*
1104 * ALSA PCM close callback
1105 */
had_pcm_close(struct snd_pcm_substream * substream)1106 static int had_pcm_close(struct snd_pcm_substream *substream)
1107 {
1108 struct snd_intelhad *intelhaddata;
1109
1110 intelhaddata = snd_pcm_substream_chip(substream);
1111
1112 /* unreference and sync with the pending PCM accesses */
1113 spin_lock_irq(&intelhaddata->had_spinlock);
1114 intelhaddata->stream_info.substream = NULL;
1115 intelhaddata->stream_info.substream_refcount--;
1116 while (intelhaddata->stream_info.substream_refcount > 0) {
1117 spin_unlock_irq(&intelhaddata->had_spinlock);
1118 cpu_relax();
1119 spin_lock_irq(&intelhaddata->had_spinlock);
1120 }
1121 spin_unlock_irq(&intelhaddata->had_spinlock);
1122
1123 pm_runtime_mark_last_busy(intelhaddata->dev);
1124 pm_runtime_put_autosuspend(intelhaddata->dev);
1125 return 0;
1126 }
1127
1128 /*
1129 * ALSA PCM hw_params callback
1130 */
had_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * hw_params)1131 static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1132 struct snd_pcm_hw_params *hw_params)
1133 {
1134 struct snd_intelhad *intelhaddata;
1135 int buf_size;
1136
1137 intelhaddata = snd_pcm_substream_chip(substream);
1138 buf_size = params_buffer_bytes(hw_params);
1139 dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1140 __func__, buf_size);
1141 return 0;
1142 }
1143
1144 /*
1145 * ALSA PCM hw_free callback
1146 */
had_pcm_hw_free(struct snd_pcm_substream * substream)1147 static int had_pcm_hw_free(struct snd_pcm_substream *substream)
1148 {
1149 struct snd_intelhad *intelhaddata;
1150
1151 intelhaddata = snd_pcm_substream_chip(substream);
1152 had_do_reset(intelhaddata);
1153
1154 return 0;
1155 }
1156
1157 /*
1158 * ALSA PCM trigger callback
1159 */
had_pcm_trigger(struct snd_pcm_substream * substream,int cmd)1160 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1161 {
1162 int retval = 0;
1163 struct snd_intelhad *intelhaddata;
1164
1165 intelhaddata = snd_pcm_substream_chip(substream);
1166
1167 spin_lock(&intelhaddata->had_spinlock);
1168 switch (cmd) {
1169 case SNDRV_PCM_TRIGGER_START:
1170 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1171 case SNDRV_PCM_TRIGGER_RESUME:
1172 /* Enable Audio */
1173 had_ack_irqs(intelhaddata); /* FIXME: do we need this? */
1174 had_enable_audio(intelhaddata, true);
1175 break;
1176
1177 case SNDRV_PCM_TRIGGER_STOP:
1178 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1179 /* Disable Audio */
1180 had_enable_audio(intelhaddata, false);
1181 intelhaddata->need_reset = true;
1182 break;
1183
1184 default:
1185 retval = -EINVAL;
1186 }
1187 spin_unlock(&intelhaddata->had_spinlock);
1188 return retval;
1189 }
1190
1191 /*
1192 * ALSA PCM prepare callback
1193 */
had_pcm_prepare(struct snd_pcm_substream * substream)1194 static int had_pcm_prepare(struct snd_pcm_substream *substream)
1195 {
1196 int retval;
1197 u32 disp_samp_freq, n_param;
1198 u32 link_rate = 0;
1199 struct snd_intelhad *intelhaddata;
1200 struct snd_pcm_runtime *runtime;
1201
1202 intelhaddata = snd_pcm_substream_chip(substream);
1203 runtime = substream->runtime;
1204
1205 dev_dbg(intelhaddata->dev, "period_size=%d\n",
1206 (int)frames_to_bytes(runtime, runtime->period_size));
1207 dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1208 dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1209 (int)snd_pcm_lib_buffer_bytes(substream));
1210 dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1211 dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
1212
1213 had_do_reset(intelhaddata);
1214
1215 /* Get N value in KHz */
1216 disp_samp_freq = intelhaddata->tmds_clock_speed;
1217
1218 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1219 if (retval) {
1220 dev_err(intelhaddata->dev,
1221 "programming N value failed %#x\n", retval);
1222 goto prep_end;
1223 }
1224
1225 if (intelhaddata->dp_output)
1226 link_rate = intelhaddata->link_rate;
1227
1228 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1229 n_param, intelhaddata);
1230
1231 had_prog_dip(substream, intelhaddata);
1232
1233 retval = had_init_audio_ctrl(substream, intelhaddata);
1234
1235 /* Prog buffer address */
1236 had_init_ringbuf(substream, intelhaddata);
1237
1238 /*
1239 * Program channel mapping in following order:
1240 * FL, FR, C, LFE, RL, RR
1241 */
1242
1243 had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
1244
1245 prep_end:
1246 return retval;
1247 }
1248
1249 /*
1250 * ALSA PCM pointer callback
1251 */
had_pcm_pointer(struct snd_pcm_substream * substream)1252 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
1253 {
1254 struct snd_intelhad *intelhaddata;
1255 int len;
1256
1257 intelhaddata = snd_pcm_substream_chip(substream);
1258
1259 if (!intelhaddata->connected)
1260 return SNDRV_PCM_POS_XRUN;
1261
1262 len = had_process_ringbuf(substream, intelhaddata);
1263 if (len < 0)
1264 return SNDRV_PCM_POS_XRUN;
1265 len = bytes_to_frames(substream->runtime, len);
1266 /* wrapping may happen when periods=1 */
1267 len %= substream->runtime->buffer_size;
1268 return len;
1269 }
1270
1271 /*
1272 * ALSA PCM mmap callback
1273 */
had_pcm_mmap(struct snd_pcm_substream * substream,struct vm_area_struct * vma)1274 static int had_pcm_mmap(struct snd_pcm_substream *substream,
1275 struct vm_area_struct *vma)
1276 {
1277 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1278 return remap_pfn_range(vma, vma->vm_start,
1279 substream->dma_buffer.addr >> PAGE_SHIFT,
1280 vma->vm_end - vma->vm_start, vma->vm_page_prot);
1281 }
1282
1283 /*
1284 * ALSA PCM ops
1285 */
1286 static const struct snd_pcm_ops had_pcm_ops = {
1287 .open = had_pcm_open,
1288 .close = had_pcm_close,
1289 .hw_params = had_pcm_hw_params,
1290 .hw_free = had_pcm_hw_free,
1291 .prepare = had_pcm_prepare,
1292 .trigger = had_pcm_trigger,
1293 .pointer = had_pcm_pointer,
1294 .mmap = had_pcm_mmap,
1295 };
1296
1297 /* process mode change of the running stream; called in mutex */
had_process_mode_change(struct snd_intelhad * intelhaddata)1298 static int had_process_mode_change(struct snd_intelhad *intelhaddata)
1299 {
1300 struct snd_pcm_substream *substream;
1301 int retval = 0;
1302 u32 disp_samp_freq, n_param;
1303 u32 link_rate = 0;
1304
1305 substream = had_substream_get(intelhaddata);
1306 if (!substream)
1307 return 0;
1308
1309 /* Disable Audio */
1310 had_enable_audio(intelhaddata, false);
1311
1312 /* Update CTS value */
1313 disp_samp_freq = intelhaddata->tmds_clock_speed;
1314
1315 retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1316 if (retval) {
1317 dev_err(intelhaddata->dev,
1318 "programming N value failed %#x\n", retval);
1319 goto out;
1320 }
1321
1322 if (intelhaddata->dp_output)
1323 link_rate = intelhaddata->link_rate;
1324
1325 had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1326 n_param, intelhaddata);
1327
1328 /* Enable Audio */
1329 had_enable_audio(intelhaddata, true);
1330
1331 out:
1332 had_substream_put(intelhaddata);
1333 return retval;
1334 }
1335
1336 /* process hot plug, called from wq with mutex locked */
had_process_hot_plug(struct snd_intelhad * intelhaddata)1337 static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
1338 {
1339 struct snd_pcm_substream *substream;
1340
1341 spin_lock_irq(&intelhaddata->had_spinlock);
1342 if (intelhaddata->connected) {
1343 dev_dbg(intelhaddata->dev, "Device already connected\n");
1344 spin_unlock_irq(&intelhaddata->had_spinlock);
1345 return;
1346 }
1347
1348 /* Disable Audio */
1349 had_enable_audio(intelhaddata, false);
1350
1351 intelhaddata->connected = true;
1352 dev_dbg(intelhaddata->dev,
1353 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1354 __func__, __LINE__);
1355 spin_unlock_irq(&intelhaddata->had_spinlock);
1356
1357 had_build_channel_allocation_map(intelhaddata);
1358
1359 /* Report to above ALSA layer */
1360 substream = had_substream_get(intelhaddata);
1361 if (substream) {
1362 snd_pcm_stop_xrun(substream);
1363 had_substream_put(intelhaddata);
1364 }
1365
1366 snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT);
1367 }
1368
1369 /* process hot unplug, called from wq with mutex locked */
had_process_hot_unplug(struct snd_intelhad * intelhaddata)1370 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1371 {
1372 struct snd_pcm_substream *substream;
1373
1374 spin_lock_irq(&intelhaddata->had_spinlock);
1375 if (!intelhaddata->connected) {
1376 dev_dbg(intelhaddata->dev, "Device already disconnected\n");
1377 spin_unlock_irq(&intelhaddata->had_spinlock);
1378 return;
1379
1380 }
1381
1382 /* Disable Audio */
1383 had_enable_audio(intelhaddata, false);
1384
1385 intelhaddata->connected = false;
1386 dev_dbg(intelhaddata->dev,
1387 "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
1388 __func__, __LINE__);
1389 spin_unlock_irq(&intelhaddata->had_spinlock);
1390
1391 kfree(intelhaddata->chmap->chmap);
1392 intelhaddata->chmap->chmap = NULL;
1393
1394 /* Report to above ALSA layer */
1395 substream = had_substream_get(intelhaddata);
1396 if (substream) {
1397 snd_pcm_stop_xrun(substream);
1398 had_substream_put(intelhaddata);
1399 }
1400
1401 snd_jack_report(intelhaddata->jack, 0);
1402 }
1403
1404 /*
1405 * ALSA iec958 and ELD controls
1406 */
1407
had_iec958_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1408 static int had_iec958_info(struct snd_kcontrol *kcontrol,
1409 struct snd_ctl_elem_info *uinfo)
1410 {
1411 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1412 uinfo->count = 1;
1413 return 0;
1414 }
1415
had_iec958_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1416 static int had_iec958_get(struct snd_kcontrol *kcontrol,
1417 struct snd_ctl_elem_value *ucontrol)
1418 {
1419 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1420
1421 mutex_lock(&intelhaddata->mutex);
1422 ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1423 ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1424 ucontrol->value.iec958.status[2] =
1425 (intelhaddata->aes_bits >> 16) & 0xff;
1426 ucontrol->value.iec958.status[3] =
1427 (intelhaddata->aes_bits >> 24) & 0xff;
1428 mutex_unlock(&intelhaddata->mutex);
1429 return 0;
1430 }
1431
had_iec958_mask_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1432 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1433 struct snd_ctl_elem_value *ucontrol)
1434 {
1435 ucontrol->value.iec958.status[0] = 0xff;
1436 ucontrol->value.iec958.status[1] = 0xff;
1437 ucontrol->value.iec958.status[2] = 0xff;
1438 ucontrol->value.iec958.status[3] = 0xff;
1439 return 0;
1440 }
1441
had_iec958_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1442 static int had_iec958_put(struct snd_kcontrol *kcontrol,
1443 struct snd_ctl_elem_value *ucontrol)
1444 {
1445 unsigned int val;
1446 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1447 int changed = 0;
1448
1449 val = (ucontrol->value.iec958.status[0] << 0) |
1450 (ucontrol->value.iec958.status[1] << 8) |
1451 (ucontrol->value.iec958.status[2] << 16) |
1452 (ucontrol->value.iec958.status[3] << 24);
1453 mutex_lock(&intelhaddata->mutex);
1454 if (intelhaddata->aes_bits != val) {
1455 intelhaddata->aes_bits = val;
1456 changed = 1;
1457 }
1458 mutex_unlock(&intelhaddata->mutex);
1459 return changed;
1460 }
1461
had_ctl_eld_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)1462 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1463 struct snd_ctl_elem_info *uinfo)
1464 {
1465 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1466 uinfo->count = HDMI_MAX_ELD_BYTES;
1467 return 0;
1468 }
1469
had_ctl_eld_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1470 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1471 struct snd_ctl_elem_value *ucontrol)
1472 {
1473 struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1474
1475 mutex_lock(&intelhaddata->mutex);
1476 memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1477 HDMI_MAX_ELD_BYTES);
1478 mutex_unlock(&intelhaddata->mutex);
1479 return 0;
1480 }
1481
1482 static const struct snd_kcontrol_new had_controls[] = {
1483 {
1484 .access = SNDRV_CTL_ELEM_ACCESS_READ,
1485 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1486 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1487 .info = had_iec958_info, /* shared */
1488 .get = had_iec958_mask_get,
1489 },
1490 {
1491 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1492 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1493 .info = had_iec958_info,
1494 .get = had_iec958_get,
1495 .put = had_iec958_put,
1496 },
1497 {
1498 .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1499 SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1500 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1501 .name = "ELD",
1502 .info = had_ctl_eld_info,
1503 .get = had_ctl_eld_get,
1504 },
1505 };
1506
1507 /*
1508 * audio interrupt handler
1509 */
display_pipe_interrupt_handler(int irq,void * dev_id)1510 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1511 {
1512 struct snd_intelhad_card *card_ctx = dev_id;
1513 u32 audio_stat[3] = {};
1514 int pipe, port;
1515
1516 for_each_pipe(card_ctx, pipe) {
1517 /* use raw register access to ack IRQs even while disconnected */
1518 audio_stat[pipe] = had_read_register_raw(card_ctx, pipe,
1519 AUD_HDMI_STATUS) &
1520 (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE);
1521
1522 if (audio_stat[pipe])
1523 had_write_register_raw(card_ctx, pipe,
1524 AUD_HDMI_STATUS, audio_stat[pipe]);
1525 }
1526
1527 for_each_port(card_ctx, port) {
1528 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1529 int pipe = ctx->pipe;
1530
1531 if (pipe < 0)
1532 continue;
1533
1534 if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE)
1535 had_process_buffer_done(ctx);
1536 if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN)
1537 had_process_buffer_underrun(ctx);
1538 }
1539
1540 return IRQ_HANDLED;
1541 }
1542
1543 /*
1544 * monitor plug/unplug notification from i915; just kick off the work
1545 */
notify_audio_lpe(struct platform_device * pdev,int port)1546 static void notify_audio_lpe(struct platform_device *pdev, int port)
1547 {
1548 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1549 struct snd_intelhad *ctx;
1550
1551 ctx = &card_ctx->pcm_ctx[single_port ? 0 : port];
1552 if (single_port)
1553 ctx->port = port;
1554
1555 schedule_work(&ctx->hdmi_audio_wq);
1556 }
1557
1558 /* the work to handle monitor hot plug/unplug */
had_audio_wq(struct work_struct * work)1559 static void had_audio_wq(struct work_struct *work)
1560 {
1561 struct snd_intelhad *ctx =
1562 container_of(work, struct snd_intelhad, hdmi_audio_wq);
1563 struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
1564 struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port];
1565
1566 pm_runtime_get_sync(ctx->dev);
1567 mutex_lock(&ctx->mutex);
1568 if (ppdata->pipe < 0) {
1569 dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n",
1570 __func__, ctx->port);
1571
1572 memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
1573
1574 ctx->dp_output = false;
1575 ctx->tmds_clock_speed = 0;
1576 ctx->link_rate = 0;
1577
1578 /* Shut down the stream */
1579 had_process_hot_unplug(ctx);
1580
1581 ctx->pipe = -1;
1582 } else {
1583 dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1584 __func__, ctx->port, ppdata->ls_clock);
1585
1586 memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld));
1587
1588 ctx->dp_output = ppdata->dp_output;
1589 if (ctx->dp_output) {
1590 ctx->tmds_clock_speed = 0;
1591 ctx->link_rate = ppdata->ls_clock;
1592 } else {
1593 ctx->tmds_clock_speed = ppdata->ls_clock;
1594 ctx->link_rate = 0;
1595 }
1596
1597 /*
1598 * Shut down the stream before we change
1599 * the pipe assignment for this pcm device
1600 */
1601 had_process_hot_plug(ctx);
1602
1603 ctx->pipe = ppdata->pipe;
1604
1605 /* Restart the stream if necessary */
1606 had_process_mode_change(ctx);
1607 }
1608
1609 mutex_unlock(&ctx->mutex);
1610 pm_runtime_mark_last_busy(ctx->dev);
1611 pm_runtime_put_autosuspend(ctx->dev);
1612 }
1613
1614 /*
1615 * Jack interface
1616 */
had_create_jack(struct snd_intelhad * ctx,struct snd_pcm * pcm)1617 static int had_create_jack(struct snd_intelhad *ctx,
1618 struct snd_pcm *pcm)
1619 {
1620 char hdmi_str[32];
1621 int err;
1622
1623 snprintf(hdmi_str, sizeof(hdmi_str),
1624 "HDMI/DP,pcm=%d", pcm->device);
1625
1626 err = snd_jack_new(ctx->card_ctx->card, hdmi_str,
1627 SND_JACK_AVOUT, &ctx->jack,
1628 true, false);
1629 if (err < 0)
1630 return err;
1631 ctx->jack->private_data = ctx;
1632 return 0;
1633 }
1634
1635 /*
1636 * PM callbacks
1637 */
1638
hdmi_lpe_audio_suspend(struct device * dev)1639 static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev)
1640 {
1641 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1642
1643 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot);
1644
1645 return 0;
1646 }
1647
hdmi_lpe_audio_resume(struct device * dev)1648 static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev)
1649 {
1650 struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1651
1652 pm_runtime_mark_last_busy(dev);
1653
1654 snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0);
1655
1656 return 0;
1657 }
1658
1659 /* release resources */
hdmi_lpe_audio_free(struct snd_card * card)1660 static void hdmi_lpe_audio_free(struct snd_card *card)
1661 {
1662 struct snd_intelhad_card *card_ctx = card->private_data;
1663 struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data;
1664 int port;
1665
1666 spin_lock_irq(&pdata->lpe_audio_slock);
1667 pdata->notify_audio_lpe = NULL;
1668 spin_unlock_irq(&pdata->lpe_audio_slock);
1669
1670 for_each_port(card_ctx, port) {
1671 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1672
1673 cancel_work_sync(&ctx->hdmi_audio_wq);
1674 }
1675
1676 if (card_ctx->mmio_start)
1677 iounmap(card_ctx->mmio_start);
1678 if (card_ctx->irq >= 0)
1679 free_irq(card_ctx->irq, card_ctx);
1680 }
1681
1682 /*
1683 * hdmi_lpe_audio_probe - start bridge with i915
1684 *
1685 * This function is called when the i915 driver creates the
1686 * hdmi-lpe-audio platform device.
1687 */
hdmi_lpe_audio_probe(struct platform_device * pdev)1688 static int hdmi_lpe_audio_probe(struct platform_device *pdev)
1689 {
1690 struct snd_card *card;
1691 struct snd_intelhad_card *card_ctx;
1692 struct snd_intelhad *ctx;
1693 struct snd_pcm *pcm;
1694 struct intel_hdmi_lpe_audio_pdata *pdata;
1695 int irq;
1696 struct resource *res_mmio;
1697 int port, ret;
1698
1699 pdata = pdev->dev.platform_data;
1700 if (!pdata) {
1701 dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1702 return -EINVAL;
1703 }
1704
1705 /* get resources */
1706 irq = platform_get_irq(pdev, 0);
1707 if (irq < 0)
1708 return irq;
1709
1710 res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1711 if (!res_mmio) {
1712 dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1713 return -ENXIO;
1714 }
1715
1716 /* create a card instance with ALSA framework */
1717 ret = snd_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1718 THIS_MODULE, sizeof(*card_ctx), &card);
1719 if (ret)
1720 return ret;
1721
1722 card_ctx = card->private_data;
1723 card_ctx->dev = &pdev->dev;
1724 card_ctx->card = card;
1725 strcpy(card->driver, INTEL_HAD);
1726 strcpy(card->shortname, "Intel HDMI/DP LPE Audio");
1727 strcpy(card->longname, "Intel HDMI/DP LPE Audio");
1728
1729 card_ctx->irq = -1;
1730
1731 card->private_free = hdmi_lpe_audio_free;
1732
1733 platform_set_drvdata(pdev, card_ctx);
1734
1735 card_ctx->num_pipes = pdata->num_pipes;
1736 card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1737
1738 for_each_port(card_ctx, port) {
1739 ctx = &card_ctx->pcm_ctx[port];
1740 ctx->card_ctx = card_ctx;
1741 ctx->dev = card_ctx->dev;
1742 ctx->port = single_port ? -1 : port;
1743 ctx->pipe = -1;
1744
1745 spin_lock_init(&ctx->had_spinlock);
1746 mutex_init(&ctx->mutex);
1747 INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
1748 }
1749
1750 dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1751 __func__, (unsigned int)res_mmio->start,
1752 (unsigned int)res_mmio->end);
1753
1754 card_ctx->mmio_start = ioremap(res_mmio->start,
1755 (size_t)(resource_size(res_mmio)));
1756 if (!card_ctx->mmio_start) {
1757 dev_err(&pdev->dev, "Could not get ioremap\n");
1758 ret = -EACCES;
1759 goto err;
1760 }
1761
1762 /* setup interrupt handler */
1763 ret = request_irq(irq, display_pipe_interrupt_handler, 0,
1764 pdev->name, card_ctx);
1765 if (ret < 0) {
1766 dev_err(&pdev->dev, "request_irq failed\n");
1767 goto err;
1768 }
1769
1770 card_ctx->irq = irq;
1771
1772 /* only 32bit addressable */
1773 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1774 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1775
1776 init_channel_allocations();
1777
1778 card_ctx->num_pipes = pdata->num_pipes;
1779 card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1780
1781 for_each_port(card_ctx, port) {
1782 int i;
1783
1784 ctx = &card_ctx->pcm_ctx[port];
1785 ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS,
1786 MAX_CAP_STREAMS, &pcm);
1787 if (ret)
1788 goto err;
1789
1790 /* setup private data which can be retrieved when required */
1791 pcm->private_data = ctx;
1792 pcm->info_flags = 0;
1793 strlcpy(pcm->name, card->shortname, strlen(card->shortname));
1794 /* setup the ops for playabck */
1795 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
1796
1797 /* allocate dma pages;
1798 * try to allocate 600k buffer as default which is large enough
1799 */
1800 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_UC,
1801 card->dev, HAD_DEFAULT_BUFFER,
1802 HAD_MAX_BUFFER);
1803
1804 /* create controls */
1805 for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1806 struct snd_kcontrol *kctl;
1807
1808 kctl = snd_ctl_new1(&had_controls[i], ctx);
1809 if (!kctl) {
1810 ret = -ENOMEM;
1811 goto err;
1812 }
1813
1814 kctl->id.device = pcm->device;
1815
1816 ret = snd_ctl_add(card, kctl);
1817 if (ret < 0)
1818 goto err;
1819 }
1820
1821 /* Register channel map controls */
1822 ret = had_register_chmap_ctls(ctx, pcm);
1823 if (ret < 0)
1824 goto err;
1825
1826 ret = had_create_jack(ctx, pcm);
1827 if (ret < 0)
1828 goto err;
1829 }
1830
1831 ret = snd_card_register(card);
1832 if (ret)
1833 goto err;
1834
1835 spin_lock_irq(&pdata->lpe_audio_slock);
1836 pdata->notify_audio_lpe = notify_audio_lpe;
1837 spin_unlock_irq(&pdata->lpe_audio_slock);
1838
1839 pm_runtime_use_autosuspend(&pdev->dev);
1840 pm_runtime_mark_last_busy(&pdev->dev);
1841
1842 dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1843 for_each_port(card_ctx, port) {
1844 struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1845
1846 schedule_work(&ctx->hdmi_audio_wq);
1847 }
1848
1849 return 0;
1850
1851 err:
1852 snd_card_free(card);
1853 return ret;
1854 }
1855
1856 /*
1857 * hdmi_lpe_audio_remove - stop bridge with i915
1858 *
1859 * This function is called when the platform device is destroyed.
1860 */
hdmi_lpe_audio_remove(struct platform_device * pdev)1861 static int hdmi_lpe_audio_remove(struct platform_device *pdev)
1862 {
1863 struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1864
1865 snd_card_free(card_ctx->card);
1866 return 0;
1867 }
1868
1869 static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1870 SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1871 };
1872
1873 static struct platform_driver hdmi_lpe_audio_driver = {
1874 .driver = {
1875 .name = "hdmi-lpe-audio",
1876 .pm = &hdmi_lpe_audio_pm,
1877 },
1878 .probe = hdmi_lpe_audio_probe,
1879 .remove = hdmi_lpe_audio_remove,
1880 };
1881
1882 module_platform_driver(hdmi_lpe_audio_driver);
1883 MODULE_ALIAS("platform:hdmi_lpe_audio");
1884
1885 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1886 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1887 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1888 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1889 MODULE_DESCRIPTION("Intel HDMI Audio driver");
1890 MODULE_LICENSE("GPL v2");
1891 MODULE_SUPPORTED_DEVICE("{Intel,Intel_HAD}");
1892
