1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
7 //
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
12 //
13
14 /*
15 * Hardware interface for HDA DSP code loader
16 */
17
18 #include <linux/firmware.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/hda_register.h>
21 #include <sound/sof.h>
22 #include "../ops.h"
23 #include "hda.h"
24
25 #define HDA_FW_BOOT_ATTEMPTS 3
26 #define HDA_CL_STREAM_FORMAT 0x40
27
cl_stream_prepare(struct snd_sof_dev * sdev,unsigned int format,unsigned int size,struct snd_dma_buffer * dmab,int direction)28 static struct hdac_ext_stream *cl_stream_prepare(struct snd_sof_dev *sdev, unsigned int format,
29 unsigned int size, struct snd_dma_buffer *dmab,
30 int direction)
31 {
32 struct hdac_ext_stream *dsp_stream;
33 struct hdac_stream *hstream;
34 struct pci_dev *pci = to_pci_dev(sdev->dev);
35 int ret;
36
37 dsp_stream = hda_dsp_stream_get(sdev, direction);
38
39 if (!dsp_stream) {
40 dev_err(sdev->dev, "error: no stream available\n");
41 return ERR_PTR(-ENODEV);
42 }
43 hstream = &dsp_stream->hstream;
44 hstream->substream = NULL;
45
46 /* allocate DMA buffer */
47 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, &pci->dev, size, dmab);
48 if (ret < 0) {
49 dev_err(sdev->dev, "error: memory alloc failed: %x\n", ret);
50 goto error;
51 }
52
53 hstream->period_bytes = 0;/* initialize period_bytes */
54 hstream->format_val = format;
55 hstream->bufsize = size;
56
57 if (direction == SNDRV_PCM_STREAM_CAPTURE) {
58 ret = hda_dsp_iccmax_stream_hw_params(sdev, dsp_stream, dmab, NULL);
59 if (ret < 0) {
60 dev_err(sdev->dev, "error: iccmax stream prepare failed: %x\n", ret);
61 goto error;
62 }
63 } else {
64 ret = hda_dsp_stream_hw_params(sdev, dsp_stream, dmab, NULL);
65 if (ret < 0) {
66 dev_err(sdev->dev, "error: hdac prepare failed: %x\n", ret);
67 goto error;
68 }
69 hda_dsp_stream_spib_config(sdev, dsp_stream, HDA_DSP_SPIB_ENABLE, size);
70 }
71
72 return dsp_stream;
73
74 error:
75 hda_dsp_stream_put(sdev, direction, hstream->stream_tag);
76 snd_dma_free_pages(dmab);
77 return ERR_PTR(ret);
78 }
79
80 /*
81 * first boot sequence has some extra steps. core 0 waits for power
82 * status on core 1, so power up core 1 also momentarily, keep it in
83 * reset/stall and then turn it off
84 */
cl_dsp_init(struct snd_sof_dev * sdev,int stream_tag)85 static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag)
86 {
87 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
88 const struct sof_intel_dsp_desc *chip = hda->desc;
89 unsigned int status;
90 int ret;
91 int i;
92
93 /* step 1: power up corex */
94 ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
95 if (ret < 0) {
96 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
97 dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
98 goto err;
99 }
100
101 /* DSP is powered up, set all SSPs to slave mode */
102 for (i = 0; i < chip->ssp_count; i++) {
103 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
104 chip->ssp_base_offset
105 + i * SSP_DEV_MEM_SIZE
106 + SSP_SSC1_OFFSET,
107 SSP_SET_SLAVE,
108 SSP_SET_SLAVE);
109 }
110
111 /* step 2: purge FW request */
112 snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
113 chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
114 ((stream_tag - 1) << 9)));
115
116 /* step 3: unset core 0 reset state & unstall/run core 0 */
117 ret = hda_dsp_core_run(sdev, BIT(0));
118 if (ret < 0) {
119 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
120 dev_err(sdev->dev,
121 "error: dsp core start failed %d\n", ret);
122 ret = -EIO;
123 goto err;
124 }
125
126 /* step 4: wait for IPC DONE bit from ROM */
127 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
128 chip->ipc_ack, status,
129 ((status & chip->ipc_ack_mask)
130 == chip->ipc_ack_mask),
131 HDA_DSP_REG_POLL_INTERVAL_US,
132 HDA_DSP_INIT_TIMEOUT_US);
133
134 if (ret < 0) {
135 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
136 dev_err(sdev->dev,
137 "error: %s: timeout for HIPCIE done\n",
138 __func__);
139 goto err;
140 }
141
142 /* set DONE bit to clear the reply IPC message */
143 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
144 chip->ipc_ack,
145 chip->ipc_ack_mask,
146 chip->ipc_ack_mask);
147
148 /* step 5: power down corex */
149 ret = hda_dsp_core_power_down(sdev, chip->host_managed_cores_mask & ~(BIT(0)));
150 if (ret < 0) {
151 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
152 dev_err(sdev->dev,
153 "error: dsp core x power down failed\n");
154 goto err;
155 }
156
157 /* step 6: enable IPC interrupts */
158 hda_dsp_ipc_int_enable(sdev);
159
160 /* step 7: wait for ROM init */
161 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
162 HDA_DSP_SRAM_REG_ROM_STATUS, status,
163 ((status & HDA_DSP_ROM_STS_MASK)
164 == HDA_DSP_ROM_INIT),
165 HDA_DSP_REG_POLL_INTERVAL_US,
166 chip->rom_init_timeout *
167 USEC_PER_MSEC);
168 if (!ret)
169 return 0;
170
171 if (hda->boot_iteration == HDA_FW_BOOT_ATTEMPTS)
172 dev_err(sdev->dev,
173 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
174 __func__);
175
176 err:
177 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
178 hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
179
180 return ret;
181 }
182
cl_trigger(struct snd_sof_dev * sdev,struct hdac_ext_stream * stream,int cmd)183 static int cl_trigger(struct snd_sof_dev *sdev,
184 struct hdac_ext_stream *stream, int cmd)
185 {
186 struct hdac_stream *hstream = &stream->hstream;
187 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
188
189 /* code loader is special case that reuses stream ops */
190 switch (cmd) {
191 case SNDRV_PCM_TRIGGER_START:
192 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
193 1 << hstream->index,
194 1 << hstream->index);
195
196 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
197 sd_offset,
198 SOF_HDA_SD_CTL_DMA_START |
199 SOF_HDA_CL_DMA_SD_INT_MASK,
200 SOF_HDA_SD_CTL_DMA_START |
201 SOF_HDA_CL_DMA_SD_INT_MASK);
202
203 hstream->running = true;
204 return 0;
205 default:
206 return hda_dsp_stream_trigger(sdev, stream, cmd);
207 }
208 }
209
cl_cleanup(struct snd_sof_dev * sdev,struct snd_dma_buffer * dmab,struct hdac_ext_stream * stream)210 static int cl_cleanup(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
211 struct hdac_ext_stream *stream)
212 {
213 struct hdac_stream *hstream = &stream->hstream;
214 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
215 int ret = 0;
216
217 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK)
218 ret = hda_dsp_stream_spib_config(sdev, stream, HDA_DSP_SPIB_DISABLE, 0);
219 else
220 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
221 SOF_HDA_SD_CTL_DMA_START, 0);
222
223 hda_dsp_stream_put(sdev, hstream->direction, hstream->stream_tag);
224 hstream->running = 0;
225 hstream->substream = NULL;
226
227 /* reset BDL address */
228 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
229 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL, 0);
230 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
231 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU, 0);
232
233 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset, 0);
234 snd_dma_free_pages(dmab);
235 dmab->area = NULL;
236 hstream->bufsize = 0;
237 hstream->format_val = 0;
238
239 return ret;
240 }
241
cl_copy_fw(struct snd_sof_dev * sdev,struct hdac_ext_stream * stream)242 static int cl_copy_fw(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream)
243 {
244 unsigned int reg;
245 int ret, status;
246
247 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_START);
248 if (ret < 0) {
249 dev_err(sdev->dev, "error: DMA trigger start failed\n");
250 return ret;
251 }
252
253 status = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
254 HDA_DSP_SRAM_REG_ROM_STATUS, reg,
255 ((reg & HDA_DSP_ROM_STS_MASK)
256 == HDA_DSP_ROM_FW_ENTERED),
257 HDA_DSP_REG_POLL_INTERVAL_US,
258 HDA_DSP_BASEFW_TIMEOUT_US);
259
260 /*
261 * even in case of errors we still need to stop the DMAs,
262 * but we return the initial error should the DMA stop also fail
263 */
264
265 if (status < 0) {
266 dev_err(sdev->dev,
267 "error: %s: timeout HDA_DSP_SRAM_REG_ROM_STATUS read\n",
268 __func__);
269 }
270
271 ret = cl_trigger(sdev, stream, SNDRV_PCM_TRIGGER_STOP);
272 if (ret < 0) {
273 dev_err(sdev->dev, "error: DMA trigger stop failed\n");
274 if (!status)
275 status = ret;
276 }
277
278 return status;
279 }
280
hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev * sdev)281 int hda_dsp_cl_boot_firmware_iccmax(struct snd_sof_dev *sdev)
282 {
283 struct snd_sof_pdata *plat_data = sdev->pdata;
284 struct hdac_ext_stream *iccmax_stream;
285 struct hdac_bus *bus = sof_to_bus(sdev);
286 struct firmware stripped_firmware;
287 int ret, ret1;
288 u8 original_gb;
289
290 /* save the original LTRP guardband value */
291 original_gb = snd_hdac_chip_readb(bus, VS_LTRP) & HDA_VS_INTEL_LTRP_GB_MASK;
292
293 if (plat_data->fw->size <= plat_data->fw_offset) {
294 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
295 return -EINVAL;
296 }
297
298 stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
299
300 /* prepare capture stream for ICCMAX */
301 iccmax_stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size,
302 &sdev->dmab_bdl, SNDRV_PCM_STREAM_CAPTURE);
303 if (IS_ERR(iccmax_stream)) {
304 dev_err(sdev->dev, "error: dma prepare for ICCMAX stream failed\n");
305 return PTR_ERR(iccmax_stream);
306 }
307
308 ret = hda_dsp_cl_boot_firmware(sdev);
309
310 /*
311 * Perform iccmax stream cleanup. This should be done even if firmware loading fails.
312 * If the cleanup also fails, we return the initial error
313 */
314 ret1 = cl_cleanup(sdev, &sdev->dmab_bdl, iccmax_stream);
315 if (ret1 < 0) {
316 dev_err(sdev->dev, "error: ICCMAX stream cleanup failed\n");
317
318 /* set return value to indicate cleanup failure */
319 if (!ret)
320 ret = ret1;
321 }
322
323 /* restore the original guardband value after FW boot */
324 snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, original_gb);
325
326 return ret;
327 }
328
hda_dsp_cl_boot_firmware(struct snd_sof_dev * sdev)329 int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
330 {
331 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
332 struct snd_sof_pdata *plat_data = sdev->pdata;
333 const struct sof_dev_desc *desc = plat_data->desc;
334 const struct sof_intel_dsp_desc *chip_info;
335 struct hdac_ext_stream *stream;
336 struct firmware stripped_firmware;
337 int ret, ret1, i;
338
339 chip_info = desc->chip_info;
340
341 if (plat_data->fw->size <= plat_data->fw_offset) {
342 dev_err(sdev->dev, "error: firmware size must be greater than firmware offset\n");
343 return -EINVAL;
344 }
345
346 stripped_firmware.data = plat_data->fw->data + plat_data->fw_offset;
347 stripped_firmware.size = plat_data->fw->size - plat_data->fw_offset;
348
349 /* init for booting wait */
350 init_waitqueue_head(&sdev->boot_wait);
351
352 /* prepare DMA for code loader stream */
353 stream = cl_stream_prepare(sdev, HDA_CL_STREAM_FORMAT, stripped_firmware.size,
354 &sdev->dmab, SNDRV_PCM_STREAM_PLAYBACK);
355 if (IS_ERR(stream)) {
356 dev_err(sdev->dev, "error: dma prepare for fw loading failed\n");
357 return PTR_ERR(stream);
358 }
359
360 memcpy(sdev->dmab.area, stripped_firmware.data,
361 stripped_firmware.size);
362
363 /* try ROM init a few times before giving up */
364 for (i = 0; i < HDA_FW_BOOT_ATTEMPTS; i++) {
365 dev_dbg(sdev->dev,
366 "Attempting iteration %d of Core En/ROM load...\n", i);
367
368 hda->boot_iteration = i + 1;
369 ret = cl_dsp_init(sdev, stream->hstream.stream_tag);
370
371 /* don't retry anymore if successful */
372 if (!ret)
373 break;
374 }
375
376 if (i == HDA_FW_BOOT_ATTEMPTS) {
377 dev_err(sdev->dev, "error: dsp init failed after %d attempts with err: %d\n",
378 i, ret);
379 dev_err(sdev->dev, "ROM error=0x%x: FW status=0x%x\n",
380 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
381 HDA_DSP_SRAM_REG_ROM_ERROR),
382 snd_sof_dsp_read(sdev, HDA_DSP_BAR,
383 HDA_DSP_SRAM_REG_ROM_STATUS));
384 goto cleanup;
385 }
386
387 /*
388 * When a SoundWire link is in clock stop state, a Slave
389 * device may trigger in-band wakes for events such as jack
390 * insertion or acoustic event detection. This event will lead
391 * to a WAKEEN interrupt, handled by the PCI device and routed
392 * to PME if the PCI device is in D3. The resume function in
393 * audio PCI driver will be invoked by ACPI for PME event and
394 * initialize the device and process WAKEEN interrupt.
395 *
396 * The WAKEEN interrupt should be processed ASAP to prevent an
397 * interrupt flood, otherwise other interrupts, such IPC,
398 * cannot work normally. The WAKEEN is handled after the ROM
399 * is initialized successfully, which ensures power rails are
400 * enabled before accessing the SoundWire SHIM registers
401 */
402 if (!sdev->first_boot)
403 hda_sdw_process_wakeen(sdev);
404
405 /*
406 * at this point DSP ROM has been initialized and
407 * should be ready for code loading and firmware boot
408 */
409 ret = cl_copy_fw(sdev, stream);
410 if (!ret)
411 dev_dbg(sdev->dev, "Firmware download successful, booting...\n");
412 else
413 dev_err(sdev->dev, "error: load fw failed ret: %d\n", ret);
414
415 cleanup:
416 /*
417 * Perform codeloader stream cleanup.
418 * This should be done even if firmware loading fails.
419 * If the cleanup also fails, we return the initial error
420 */
421 ret1 = cl_cleanup(sdev, &sdev->dmab, stream);
422 if (ret1 < 0) {
423 dev_err(sdev->dev, "error: Code loader DSP cleanup failed\n");
424
425 /* set return value to indicate cleanup failure */
426 if (!ret)
427 ret = ret1;
428 }
429
430 /*
431 * return primary core id if both fw copy
432 * and stream clean up are successful
433 */
434 if (!ret)
435 return chip_info->init_core_mask;
436
437 /* dump dsp registers and disable DSP upon error */
438 hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
439
440 /* disable DSP */
441 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
442 SOF_HDA_REG_PP_PPCTL,
443 SOF_HDA_PPCTL_GPROCEN, 0);
444 return ret;
445 }
446
447 /* pre fw run operations */
hda_dsp_pre_fw_run(struct snd_sof_dev * sdev)448 int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev)
449 {
450 /* disable clock gating and power gating */
451 return hda_dsp_ctrl_clock_power_gating(sdev, false);
452 }
453
454 /* post fw run operations */
hda_dsp_post_fw_run(struct snd_sof_dev * sdev)455 int hda_dsp_post_fw_run(struct snd_sof_dev *sdev)
456 {
457 int ret;
458
459 if (sdev->first_boot) {
460 ret = hda_sdw_startup(sdev);
461 if (ret < 0) {
462 dev_err(sdev->dev,
463 "error: could not startup SoundWire links\n");
464 return ret;
465 }
466 }
467
468 hda_sdw_int_enable(sdev, true);
469
470 /* re-enable clock gating and power gating */
471 return hda_dsp_ctrl_clock_power_gating(sdev, true);
472 }
473
