1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 //
3 // Copyright (c) 2018 BayLibre, SAS.
4 // Author: Jerome Brunet <jbrunet@baylibre.com>
5
6 /* This driver implements the frontend capture DAI of AXG based SoCs */
7
8 #include <linux/clk.h>
9 #include <linux/regmap.h>
10 #include <linux/module.h>
11 #include <linux/of_platform.h>
12 #include <sound/pcm_params.h>
13 #include <sound/soc.h>
14 #include <sound/soc-dai.h>
15
16 #include "axg-fifo.h"
17
18 #define CTRL0_TODDR_SEL_RESAMPLE BIT(30)
19 #define CTRL0_TODDR_EXT_SIGNED BIT(29)
20 #define CTRL0_TODDR_PP_MODE BIT(28)
21 #define CTRL0_TODDR_SYNC_CH BIT(27)
22 #define CTRL0_TODDR_TYPE_MASK GENMASK(15, 13)
23 #define CTRL0_TODDR_TYPE(x) ((x) << 13)
24 #define CTRL0_TODDR_MSB_POS_MASK GENMASK(12, 8)
25 #define CTRL0_TODDR_MSB_POS(x) ((x) << 8)
26 #define CTRL0_TODDR_LSB_POS_MASK GENMASK(7, 3)
27 #define CTRL0_TODDR_LSB_POS(x) ((x) << 3)
28 #define CTRL1_TODDR_FORCE_FINISH BIT(25)
29 #define CTRL1_SEL_SHIFT 28
30
31 #define TODDR_MSB_POS 31
32
axg_toddr_pcm_new(struct snd_soc_pcm_runtime * rtd,struct snd_soc_dai * dai)33 static int axg_toddr_pcm_new(struct snd_soc_pcm_runtime *rtd,
34 struct snd_soc_dai *dai)
35 {
36 return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_CAPTURE);
37 }
38
g12a_toddr_dai_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)39 static int g12a_toddr_dai_prepare(struct snd_pcm_substream *substream,
40 struct snd_soc_dai *dai)
41 {
42 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
43
44 /* Reset the write pointer to the FIFO_INIT_ADDR */
45 regmap_update_bits(fifo->map, FIFO_CTRL1,
46 CTRL1_TODDR_FORCE_FINISH, 0);
47 regmap_update_bits(fifo->map, FIFO_CTRL1,
48 CTRL1_TODDR_FORCE_FINISH, CTRL1_TODDR_FORCE_FINISH);
49 regmap_update_bits(fifo->map, FIFO_CTRL1,
50 CTRL1_TODDR_FORCE_FINISH, 0);
51
52 return 0;
53 }
54
axg_toddr_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)55 static int axg_toddr_dai_hw_params(struct snd_pcm_substream *substream,
56 struct snd_pcm_hw_params *params,
57 struct snd_soc_dai *dai)
58 {
59 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
60 unsigned int type, width;
61
62 switch (params_physical_width(params)) {
63 case 8:
64 type = 0; /* 8 samples of 8 bits */
65 break;
66 case 16:
67 type = 2; /* 4 samples of 16 bits - right justified */
68 break;
69 case 32:
70 type = 4; /* 2 samples of 32 bits - right justified */
71 break;
72 default:
73 return -EINVAL;
74 }
75
76 width = params_width(params);
77
78 regmap_update_bits(fifo->map, FIFO_CTRL0,
79 CTRL0_TODDR_TYPE_MASK |
80 CTRL0_TODDR_MSB_POS_MASK |
81 CTRL0_TODDR_LSB_POS_MASK,
82 CTRL0_TODDR_TYPE(type) |
83 CTRL0_TODDR_MSB_POS(TODDR_MSB_POS) |
84 CTRL0_TODDR_LSB_POS(TODDR_MSB_POS - (width - 1)));
85
86 return 0;
87 }
88
axg_toddr_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)89 static int axg_toddr_dai_startup(struct snd_pcm_substream *substream,
90 struct snd_soc_dai *dai)
91 {
92 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
93 int ret;
94
95 /* Enable pclk to access registers and clock the fifo ip */
96 ret = clk_prepare_enable(fifo->pclk);
97 if (ret)
98 return ret;
99
100 /* Select orginal data - resampling not supported ATM */
101 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SEL_RESAMPLE, 0);
102
103 /* Only signed format are supported ATM */
104 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_EXT_SIGNED,
105 CTRL0_TODDR_EXT_SIGNED);
106
107 /* Apply single buffer mode to the interface */
108 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_PP_MODE, 0);
109
110 return 0;
111 }
112
axg_toddr_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)113 static void axg_toddr_dai_shutdown(struct snd_pcm_substream *substream,
114 struct snd_soc_dai *dai)
115 {
116 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
117
118 clk_disable_unprepare(fifo->pclk);
119 }
120
121 static const struct snd_soc_dai_ops axg_toddr_ops = {
122 .hw_params = axg_toddr_dai_hw_params,
123 .startup = axg_toddr_dai_startup,
124 .shutdown = axg_toddr_dai_shutdown,
125 };
126
127 static struct snd_soc_dai_driver axg_toddr_dai_drv = {
128 .name = "TODDR",
129 .capture = {
130 .stream_name = "Capture",
131 .channels_min = 1,
132 .channels_max = AXG_FIFO_CH_MAX,
133 .rates = AXG_FIFO_RATES,
134 .formats = AXG_FIFO_FORMATS,
135 },
136 .ops = &axg_toddr_ops,
137 .pcm_new = axg_toddr_pcm_new,
138 };
139
140 static const char * const axg_toddr_sel_texts[] = {
141 "IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7"
142 };
143
144 static SOC_ENUM_SINGLE_DECL(axg_toddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
145 axg_toddr_sel_texts);
146
147 static const struct snd_kcontrol_new axg_toddr_in_mux =
148 SOC_DAPM_ENUM("Input Source", axg_toddr_sel_enum);
149
150 static const struct snd_soc_dapm_widget axg_toddr_dapm_widgets[] = {
151 SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &axg_toddr_in_mux),
152 SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
153 SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
154 SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
155 SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0),
156 SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0),
157 SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0),
158 SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0),
159 SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0),
160 };
161
162 static const struct snd_soc_dapm_route axg_toddr_dapm_routes[] = {
163 { "Capture", NULL, "SRC SEL" },
164 { "SRC SEL", "IN 0", "IN 0" },
165 { "SRC SEL", "IN 1", "IN 1" },
166 { "SRC SEL", "IN 2", "IN 2" },
167 { "SRC SEL", "IN 3", "IN 3" },
168 { "SRC SEL", "IN 4", "IN 4" },
169 { "SRC SEL", "IN 5", "IN 5" },
170 { "SRC SEL", "IN 6", "IN 6" },
171 { "SRC SEL", "IN 7", "IN 7" },
172 };
173
174 static const struct snd_soc_component_driver axg_toddr_component_drv = {
175 .dapm_widgets = axg_toddr_dapm_widgets,
176 .num_dapm_widgets = ARRAY_SIZE(axg_toddr_dapm_widgets),
177 .dapm_routes = axg_toddr_dapm_routes,
178 .num_dapm_routes = ARRAY_SIZE(axg_toddr_dapm_routes),
179 .open = axg_fifo_pcm_open,
180 .close = axg_fifo_pcm_close,
181 .hw_params = axg_fifo_pcm_hw_params,
182 .hw_free = axg_fifo_pcm_hw_free,
183 .pointer = axg_fifo_pcm_pointer,
184 .trigger = axg_fifo_pcm_trigger,
185 };
186
187 static const struct axg_fifo_match_data axg_toddr_match_data = {
188 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
189 .component_drv = &axg_toddr_component_drv,
190 .dai_drv = &axg_toddr_dai_drv
191 };
192
g12a_toddr_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)193 static int g12a_toddr_dai_startup(struct snd_pcm_substream *substream,
194 struct snd_soc_dai *dai)
195 {
196 struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
197 int ret;
198
199 ret = axg_toddr_dai_startup(substream, dai);
200 if (ret)
201 return ret;
202
203 /*
204 * Make sure the first channel ends up in the at beginning of the output
205 * As weird as it looks, without this the first channel may be misplaced
206 * in memory, with a random shift of 2 channels.
207 */
208 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_TODDR_SYNC_CH,
209 CTRL0_TODDR_SYNC_CH);
210
211 return 0;
212 }
213
214 static const struct snd_soc_dai_ops g12a_toddr_ops = {
215 .prepare = g12a_toddr_dai_prepare,
216 .hw_params = axg_toddr_dai_hw_params,
217 .startup = g12a_toddr_dai_startup,
218 .shutdown = axg_toddr_dai_shutdown,
219 };
220
221 static struct snd_soc_dai_driver g12a_toddr_dai_drv = {
222 .name = "TODDR",
223 .capture = {
224 .stream_name = "Capture",
225 .channels_min = 1,
226 .channels_max = AXG_FIFO_CH_MAX,
227 .rates = AXG_FIFO_RATES,
228 .formats = AXG_FIFO_FORMATS,
229 },
230 .ops = &g12a_toddr_ops,
231 .pcm_new = axg_toddr_pcm_new,
232 };
233
234 static const struct snd_soc_component_driver g12a_toddr_component_drv = {
235 .dapm_widgets = axg_toddr_dapm_widgets,
236 .num_dapm_widgets = ARRAY_SIZE(axg_toddr_dapm_widgets),
237 .dapm_routes = axg_toddr_dapm_routes,
238 .num_dapm_routes = ARRAY_SIZE(axg_toddr_dapm_routes),
239 .open = axg_fifo_pcm_open,
240 .close = axg_fifo_pcm_close,
241 .hw_params = g12a_fifo_pcm_hw_params,
242 .hw_free = axg_fifo_pcm_hw_free,
243 .pointer = axg_fifo_pcm_pointer,
244 .trigger = axg_fifo_pcm_trigger,
245 };
246
247 static const struct axg_fifo_match_data g12a_toddr_match_data = {
248 .field_threshold = REG_FIELD(FIFO_CTRL1, 16, 23),
249 .component_drv = &g12a_toddr_component_drv,
250 .dai_drv = &g12a_toddr_dai_drv
251 };
252
253 static const char * const sm1_toddr_sel_texts[] = {
254 "IN 0", "IN 1", "IN 2", "IN 3", "IN 4", "IN 5", "IN 6", "IN 7",
255 "IN 8", "IN 9", "IN 10", "IN 11", "IN 12", "IN 13", "IN 14", "IN 15"
256 };
257
258 static SOC_ENUM_SINGLE_DECL(sm1_toddr_sel_enum, FIFO_CTRL1, CTRL1_SEL_SHIFT,
259 sm1_toddr_sel_texts);
260
261 static const struct snd_kcontrol_new sm1_toddr_in_mux =
262 SOC_DAPM_ENUM("Input Source", sm1_toddr_sel_enum);
263
264 static const struct snd_soc_dapm_widget sm1_toddr_dapm_widgets[] = {
265 SND_SOC_DAPM_MUX("SRC SEL", SND_SOC_NOPM, 0, 0, &sm1_toddr_in_mux),
266 SND_SOC_DAPM_AIF_IN("IN 0", NULL, 0, SND_SOC_NOPM, 0, 0),
267 SND_SOC_DAPM_AIF_IN("IN 1", NULL, 0, SND_SOC_NOPM, 0, 0),
268 SND_SOC_DAPM_AIF_IN("IN 2", NULL, 0, SND_SOC_NOPM, 0, 0),
269 SND_SOC_DAPM_AIF_IN("IN 3", NULL, 0, SND_SOC_NOPM, 0, 0),
270 SND_SOC_DAPM_AIF_IN("IN 4", NULL, 0, SND_SOC_NOPM, 0, 0),
271 SND_SOC_DAPM_AIF_IN("IN 5", NULL, 0, SND_SOC_NOPM, 0, 0),
272 SND_SOC_DAPM_AIF_IN("IN 6", NULL, 0, SND_SOC_NOPM, 0, 0),
273 SND_SOC_DAPM_AIF_IN("IN 7", NULL, 0, SND_SOC_NOPM, 0, 0),
274 SND_SOC_DAPM_AIF_IN("IN 8", NULL, 0, SND_SOC_NOPM, 0, 0),
275 SND_SOC_DAPM_AIF_IN("IN 9", NULL, 0, SND_SOC_NOPM, 0, 0),
276 SND_SOC_DAPM_AIF_IN("IN 10", NULL, 0, SND_SOC_NOPM, 0, 0),
277 SND_SOC_DAPM_AIF_IN("IN 11", NULL, 0, SND_SOC_NOPM, 0, 0),
278 SND_SOC_DAPM_AIF_IN("IN 12", NULL, 0, SND_SOC_NOPM, 0, 0),
279 SND_SOC_DAPM_AIF_IN("IN 13", NULL, 0, SND_SOC_NOPM, 0, 0),
280 SND_SOC_DAPM_AIF_IN("IN 14", NULL, 0, SND_SOC_NOPM, 0, 0),
281 SND_SOC_DAPM_AIF_IN("IN 15", NULL, 0, SND_SOC_NOPM, 0, 0),
282 };
283
284 static const struct snd_soc_dapm_route sm1_toddr_dapm_routes[] = {
285 { "Capture", NULL, "SRC SEL" },
286 { "SRC SEL", "IN 0", "IN 0" },
287 { "SRC SEL", "IN 1", "IN 1" },
288 { "SRC SEL", "IN 2", "IN 2" },
289 { "SRC SEL", "IN 3", "IN 3" },
290 { "SRC SEL", "IN 4", "IN 4" },
291 { "SRC SEL", "IN 5", "IN 5" },
292 { "SRC SEL", "IN 6", "IN 6" },
293 { "SRC SEL", "IN 7", "IN 7" },
294 { "SRC SEL", "IN 8", "IN 8" },
295 { "SRC SEL", "IN 9", "IN 9" },
296 { "SRC SEL", "IN 10", "IN 10" },
297 { "SRC SEL", "IN 11", "IN 11" },
298 { "SRC SEL", "IN 12", "IN 12" },
299 { "SRC SEL", "IN 13", "IN 13" },
300 { "SRC SEL", "IN 14", "IN 14" },
301 { "SRC SEL", "IN 15", "IN 15" },
302 };
303
304 static const struct snd_soc_component_driver sm1_toddr_component_drv = {
305 .dapm_widgets = sm1_toddr_dapm_widgets,
306 .num_dapm_widgets = ARRAY_SIZE(sm1_toddr_dapm_widgets),
307 .dapm_routes = sm1_toddr_dapm_routes,
308 .num_dapm_routes = ARRAY_SIZE(sm1_toddr_dapm_routes),
309 .open = axg_fifo_pcm_open,
310 .close = axg_fifo_pcm_close,
311 .hw_params = g12a_fifo_pcm_hw_params,
312 .hw_free = axg_fifo_pcm_hw_free,
313 .pointer = axg_fifo_pcm_pointer,
314 .trigger = axg_fifo_pcm_trigger,
315 };
316
317 static const struct axg_fifo_match_data sm1_toddr_match_data = {
318 .field_threshold = REG_FIELD(FIFO_CTRL1, 12, 23),
319 .component_drv = &sm1_toddr_component_drv,
320 .dai_drv = &g12a_toddr_dai_drv
321 };
322
323 static const struct of_device_id axg_toddr_of_match[] = {
324 {
325 .compatible = "amlogic,axg-toddr",
326 .data = &axg_toddr_match_data,
327 }, {
328 .compatible = "amlogic,g12a-toddr",
329 .data = &g12a_toddr_match_data,
330 }, {
331 .compatible = "amlogic,sm1-toddr",
332 .data = &sm1_toddr_match_data,
333 }, {}
334 };
335 MODULE_DEVICE_TABLE(of, axg_toddr_of_match);
336
337 static struct platform_driver axg_toddr_pdrv = {
338 .probe = axg_fifo_probe,
339 .driver = {
340 .name = "axg-toddr",
341 .of_match_table = axg_toddr_of_match,
342 },
343 };
344 module_platform_driver(axg_toddr_pdrv);
345
346 MODULE_DESCRIPTION("Amlogic AXG capture fifo driver");
347 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
348 MODULE_LICENSE("GPL v2");
349
