1 /*
2 * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com)
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9 #ifndef __DESIGNWARE_LOCAL_H
10 #define __DESIGNWARE_LOCAL_H
11
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/types.h>
15 #include <sound/dmaengine_pcm.h>
16 #include <sound/pcm.h>
17 #include <sound/designware_i2s.h>
18
19 /* common register for all channel */
20 #define IER 0x000
21 #define IRER 0x004
22 #define ITER 0x008
23 #define CER 0x00C
24 #define CCR 0x010
25 #define RXFFR 0x014
26 #define TXFFR 0x018
27
28 /* Interrupt status register fields */
29 #define ISR_TXFO BIT(5)
30 #define ISR_TXFE BIT(4)
31 #define ISR_RXFO BIT(1)
32 #define ISR_RXDA BIT(0)
33
34 /* I2STxRxRegisters for all channels */
35 #define LRBR_LTHR(x) (0x40 * x + 0x020)
36 #define RRBR_RTHR(x) (0x40 * x + 0x024)
37 #define RER(x) (0x40 * x + 0x028)
38 #define TER(x) (0x40 * x + 0x02C)
39 #define RCR(x) (0x40 * x + 0x030)
40 #define TCR(x) (0x40 * x + 0x034)
41 #define ISR(x) (0x40 * x + 0x038)
42 #define IMR(x) (0x40 * x + 0x03C)
43 #define ROR(x) (0x40 * x + 0x040)
44 #define TOR(x) (0x40 * x + 0x044)
45 #define RFCR(x) (0x40 * x + 0x048)
46 #define TFCR(x) (0x40 * x + 0x04C)
47 #define RFF(x) (0x40 * x + 0x050)
48 #define TFF(x) (0x40 * x + 0x054)
49
50 /* I2SCOMPRegisters */
51 #define I2S_COMP_PARAM_2 0x01F0
52 #define I2S_COMP_PARAM_1 0x01F4
53 #define I2S_COMP_VERSION 0x01F8
54 #define I2S_COMP_TYPE 0x01FC
55
56 /*
57 * Component parameter register fields - define the I2S block's
58 * configuration.
59 */
60 #define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25)
61 #define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22)
62 #define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19)
63 #define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16)
64 #define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9)
65 #define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7)
66 #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6)
67 #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5)
68 #define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4)
69 #define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2)
70 #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)
71
72 #define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10)
73 #define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7)
74 #define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3)
75 #define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0)
76
77 /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
78 #define COMP_MAX_WORDSIZE (1 << 3)
79 #define COMP_MAX_DATA_WIDTH (1 << 2)
80
81 #define MAX_CHANNEL_NUM 8
82 #define MIN_CHANNEL_NUM 2
83
84 union dw_i2s_snd_dma_data {
85 struct i2s_dma_data pd;
86 struct snd_dmaengine_dai_dma_data dt;
87 };
88
89 struct dw_i2s_dev {
90 void __iomem *i2s_base;
91 struct clk *clk;
92 int active;
93 unsigned int capability;
94 unsigned int quirks;
95 unsigned int i2s_reg_comp1;
96 unsigned int i2s_reg_comp2;
97 struct device *dev;
98 u32 ccr;
99 u32 xfer_resolution;
100 u32 fifo_th;
101
102 /* data related to DMA transfers b/w i2s and DMAC */
103 union dw_i2s_snd_dma_data play_dma_data;
104 union dw_i2s_snd_dma_data capture_dma_data;
105 struct i2s_clk_config_data config;
106 int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
107
108 /* data related to PIO transfers */
109 bool use_pio;
110 struct snd_pcm_substream __rcu *tx_substream;
111 struct snd_pcm_substream __rcu *rx_substream;
112 unsigned int (*tx_fn)(struct dw_i2s_dev *dev,
113 struct snd_pcm_runtime *runtime, unsigned int tx_ptr,
114 bool *period_elapsed);
115 unsigned int (*rx_fn)(struct dw_i2s_dev *dev,
116 struct snd_pcm_runtime *runtime, unsigned int rx_ptr,
117 bool *period_elapsed);
118 unsigned int tx_ptr;
119 unsigned int rx_ptr;
120 };
121
122 #if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM)
123 void dw_pcm_push_tx(struct dw_i2s_dev *dev);
124 void dw_pcm_pop_rx(struct dw_i2s_dev *dev);
125 int dw_pcm_register(struct platform_device *pdev);
126 #else
dw_pcm_push_tx(struct dw_i2s_dev * dev)127 void dw_pcm_push_tx(struct dw_i2s_dev *dev) { }
dw_pcm_pop_rx(struct dw_i2s_dev * dev)128 void dw_pcm_pop_rx(struct dw_i2s_dev *dev) { }
dw_pcm_register(struct platform_device * pdev)129 int dw_pcm_register(struct platform_device *pdev)
130 {
131 return -EINVAL;
132 }
133 #endif
134
135 #endif
136
