1 /* 2 * Virtio GPU Device 3 * 4 * Copyright Red Hat, Inc. 2013-2014 5 * 6 * Authors: 7 * Dave Airlie <airlied@redhat.com> 8 * Gerd Hoffmann <kraxel@redhat.com> 9 * 10 * This header is BSD licensed so anyone can use the definitions 11 * to implement compatible drivers/servers: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. Neither the name of IBM nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 27 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL IBM OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 31 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 32 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 34 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 */ 37 38 #ifndef VIRTIO_GPU_HW_H 39 #define VIRTIO_GPU_HW_H 40 41 #include <linux/types.h> 42 43 /* 44 * VIRTIO_GPU_CMD_CTX_* 45 * VIRTIO_GPU_CMD_*_3D 46 */ 47 #define VIRTIO_GPU_F_VIRGL 0 48 49 /* 50 * VIRTIO_GPU_CMD_GET_EDID 51 */ 52 #define VIRTIO_GPU_F_EDID 1 53 /* 54 * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID 55 */ 56 #define VIRTIO_GPU_F_RESOURCE_UUID 2 57 58 enum virtio_gpu_ctrl_type { 59 VIRTIO_GPU_UNDEFINED = 0, 60 61 /* 2d commands */ 62 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 63 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 64 VIRTIO_GPU_CMD_RESOURCE_UNREF, 65 VIRTIO_GPU_CMD_SET_SCANOUT, 66 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 67 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 68 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 69 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 70 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 71 VIRTIO_GPU_CMD_GET_CAPSET, 72 VIRTIO_GPU_CMD_GET_EDID, 73 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID, 74 75 /* 3d commands */ 76 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 77 VIRTIO_GPU_CMD_CTX_DESTROY, 78 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 79 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 80 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 81 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 82 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 83 VIRTIO_GPU_CMD_SUBMIT_3D, 84 85 /* cursor commands */ 86 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 87 VIRTIO_GPU_CMD_MOVE_CURSOR, 88 89 /* success responses */ 90 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 91 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 92 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 93 VIRTIO_GPU_RESP_OK_CAPSET, 94 VIRTIO_GPU_RESP_OK_EDID, 95 VIRTIO_GPU_RESP_OK_RESOURCE_UUID, 96 97 /* error responses */ 98 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 99 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 100 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 101 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 102 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 103 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 104 }; 105 106 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 107 108 struct virtio_gpu_ctrl_hdr { 109 __le32 type; 110 __le32 flags; 111 __le64 fence_id; 112 __le32 ctx_id; 113 __le32 padding; 114 }; 115 116 /* data passed in the cursor vq */ 117 118 struct virtio_gpu_cursor_pos { 119 __le32 scanout_id; 120 __le32 x; 121 __le32 y; 122 __le32 padding; 123 }; 124 125 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */ 126 struct virtio_gpu_update_cursor { 127 struct virtio_gpu_ctrl_hdr hdr; 128 struct virtio_gpu_cursor_pos pos; /* update & move */ 129 __le32 resource_id; /* update only */ 130 __le32 hot_x; /* update only */ 131 __le32 hot_y; /* update only */ 132 __le32 padding; 133 }; 134 135 /* data passed in the control vq, 2d related */ 136 137 struct virtio_gpu_rect { 138 __le32 x; 139 __le32 y; 140 __le32 width; 141 __le32 height; 142 }; 143 144 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */ 145 struct virtio_gpu_resource_unref { 146 struct virtio_gpu_ctrl_hdr hdr; 147 __le32 resource_id; 148 __le32 padding; 149 }; 150 151 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */ 152 struct virtio_gpu_resource_create_2d { 153 struct virtio_gpu_ctrl_hdr hdr; 154 __le32 resource_id; 155 __le32 format; 156 __le32 width; 157 __le32 height; 158 }; 159 160 /* VIRTIO_GPU_CMD_SET_SCANOUT */ 161 struct virtio_gpu_set_scanout { 162 struct virtio_gpu_ctrl_hdr hdr; 163 struct virtio_gpu_rect r; 164 __le32 scanout_id; 165 __le32 resource_id; 166 }; 167 168 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */ 169 struct virtio_gpu_resource_flush { 170 struct virtio_gpu_ctrl_hdr hdr; 171 struct virtio_gpu_rect r; 172 __le32 resource_id; 173 __le32 padding; 174 }; 175 176 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */ 177 struct virtio_gpu_transfer_to_host_2d { 178 struct virtio_gpu_ctrl_hdr hdr; 179 struct virtio_gpu_rect r; 180 __le64 offset; 181 __le32 resource_id; 182 __le32 padding; 183 }; 184 185 struct virtio_gpu_mem_entry { 186 __le64 addr; 187 __le32 length; 188 __le32 padding; 189 }; 190 191 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */ 192 struct virtio_gpu_resource_attach_backing { 193 struct virtio_gpu_ctrl_hdr hdr; 194 __le32 resource_id; 195 __le32 nr_entries; 196 }; 197 198 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */ 199 struct virtio_gpu_resource_detach_backing { 200 struct virtio_gpu_ctrl_hdr hdr; 201 __le32 resource_id; 202 __le32 padding; 203 }; 204 205 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */ 206 #define VIRTIO_GPU_MAX_SCANOUTS 16 207 struct virtio_gpu_resp_display_info { 208 struct virtio_gpu_ctrl_hdr hdr; 209 struct virtio_gpu_display_one { 210 struct virtio_gpu_rect r; 211 __le32 enabled; 212 __le32 flags; 213 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 214 }; 215 216 /* data passed in the control vq, 3d related */ 217 218 struct virtio_gpu_box { 219 __le32 x, y, z; 220 __le32 w, h, d; 221 }; 222 223 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */ 224 struct virtio_gpu_transfer_host_3d { 225 struct virtio_gpu_ctrl_hdr hdr; 226 struct virtio_gpu_box box; 227 __le64 offset; 228 __le32 resource_id; 229 __le32 level; 230 __le32 stride; 231 __le32 layer_stride; 232 }; 233 234 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */ 235 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 236 struct virtio_gpu_resource_create_3d { 237 struct virtio_gpu_ctrl_hdr hdr; 238 __le32 resource_id; 239 __le32 target; 240 __le32 format; 241 __le32 bind; 242 __le32 width; 243 __le32 height; 244 __le32 depth; 245 __le32 array_size; 246 __le32 last_level; 247 __le32 nr_samples; 248 __le32 flags; 249 __le32 padding; 250 }; 251 252 /* VIRTIO_GPU_CMD_CTX_CREATE */ 253 struct virtio_gpu_ctx_create { 254 struct virtio_gpu_ctrl_hdr hdr; 255 __le32 nlen; 256 __le32 padding; 257 char debug_name[64]; 258 }; 259 260 /* VIRTIO_GPU_CMD_CTX_DESTROY */ 261 struct virtio_gpu_ctx_destroy { 262 struct virtio_gpu_ctrl_hdr hdr; 263 }; 264 265 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */ 266 struct virtio_gpu_ctx_resource { 267 struct virtio_gpu_ctrl_hdr hdr; 268 __le32 resource_id; 269 __le32 padding; 270 }; 271 272 /* VIRTIO_GPU_CMD_SUBMIT_3D */ 273 struct virtio_gpu_cmd_submit { 274 struct virtio_gpu_ctrl_hdr hdr; 275 __le32 size; 276 __le32 padding; 277 }; 278 279 #define VIRTIO_GPU_CAPSET_VIRGL 1 280 #define VIRTIO_GPU_CAPSET_VIRGL2 2 281 282 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */ 283 struct virtio_gpu_get_capset_info { 284 struct virtio_gpu_ctrl_hdr hdr; 285 __le32 capset_index; 286 __le32 padding; 287 }; 288 289 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */ 290 struct virtio_gpu_resp_capset_info { 291 struct virtio_gpu_ctrl_hdr hdr; 292 __le32 capset_id; 293 __le32 capset_max_version; 294 __le32 capset_max_size; 295 __le32 padding; 296 }; 297 298 /* VIRTIO_GPU_CMD_GET_CAPSET */ 299 struct virtio_gpu_get_capset { 300 struct virtio_gpu_ctrl_hdr hdr; 301 __le32 capset_id; 302 __le32 capset_version; 303 }; 304 305 /* VIRTIO_GPU_RESP_OK_CAPSET */ 306 struct virtio_gpu_resp_capset { 307 struct virtio_gpu_ctrl_hdr hdr; 308 __u8 capset_data[]; 309 }; 310 311 /* VIRTIO_GPU_CMD_GET_EDID */ 312 struct virtio_gpu_cmd_get_edid { 313 struct virtio_gpu_ctrl_hdr hdr; 314 __le32 scanout; 315 __le32 padding; 316 }; 317 318 /* VIRTIO_GPU_RESP_OK_EDID */ 319 struct virtio_gpu_resp_edid { 320 struct virtio_gpu_ctrl_hdr hdr; 321 __le32 size; 322 __le32 padding; 323 __u8 edid[1024]; 324 }; 325 326 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 327 328 struct virtio_gpu_config { 329 __le32 events_read; 330 __le32 events_clear; 331 __le32 num_scanouts; 332 __le32 num_capsets; 333 }; 334 335 /* simple formats for fbcon/X use */ 336 enum virtio_gpu_formats { 337 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 338 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 339 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 340 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 341 342 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 343 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 344 345 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 346 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 347 }; 348 349 /* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */ 350 struct virtio_gpu_resource_assign_uuid { 351 struct virtio_gpu_ctrl_hdr hdr; 352 __le32 resource_id; 353 __le32 padding; 354 }; 355 356 /* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */ 357 struct virtio_gpu_resp_resource_uuid { 358 struct virtio_gpu_ctrl_hdr hdr; 359 __u8 uuid[16]; 360 }; 361 362 #endif 363
