1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SOC_MEDIATEK_INFRACFG_H
3 #define __SOC_MEDIATEK_INFRACFG_H
4 
5 #define MT8173_TOP_AXI_PROT_EN_MCI_M2		BIT(0)
6 #define MT8173_TOP_AXI_PROT_EN_MM_M0		BIT(1)
7 #define MT8173_TOP_AXI_PROT_EN_MM_M1		BIT(2)
8 #define MT8173_TOP_AXI_PROT_EN_MMAPB_S		BIT(6)
9 #define MT8173_TOP_AXI_PROT_EN_L2C_M2		BIT(9)
10 #define MT8173_TOP_AXI_PROT_EN_L2SS_SMI		BIT(11)
11 #define MT8173_TOP_AXI_PROT_EN_L2SS_ADD		BIT(12)
12 #define MT8173_TOP_AXI_PROT_EN_CCI_M2		BIT(13)
13 #define MT8173_TOP_AXI_PROT_EN_MFG_S		BIT(14)
14 #define MT8173_TOP_AXI_PROT_EN_PERI_M0		BIT(15)
15 #define MT8173_TOP_AXI_PROT_EN_PERI_M1		BIT(16)
16 #define MT8173_TOP_AXI_PROT_EN_DEBUGSYS		BIT(17)
17 #define MT8173_TOP_AXI_PROT_EN_CQ_DMA		BIT(18)
18 #define MT8173_TOP_AXI_PROT_EN_GCPU		BIT(19)
19 #define MT8173_TOP_AXI_PROT_EN_IOMMU		BIT(20)
20 #define MT8173_TOP_AXI_PROT_EN_MFG_M0		BIT(21)
21 #define MT8173_TOP_AXI_PROT_EN_MFG_M1		BIT(22)
22 #define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT	BIT(23)
23 
24 #define MT2701_TOP_AXI_PROT_EN_MM_M0		BIT(1)
25 #define MT2701_TOP_AXI_PROT_EN_CONN_M		BIT(2)
26 #define MT2701_TOP_AXI_PROT_EN_CONN_S		BIT(8)
27 
28 #define MT7622_TOP_AXI_PROT_EN_ETHSYS		(BIT(3) | BIT(17))
29 #define MT7622_TOP_AXI_PROT_EN_HIF0		(BIT(24) | BIT(25))
30 #define MT7622_TOP_AXI_PROT_EN_HIF1		(BIT(26) | BIT(27) | \
31 						 BIT(28))
32 #define MT7622_TOP_AXI_PROT_EN_WB		(BIT(2) | BIT(6) | \
33 						 BIT(7) | BIT(8))
34 
35 #define REG_INFRA_MISC				0xf00
36 #define F_DDR_4GB_SUPPORT_EN			BIT(13)
37 
38 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
39 		bool reg_update);
40 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
41 		bool reg_update);
42 #endif /* __SOC_MEDIATEK_INFRACFG_H */
43