1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <joerg.roedel@amd.com>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #ifndef _ASM_X86_AMD_IOMMU_H
9 #define _ASM_X86_AMD_IOMMU_H
10
11 #include <linux/types.h>
12
13 /*
14 * This is mainly used to communicate information back-and-forth
15 * between SVM and IOMMU for setting up and tearing down posted
16 * interrupt
17 */
18 struct amd_iommu_pi_data {
19 u32 ga_tag;
20 u32 prev_ga_tag;
21 u64 base;
22 bool is_guest_mode;
23 struct vcpu_data *vcpu_data;
24 void *ir_data;
25 };
26
27 #ifdef CONFIG_AMD_IOMMU
28
29 struct task_struct;
30 struct pci_dev;
31
32 extern int amd_iommu_detect(void);
33 extern int amd_iommu_init_hardware(void);
34
35 /**
36 * amd_iommu_enable_device_erratum() - Enable erratum workaround for device
37 * in the IOMMUv2 driver
38 * @pdev: The PCI device the workaround is necessary for
39 * @erratum: The erratum workaround to enable
40 *
41 * The function needs to be called before amd_iommu_init_device().
42 * Possible values for the erratum number are for now:
43 * - AMD_PRI_DEV_ERRATUM_ENABLE_RESET - Reset PRI capability when PRI
44 * is enabled
45 * - AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE - Limit number of outstanding PRI
46 * requests to one
47 */
48 #define AMD_PRI_DEV_ERRATUM_ENABLE_RESET 0
49 #define AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE 1
50
51 extern void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum);
52
53 /**
54 * amd_iommu_init_device() - Init device for use with IOMMUv2 driver
55 * @pdev: The PCI device to initialize
56 * @pasids: Number of PASIDs to support for this device
57 *
58 * This function does all setup for the device pdev so that it can be
59 * used with IOMMUv2.
60 * Returns 0 on success or negative value on error.
61 */
62 extern int amd_iommu_init_device(struct pci_dev *pdev, int pasids);
63
64 /**
65 * amd_iommu_free_device() - Free all IOMMUv2 related device resources
66 * and disable IOMMUv2 usage for this device
67 * @pdev: The PCI device to disable IOMMUv2 usage for'
68 */
69 extern void amd_iommu_free_device(struct pci_dev *pdev);
70
71 /**
72 * amd_iommu_bind_pasid() - Bind a given task to a PASID on a device
73 * @pdev: The PCI device to bind the task to
74 * @pasid: The PASID on the device the task should be bound to
75 * @task: the task to bind
76 *
77 * The function returns 0 on success or a negative value on error.
78 */
79 extern int amd_iommu_bind_pasid(struct pci_dev *pdev, u32 pasid,
80 struct task_struct *task);
81
82 /**
83 * amd_iommu_unbind_pasid() - Unbind a PASID from its task on
84 * a device
85 * @pdev: The device of the PASID
86 * @pasid: The PASID to unbind
87 *
88 * When this function returns the device is no longer using the PASID
89 * and the PASID is no longer bound to its task.
90 */
91 extern void amd_iommu_unbind_pasid(struct pci_dev *pdev, u32 pasid);
92
93 /**
94 * amd_iommu_set_invalid_ppr_cb() - Register a call-back for failed
95 * PRI requests
96 * @pdev: The PCI device the call-back should be registered for
97 * @cb: The call-back function
98 *
99 * The IOMMUv2 driver invokes this call-back when it is unable to
100 * successfully handle a PRI request. The device driver can then decide
101 * which PRI response the device should see. Possible return values for
102 * the call-back are:
103 *
104 * - AMD_IOMMU_INV_PRI_RSP_SUCCESS - Send SUCCESS back to the device
105 * - AMD_IOMMU_INV_PRI_RSP_INVALID - Send INVALID back to the device
106 * - AMD_IOMMU_INV_PRI_RSP_FAIL - Send Failure back to the device,
107 * the device is required to disable
108 * PRI when it receives this response
109 *
110 * The function returns 0 on success or negative value on error.
111 */
112 #define AMD_IOMMU_INV_PRI_RSP_SUCCESS 0
113 #define AMD_IOMMU_INV_PRI_RSP_INVALID 1
114 #define AMD_IOMMU_INV_PRI_RSP_FAIL 2
115
116 typedef int (*amd_iommu_invalid_ppr_cb)(struct pci_dev *pdev,
117 u32 pasid,
118 unsigned long address,
119 u16);
120
121 extern int amd_iommu_set_invalid_ppr_cb(struct pci_dev *pdev,
122 amd_iommu_invalid_ppr_cb cb);
123
124 #define PPR_FAULT_EXEC (1 << 1)
125 #define PPR_FAULT_READ (1 << 2)
126 #define PPR_FAULT_WRITE (1 << 5)
127 #define PPR_FAULT_USER (1 << 6)
128 #define PPR_FAULT_RSVD (1 << 7)
129 #define PPR_FAULT_GN (1 << 8)
130
131 /**
132 * amd_iommu_device_info() - Get information about IOMMUv2 support of a
133 * PCI device
134 * @pdev: PCI device to query information from
135 * @info: A pointer to an amd_iommu_device_info structure which will contain
136 * the information about the PCI device
137 *
138 * Returns 0 on success, negative value on error
139 */
140
141 #define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */
142 #define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */
143 #define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */
144 #define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8 /* Device may request execution
145 on memory pages */
146 #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 /* Device may request
147 super-user privileges */
148
149 struct amd_iommu_device_info {
150 int max_pasids;
151 u32 flags;
152 };
153
154 extern int amd_iommu_device_info(struct pci_dev *pdev,
155 struct amd_iommu_device_info *info);
156
157 /**
158 * amd_iommu_set_invalidate_ctx_cb() - Register a call-back for invalidating
159 * a pasid context. This call-back is
160 * invoked when the IOMMUv2 driver needs to
161 * invalidate a PASID context, for example
162 * because the task that is bound to that
163 * context is about to exit.
164 *
165 * @pdev: The PCI device the call-back should be registered for
166 * @cb: The call-back function
167 */
168
169 typedef void (*amd_iommu_invalidate_ctx)(struct pci_dev *pdev, u32 pasid);
170
171 extern int amd_iommu_set_invalidate_ctx_cb(struct pci_dev *pdev,
172 amd_iommu_invalidate_ctx cb);
173 #else /* CONFIG_AMD_IOMMU */
174
amd_iommu_detect(void)175 static inline int amd_iommu_detect(void) { return -ENODEV; }
176
177 #endif /* CONFIG_AMD_IOMMU */
178
179 #if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)
180
181 /* IOMMU AVIC Function */
182 extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));
183
184 extern int
185 amd_iommu_update_ga(int cpu, bool is_run, void *data);
186
187 extern int amd_iommu_activate_guest_mode(void *data);
188 extern int amd_iommu_deactivate_guest_mode(void *data);
189
190 #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
191
192 static inline int
amd_iommu_register_ga_log_notifier(int (* notifier)(u32))193 amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
194 {
195 return 0;
196 }
197
198 static inline int
amd_iommu_update_ga(int cpu,bool is_run,void * data)199 amd_iommu_update_ga(int cpu, bool is_run, void *data)
200 {
201 return 0;
202 }
203
amd_iommu_activate_guest_mode(void * data)204 static inline int amd_iommu_activate_guest_mode(void *data)
205 {
206 return 0;
207 }
208
amd_iommu_deactivate_guest_mode(void * data)209 static inline int amd_iommu_deactivate_guest_mode(void *data)
210 {
211 return 0;
212 }
213 #endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
214
215 #endif /* _ASM_X86_AMD_IOMMU_H */
216
