1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2003 Digi International (www.digi.com)
4 * Scott H Kilau <Scott_Kilau at digi dot com>
5 *
6 * NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE!
7 *
8 * This is shared code between Digi's CVS archive and the
9 * Linux Kernel sources.
10 * Changing the source just for reformatting needlessly breaks
11 * our CVS diff history.
12 *
13 * Send any bug fixes/changes to: Eng.Linux at digi dot com.
14 * Thank you.
15 *
16 */
17
18 #include <linux/delay.h> /* For udelay */
19 #include <linux/io.h> /* For read[bwl]/write[bwl] */
20 #include <linux/serial.h> /* For struct async_serial */
21 #include <linux/serial_reg.h> /* For the various UART offsets */
22 #include <linux/pci.h>
23 #include <linux/tty.h>
24
25 #include "jsm.h" /* Driver main header file */
26
27 static struct {
28 unsigned int rate;
29 unsigned int cflag;
30 } baud_rates[] = {
31 { 921600, B921600 },
32 { 460800, B460800 },
33 { 230400, B230400 },
34 { 115200, B115200 },
35 { 57600, B57600 },
36 { 38400, B38400 },
37 { 19200, B19200 },
38 { 9600, B9600 },
39 { 4800, B4800 },
40 { 2400, B2400 },
41 { 1200, B1200 },
42 { 600, B600 },
43 { 300, B300 },
44 { 200, B200 },
45 { 150, B150 },
46 { 134, B134 },
47 { 110, B110 },
48 { 75, B75 },
49 { 50, B50 },
50 };
51
cls_set_cts_flow_control(struct jsm_channel * ch)52 static void cls_set_cts_flow_control(struct jsm_channel *ch)
53 {
54 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
55 u8 ier = readb(&ch->ch_cls_uart->ier);
56 u8 isr_fcr = 0;
57
58 /*
59 * The Enhanced Register Set may only be accessed when
60 * the Line Control Register is set to 0xBFh.
61 */
62 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
63
64 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
65
66 /* Turn on CTS flow control, turn off IXON flow control */
67 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_CTSDSR);
68 isr_fcr &= ~(UART_EXAR654_EFR_IXON);
69
70 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
71
72 /* Write old LCR value back out, which turns enhanced access off */
73 writeb(lcrb, &ch->ch_cls_uart->lcr);
74
75 /*
76 * Enable interrupts for CTS flow, turn off interrupts for
77 * received XOFF chars
78 */
79 ier |= (UART_EXAR654_IER_CTSDSR);
80 ier &= ~(UART_EXAR654_IER_XOFF);
81 writeb(ier, &ch->ch_cls_uart->ier);
82
83 /* Set the usual FIFO values */
84 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
85
86 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
87 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
88 &ch->ch_cls_uart->isr_fcr);
89
90 ch->ch_t_tlevel = 16;
91 }
92
cls_set_ixon_flow_control(struct jsm_channel * ch)93 static void cls_set_ixon_flow_control(struct jsm_channel *ch)
94 {
95 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
96 u8 ier = readb(&ch->ch_cls_uart->ier);
97 u8 isr_fcr = 0;
98
99 /*
100 * The Enhanced Register Set may only be accessed when
101 * the Line Control Register is set to 0xBFh.
102 */
103 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
104
105 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
106
107 /* Turn on IXON flow control, turn off CTS flow control */
108 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXON);
109 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR);
110
111 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
112
113 /* Now set our current start/stop chars while in enhanced mode */
114 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
115 writeb(0, &ch->ch_cls_uart->lsr);
116 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
117 writeb(0, &ch->ch_cls_uart->spr);
118
119 /* Write old LCR value back out, which turns enhanced access off */
120 writeb(lcrb, &ch->ch_cls_uart->lcr);
121
122 /*
123 * Disable interrupts for CTS flow, turn on interrupts for
124 * received XOFF chars
125 */
126 ier &= ~(UART_EXAR654_IER_CTSDSR);
127 ier |= (UART_EXAR654_IER_XOFF);
128 writeb(ier, &ch->ch_cls_uart->ier);
129
130 /* Set the usual FIFO values */
131 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
132
133 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
134 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
135 &ch->ch_cls_uart->isr_fcr);
136 }
137
cls_set_no_output_flow_control(struct jsm_channel * ch)138 static void cls_set_no_output_flow_control(struct jsm_channel *ch)
139 {
140 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
141 u8 ier = readb(&ch->ch_cls_uart->ier);
142 u8 isr_fcr = 0;
143
144 /*
145 * The Enhanced Register Set may only be accessed when
146 * the Line Control Register is set to 0xBFh.
147 */
148 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
149
150 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
151
152 /* Turn off IXON flow control, turn off CTS flow control */
153 isr_fcr |= (UART_EXAR654_EFR_ECB);
154 isr_fcr &= ~(UART_EXAR654_EFR_CTSDSR | UART_EXAR654_EFR_IXON);
155
156 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
157
158 /* Write old LCR value back out, which turns enhanced access off */
159 writeb(lcrb, &ch->ch_cls_uart->lcr);
160
161 /*
162 * Disable interrupts for CTS flow, turn off interrupts for
163 * received XOFF chars
164 */
165 ier &= ~(UART_EXAR654_IER_CTSDSR);
166 ier &= ~(UART_EXAR654_IER_XOFF);
167 writeb(ier, &ch->ch_cls_uart->ier);
168
169 /* Set the usual FIFO values */
170 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
171
172 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
173 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
174 &ch->ch_cls_uart->isr_fcr);
175
176 ch->ch_r_watermark = 0;
177 ch->ch_t_tlevel = 16;
178 ch->ch_r_tlevel = 16;
179 }
180
cls_set_rts_flow_control(struct jsm_channel * ch)181 static void cls_set_rts_flow_control(struct jsm_channel *ch)
182 {
183 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
184 u8 ier = readb(&ch->ch_cls_uart->ier);
185 u8 isr_fcr = 0;
186
187 /*
188 * The Enhanced Register Set may only be accessed when
189 * the Line Control Register is set to 0xBFh.
190 */
191 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
192
193 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
194
195 /* Turn on RTS flow control, turn off IXOFF flow control */
196 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_RTSDTR);
197 isr_fcr &= ~(UART_EXAR654_EFR_IXOFF);
198
199 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
200
201 /* Write old LCR value back out, which turns enhanced access off */
202 writeb(lcrb, &ch->ch_cls_uart->lcr);
203
204 /* Enable interrupts for RTS flow */
205 ier |= (UART_EXAR654_IER_RTSDTR);
206 writeb(ier, &ch->ch_cls_uart->ier);
207
208 /* Set the usual FIFO values */
209 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
210
211 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_56 |
212 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
213 &ch->ch_cls_uart->isr_fcr);
214
215 ch->ch_r_watermark = 4;
216 ch->ch_r_tlevel = 8;
217 }
218
cls_set_ixoff_flow_control(struct jsm_channel * ch)219 static void cls_set_ixoff_flow_control(struct jsm_channel *ch)
220 {
221 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
222 u8 ier = readb(&ch->ch_cls_uart->ier);
223 u8 isr_fcr = 0;
224
225 /*
226 * The Enhanced Register Set may only be accessed when
227 * the Line Control Register is set to 0xBFh.
228 */
229 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
230
231 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
232
233 /* Turn on IXOFF flow control, turn off RTS flow control */
234 isr_fcr |= (UART_EXAR654_EFR_ECB | UART_EXAR654_EFR_IXOFF);
235 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR);
236
237 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
238
239 /* Now set our current start/stop chars while in enhanced mode */
240 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr);
241 writeb(0, &ch->ch_cls_uart->lsr);
242 writeb(ch->ch_stopc, &ch->ch_cls_uart->msr);
243 writeb(0, &ch->ch_cls_uart->spr);
244
245 /* Write old LCR value back out, which turns enhanced access off */
246 writeb(lcrb, &ch->ch_cls_uart->lcr);
247
248 /* Disable interrupts for RTS flow */
249 ier &= ~(UART_EXAR654_IER_RTSDTR);
250 writeb(ier, &ch->ch_cls_uart->ier);
251
252 /* Set the usual FIFO values */
253 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
254
255 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
256 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
257 &ch->ch_cls_uart->isr_fcr);
258 }
259
cls_set_no_input_flow_control(struct jsm_channel * ch)260 static void cls_set_no_input_flow_control(struct jsm_channel *ch)
261 {
262 u8 lcrb = readb(&ch->ch_cls_uart->lcr);
263 u8 ier = readb(&ch->ch_cls_uart->ier);
264 u8 isr_fcr = 0;
265
266 /*
267 * The Enhanced Register Set may only be accessed when
268 * the Line Control Register is set to 0xBFh.
269 */
270 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
271
272 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
273
274 /* Turn off IXOFF flow control, turn off RTS flow control */
275 isr_fcr |= (UART_EXAR654_EFR_ECB);
276 isr_fcr &= ~(UART_EXAR654_EFR_RTSDTR | UART_EXAR654_EFR_IXOFF);
277
278 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
279
280 /* Write old LCR value back out, which turns enhanced access off */
281 writeb(lcrb, &ch->ch_cls_uart->lcr);
282
283 /* Disable interrupts for RTS flow */
284 ier &= ~(UART_EXAR654_IER_RTSDTR);
285 writeb(ier, &ch->ch_cls_uart->ier);
286
287 /* Set the usual FIFO values */
288 writeb((UART_FCR_ENABLE_FIFO), &ch->ch_cls_uart->isr_fcr);
289
290 writeb((UART_FCR_ENABLE_FIFO | UART_16654_FCR_RXTRIGGER_16 |
291 UART_16654_FCR_TXTRIGGER_16 | UART_FCR_CLEAR_RCVR),
292 &ch->ch_cls_uart->isr_fcr);
293
294 ch->ch_t_tlevel = 16;
295 ch->ch_r_tlevel = 16;
296 }
297
298 /*
299 * cls_clear_break.
300 * Determines whether its time to shut off break condition.
301 *
302 * No locks are assumed to be held when calling this function.
303 * channel lock is held and released in this function.
304 */
cls_clear_break(struct jsm_channel * ch)305 static void cls_clear_break(struct jsm_channel *ch)
306 {
307 unsigned long lock_flags;
308
309 spin_lock_irqsave(&ch->ch_lock, lock_flags);
310
311 /* Turn break off, and unset some variables */
312 if (ch->ch_flags & CH_BREAK_SENDING) {
313 u8 temp = readb(&ch->ch_cls_uart->lcr);
314
315 writeb((temp & ~UART_LCR_SBC), &ch->ch_cls_uart->lcr);
316
317 ch->ch_flags &= ~(CH_BREAK_SENDING);
318 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
319 "clear break Finishing UART_LCR_SBC! finished: %lx\n",
320 jiffies);
321 }
322 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
323 }
324
cls_disable_receiver(struct jsm_channel * ch)325 static void cls_disable_receiver(struct jsm_channel *ch)
326 {
327 u8 tmp = readb(&ch->ch_cls_uart->ier);
328
329 tmp &= ~(UART_IER_RDI);
330 writeb(tmp, &ch->ch_cls_uart->ier);
331 }
332
cls_enable_receiver(struct jsm_channel * ch)333 static void cls_enable_receiver(struct jsm_channel *ch)
334 {
335 u8 tmp = readb(&ch->ch_cls_uart->ier);
336
337 tmp |= (UART_IER_RDI);
338 writeb(tmp, &ch->ch_cls_uart->ier);
339 }
340
341 /* Make the UART raise any of the output signals we want up */
cls_assert_modem_signals(struct jsm_channel * ch)342 static void cls_assert_modem_signals(struct jsm_channel *ch)
343 {
344 if (!ch)
345 return;
346
347 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr);
348 }
349
cls_copy_data_from_uart_to_queue(struct jsm_channel * ch)350 static void cls_copy_data_from_uart_to_queue(struct jsm_channel *ch)
351 {
352 int qleft = 0;
353 u8 linestatus = 0;
354 u8 error_mask = 0;
355 u16 head;
356 u16 tail;
357 unsigned long flags;
358
359 if (!ch)
360 return;
361
362 spin_lock_irqsave(&ch->ch_lock, flags);
363
364 /* cache head and tail of queue */
365 head = ch->ch_r_head & RQUEUEMASK;
366 tail = ch->ch_r_tail & RQUEUEMASK;
367
368 /* Get our cached LSR */
369 linestatus = ch->ch_cached_lsr;
370 ch->ch_cached_lsr = 0;
371
372 /* Store how much space we have left in the queue */
373 qleft = tail - head - 1;
374 if (qleft < 0)
375 qleft += RQUEUEMASK + 1;
376
377 /*
378 * Create a mask to determine whether we should
379 * insert the character (if any) into our queue.
380 */
381 if (ch->ch_c_iflag & IGNBRK)
382 error_mask |= UART_LSR_BI;
383
384 while (1) {
385 /*
386 * Grab the linestatus register, we need to
387 * check to see if there is any data to read
388 */
389 linestatus = readb(&ch->ch_cls_uart->lsr);
390
391 /* Break out if there is no data to fetch */
392 if (!(linestatus & UART_LSR_DR))
393 break;
394
395 /*
396 * Discard character if we are ignoring the error mask
397 * which in this case is the break signal.
398 */
399 if (linestatus & error_mask) {
400 u8 discard;
401
402 linestatus = 0;
403 discard = readb(&ch->ch_cls_uart->txrx);
404 continue;
405 }
406
407 /*
408 * If our queue is full, we have no choice but to drop some
409 * data. The assumption is that HWFLOW or SWFLOW should have
410 * stopped things way way before we got to this point.
411 *
412 * I decided that I wanted to ditch the oldest data first,
413 * I hope thats okay with everyone? Yes? Good.
414 */
415 while (qleft < 1) {
416 tail = (tail + 1) & RQUEUEMASK;
417 ch->ch_r_tail = tail;
418 ch->ch_err_overrun++;
419 qleft++;
420 }
421
422 ch->ch_equeue[head] = linestatus & (UART_LSR_BI | UART_LSR_PE
423 | UART_LSR_FE);
424 ch->ch_rqueue[head] = readb(&ch->ch_cls_uart->txrx);
425
426 qleft--;
427
428 if (ch->ch_equeue[head] & UART_LSR_PE)
429 ch->ch_err_parity++;
430 if (ch->ch_equeue[head] & UART_LSR_BI)
431 ch->ch_err_break++;
432 if (ch->ch_equeue[head] & UART_LSR_FE)
433 ch->ch_err_frame++;
434
435 /* Add to, and flip head if needed */
436 head = (head + 1) & RQUEUEMASK;
437 ch->ch_rxcount++;
438 }
439
440 /*
441 * Write new final heads to channel structure.
442 */
443 ch->ch_r_head = head & RQUEUEMASK;
444 ch->ch_e_head = head & EQUEUEMASK;
445
446 spin_unlock_irqrestore(&ch->ch_lock, flags);
447 }
448
cls_copy_data_from_queue_to_uart(struct jsm_channel * ch)449 static void cls_copy_data_from_queue_to_uart(struct jsm_channel *ch)
450 {
451 u16 tail;
452 int n;
453 int qlen;
454 u32 len_written = 0;
455 struct circ_buf *circ;
456
457 if (!ch)
458 return;
459
460 circ = &ch->uart_port.state->xmit;
461
462 /* No data to write to the UART */
463 if (uart_circ_empty(circ))
464 return;
465
466 /* If port is "stopped", don't send any data to the UART */
467 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
468 return;
469
470 /* We have to do it this way, because of the EXAR TXFIFO count bug. */
471 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
472 return;
473
474 n = 32;
475
476 /* cache tail of queue */
477 tail = circ->tail & (UART_XMIT_SIZE - 1);
478 qlen = uart_circ_chars_pending(circ);
479
480 /* Find minimum of the FIFO space, versus queue length */
481 n = min(n, qlen);
482
483 while (n > 0) {
484 writeb(circ->buf[tail], &ch->ch_cls_uart->txrx);
485 tail = (tail + 1) & (UART_XMIT_SIZE - 1);
486 n--;
487 ch->ch_txcount++;
488 len_written++;
489 }
490
491 /* Update the final tail */
492 circ->tail = tail & (UART_XMIT_SIZE - 1);
493
494 if (len_written > ch->ch_t_tlevel)
495 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
496
497 if (uart_circ_empty(circ))
498 uart_write_wakeup(&ch->uart_port);
499 }
500
cls_parse_modem(struct jsm_channel * ch,u8 signals)501 static void cls_parse_modem(struct jsm_channel *ch, u8 signals)
502 {
503 u8 msignals = signals;
504
505 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
506 "neo_parse_modem: port: %d msignals: %x\n",
507 ch->ch_portnum, msignals);
508
509 /*
510 * Scrub off lower bits.
511 * They signify delta's, which I don't care about
512 * Keep DDCD and DDSR though
513 */
514 msignals &= 0xf8;
515
516 if (msignals & UART_MSR_DDCD)
517 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
518 if (msignals & UART_MSR_DDSR)
519 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_CTS);
520
521 if (msignals & UART_MSR_DCD)
522 ch->ch_mistat |= UART_MSR_DCD;
523 else
524 ch->ch_mistat &= ~UART_MSR_DCD;
525
526 if (msignals & UART_MSR_DSR)
527 ch->ch_mistat |= UART_MSR_DSR;
528 else
529 ch->ch_mistat &= ~UART_MSR_DSR;
530
531 if (msignals & UART_MSR_RI)
532 ch->ch_mistat |= UART_MSR_RI;
533 else
534 ch->ch_mistat &= ~UART_MSR_RI;
535
536 if (msignals & UART_MSR_CTS)
537 ch->ch_mistat |= UART_MSR_CTS;
538 else
539 ch->ch_mistat &= ~UART_MSR_CTS;
540
541 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
542 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
543 ch->ch_portnum,
544 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
545 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
546 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
547 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
548 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
549 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
550 }
551
552 /* Parse the ISR register for the specific port */
cls_parse_isr(struct jsm_board * brd,uint port)553 static inline void cls_parse_isr(struct jsm_board *brd, uint port)
554 {
555 struct jsm_channel *ch;
556 u8 isr = 0;
557 unsigned long flags;
558
559 /*
560 * No need to verify board pointer, it was already
561 * verified in the interrupt routine.
562 */
563
564 if (port >= brd->nasync)
565 return;
566
567 ch = brd->channels[port];
568 if (!ch)
569 return;
570
571 /* Here we try to figure out what caused the interrupt to happen */
572 while (1) {
573 isr = readb(&ch->ch_cls_uart->isr_fcr);
574
575 /* Bail if no pending interrupt on port */
576 if (isr & UART_IIR_NO_INT)
577 break;
578
579 /* Receive Interrupt pending */
580 if (isr & (UART_IIR_RDI | UART_IIR_RDI_TIMEOUT)) {
581 /* Read data from uart -> queue */
582 cls_copy_data_from_uart_to_queue(ch);
583 jsm_check_queue_flow_control(ch);
584 }
585
586 /* Transmit Hold register empty pending */
587 if (isr & UART_IIR_THRI) {
588 /* Transfer data (if any) from Write Queue -> UART. */
589 spin_lock_irqsave(&ch->ch_lock, flags);
590 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
591 spin_unlock_irqrestore(&ch->ch_lock, flags);
592 cls_copy_data_from_queue_to_uart(ch);
593 }
594
595 /*
596 * CTS/RTS change of state:
597 * Don't need to do anything, the cls_parse_modem
598 * below will grab the updated modem signals.
599 */
600
601 /* Parse any modem signal changes */
602 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
603 }
604 }
605
606 /* Channel lock MUST be held before calling this function! */
cls_flush_uart_write(struct jsm_channel * ch)607 static void cls_flush_uart_write(struct jsm_channel *ch)
608 {
609 u8 tmp = 0;
610 u8 i = 0;
611
612 if (!ch)
613 return;
614
615 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT),
616 &ch->ch_cls_uart->isr_fcr);
617
618 for (i = 0; i < 10; i++) {
619 /* Check to see if the UART feels it completely flushed FIFO */
620 tmp = readb(&ch->ch_cls_uart->isr_fcr);
621 if (tmp & UART_FCR_CLEAR_XMIT) {
622 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
623 "Still flushing TX UART... i: %d\n", i);
624 udelay(10);
625 } else
626 break;
627 }
628
629 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
630 }
631
632 /* Channel lock MUST be held before calling this function! */
cls_flush_uart_read(struct jsm_channel * ch)633 static void cls_flush_uart_read(struct jsm_channel *ch)
634 {
635 if (!ch)
636 return;
637
638 /*
639 * For complete POSIX compatibility, we should be purging the
640 * read FIFO in the UART here.
641 *
642 * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
643 * incorrectly flushes write data as well as just basically trashing the
644 * FIFO.
645 *
646 * Presumably, this is a bug in this UART.
647 */
648
649 udelay(10);
650 }
651
cls_send_start_character(struct jsm_channel * ch)652 static void cls_send_start_character(struct jsm_channel *ch)
653 {
654 if (!ch)
655 return;
656
657 if (ch->ch_startc != __DISABLED_CHAR) {
658 ch->ch_xon_sends++;
659 writeb(ch->ch_startc, &ch->ch_cls_uart->txrx);
660 }
661 }
662
cls_send_stop_character(struct jsm_channel * ch)663 static void cls_send_stop_character(struct jsm_channel *ch)
664 {
665 if (!ch)
666 return;
667
668 if (ch->ch_stopc != __DISABLED_CHAR) {
669 ch->ch_xoff_sends++;
670 writeb(ch->ch_stopc, &ch->ch_cls_uart->txrx);
671 }
672 }
673
674 /*
675 * cls_param()
676 * Send any/all changes to the line to the UART.
677 */
cls_param(struct jsm_channel * ch)678 static void cls_param(struct jsm_channel *ch)
679 {
680 u8 lcr = 0;
681 u8 uart_lcr = 0;
682 u8 ier = 0;
683 u32 baud = 9600;
684 int quot = 0;
685 struct jsm_board *bd;
686 int i;
687 unsigned int cflag;
688
689 bd = ch->ch_bd;
690 if (!bd)
691 return;
692
693 /*
694 * If baud rate is zero, flush queues, and set mval to drop DTR.
695 */
696 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
697 ch->ch_r_head = 0;
698 ch->ch_r_tail = 0;
699 ch->ch_e_head = 0;
700 ch->ch_e_tail = 0;
701
702 cls_flush_uart_write(ch);
703 cls_flush_uart_read(ch);
704
705 /* The baudrate is B0 so all modem lines are to be dropped. */
706 ch->ch_flags |= (CH_BAUD0);
707 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
708 cls_assert_modem_signals(ch);
709 return;
710 }
711
712 cflag = C_BAUD(ch->uart_port.state->port.tty);
713 baud = 9600;
714 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
715 if (baud_rates[i].cflag == cflag) {
716 baud = baud_rates[i].rate;
717 break;
718 }
719 }
720
721 if (ch->ch_flags & CH_BAUD0)
722 ch->ch_flags &= ~(CH_BAUD0);
723
724 if (ch->ch_c_cflag & PARENB)
725 lcr |= UART_LCR_PARITY;
726
727 if (!(ch->ch_c_cflag & PARODD))
728 lcr |= UART_LCR_EPAR;
729
730 /*
731 * Not all platforms support mark/space parity,
732 * so this will hide behind an ifdef.
733 */
734 #ifdef CMSPAR
735 if (ch->ch_c_cflag & CMSPAR)
736 lcr |= UART_LCR_SPAR;
737 #endif
738
739 if (ch->ch_c_cflag & CSTOPB)
740 lcr |= UART_LCR_STOP;
741
742 switch (ch->ch_c_cflag & CSIZE) {
743 case CS5:
744 lcr |= UART_LCR_WLEN5;
745 break;
746 case CS6:
747 lcr |= UART_LCR_WLEN6;
748 break;
749 case CS7:
750 lcr |= UART_LCR_WLEN7;
751 break;
752 case CS8:
753 default:
754 lcr |= UART_LCR_WLEN8;
755 break;
756 }
757
758 ier = readb(&ch->ch_cls_uart->ier);
759 uart_lcr = readb(&ch->ch_cls_uart->lcr);
760
761 quot = ch->ch_bd->bd_dividend / baud;
762
763 if (quot != 0) {
764 writeb(UART_LCR_DLAB, &ch->ch_cls_uart->lcr);
765 writeb((quot & 0xff), &ch->ch_cls_uart->txrx);
766 writeb((quot >> 8), &ch->ch_cls_uart->ier);
767 writeb(lcr, &ch->ch_cls_uart->lcr);
768 }
769
770 if (uart_lcr != lcr)
771 writeb(lcr, &ch->ch_cls_uart->lcr);
772
773 if (ch->ch_c_cflag & CREAD)
774 ier |= (UART_IER_RDI | UART_IER_RLSI);
775
776 ier |= (UART_IER_THRI | UART_IER_MSI);
777
778 writeb(ier, &ch->ch_cls_uart->ier);
779
780 if (ch->ch_c_cflag & CRTSCTS)
781 cls_set_cts_flow_control(ch);
782 else if (ch->ch_c_iflag & IXON) {
783 /*
784 * If start/stop is set to disable,
785 * then we should disable flow control.
786 */
787 if ((ch->ch_startc == __DISABLED_CHAR) ||
788 (ch->ch_stopc == __DISABLED_CHAR))
789 cls_set_no_output_flow_control(ch);
790 else
791 cls_set_ixon_flow_control(ch);
792 } else
793 cls_set_no_output_flow_control(ch);
794
795 if (ch->ch_c_cflag & CRTSCTS)
796 cls_set_rts_flow_control(ch);
797 else if (ch->ch_c_iflag & IXOFF) {
798 /*
799 * If start/stop is set to disable,
800 * then we should disable flow control.
801 */
802 if ((ch->ch_startc == __DISABLED_CHAR) ||
803 (ch->ch_stopc == __DISABLED_CHAR))
804 cls_set_no_input_flow_control(ch);
805 else
806 cls_set_ixoff_flow_control(ch);
807 } else
808 cls_set_no_input_flow_control(ch);
809
810 cls_assert_modem_signals(ch);
811
812 /* get current status of the modem signals now */
813 cls_parse_modem(ch, readb(&ch->ch_cls_uart->msr));
814 }
815
816 /*
817 * cls_intr()
818 *
819 * Classic specific interrupt handler.
820 */
cls_intr(int irq,void * voidbrd)821 static irqreturn_t cls_intr(int irq, void *voidbrd)
822 {
823 struct jsm_board *brd = voidbrd;
824 unsigned long lock_flags;
825 unsigned char uart_poll;
826 uint i = 0;
827
828 /* Lock out the slow poller from running on this board. */
829 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
830
831 /*
832 * Check the board's global interrupt offset to see if we
833 * acctually do have an interrupt pending on us.
834 */
835 uart_poll = readb(brd->re_map_membase + UART_CLASSIC_POLL_ADDR_OFFSET);
836
837 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",
838 __FILE__, __LINE__, uart_poll);
839
840 if (!uart_poll) {
841 jsm_dbg(INTR, &brd->pci_dev,
842 "Kernel interrupted to me, but no pending interrupts...\n");
843 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
844 return IRQ_NONE;
845 }
846
847 /* At this point, we have at least SOMETHING to service, dig further. */
848
849 /* Parse each port to find out what caused the interrupt */
850 for (i = 0; i < brd->nasync; i++)
851 cls_parse_isr(brd, i);
852
853 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
854
855 return IRQ_HANDLED;
856 }
857
858 /* Inits UART */
cls_uart_init(struct jsm_channel * ch)859 static void cls_uart_init(struct jsm_channel *ch)
860 {
861 unsigned char lcrb = readb(&ch->ch_cls_uart->lcr);
862 unsigned char isr_fcr = 0;
863
864 writeb(0, &ch->ch_cls_uart->ier);
865
866 /*
867 * The Enhanced Register Set may only be accessed when
868 * the Line Control Register is set to 0xBFh.
869 */
870 writeb(UART_EXAR654_ENHANCED_REGISTER_SET, &ch->ch_cls_uart->lcr);
871
872 isr_fcr = readb(&ch->ch_cls_uart->isr_fcr);
873
874 /* Turn on Enhanced/Extended controls */
875 isr_fcr |= (UART_EXAR654_EFR_ECB);
876
877 writeb(isr_fcr, &ch->ch_cls_uart->isr_fcr);
878
879 /* Write old LCR value back out, which turns enhanced access off */
880 writeb(lcrb, &ch->ch_cls_uart->lcr);
881
882 /* Clear out UART and FIFO */
883 readb(&ch->ch_cls_uart->txrx);
884
885 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT),
886 &ch->ch_cls_uart->isr_fcr);
887 udelay(10);
888
889 ch->ch_flags |= (CH_FIFO_ENABLED | CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
890
891 readb(&ch->ch_cls_uart->lsr);
892 readb(&ch->ch_cls_uart->msr);
893 }
894
895 /*
896 * Turns off UART.
897 */
cls_uart_off(struct jsm_channel * ch)898 static void cls_uart_off(struct jsm_channel *ch)
899 {
900 /* Stop all interrupts from accurring. */
901 writeb(0, &ch->ch_cls_uart->ier);
902 }
903
904 /*
905 * cls_get_uarts_bytes_left.
906 * Returns 0 is nothing left in the FIFO, returns 1 otherwise.
907 *
908 * The channel lock MUST be held by the calling function.
909 */
cls_get_uart_bytes_left(struct jsm_channel * ch)910 static u32 cls_get_uart_bytes_left(struct jsm_channel *ch)
911 {
912 u8 left = 0;
913 u8 lsr = readb(&ch->ch_cls_uart->lsr);
914
915 /* Determine whether the Transmitter is empty or not */
916 if (!(lsr & UART_LSR_TEMT))
917 left = 1;
918 else {
919 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
920 left = 0;
921 }
922
923 return left;
924 }
925
926 /*
927 * cls_send_break.
928 * Starts sending a break thru the UART.
929 *
930 * The channel lock MUST be held by the calling function.
931 */
cls_send_break(struct jsm_channel * ch)932 static void cls_send_break(struct jsm_channel *ch)
933 {
934 /* Tell the UART to start sending the break */
935 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
936 u8 temp = readb(&ch->ch_cls_uart->lcr);
937
938 writeb((temp | UART_LCR_SBC), &ch->ch_cls_uart->lcr);
939 ch->ch_flags |= (CH_BREAK_SENDING);
940 }
941 }
942
943 /*
944 * cls_send_immediate_char.
945 * Sends a specific character as soon as possible to the UART,
946 * jumping over any bytes that might be in the write queue.
947 *
948 * The channel lock MUST be held by the calling function.
949 */
cls_send_immediate_char(struct jsm_channel * ch,unsigned char c)950 static void cls_send_immediate_char(struct jsm_channel *ch, unsigned char c)
951 {
952 writeb(c, &ch->ch_cls_uart->txrx);
953 }
954
955 struct board_ops jsm_cls_ops = {
956 .intr = cls_intr,
957 .uart_init = cls_uart_init,
958 .uart_off = cls_uart_off,
959 .param = cls_param,
960 .assert_modem_signals = cls_assert_modem_signals,
961 .flush_uart_write = cls_flush_uart_write,
962 .flush_uart_read = cls_flush_uart_read,
963 .disable_receiver = cls_disable_receiver,
964 .enable_receiver = cls_enable_receiver,
965 .send_break = cls_send_break,
966 .clear_break = cls_clear_break,
967 .send_start_character = cls_send_start_character,
968 .send_stop_character = cls_send_stop_character,
969 .copy_data_from_queue_to_uart = cls_copy_data_from_queue_to_uart,
970 .get_uart_bytes_left = cls_get_uart_bytes_left,
971 .send_immediate_char = cls_send_immediate_char
972 };
973
974
