1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright 2018 Google LLC.
6 * Tomasz Figa <tfiga@chromium.org>
7 *
8 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
9 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
10 */
11
12 #ifndef HANTRO_H_
13 #define HANTRO_H_
14
15 #include <linux/platform_device.h>
16 #include <linux/videodev2.h>
17 #include <linux/wait.h>
18 #include <linux/clk.h>
19
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-ioctl.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/videobuf2-core.h>
25 #include <media/videobuf2-dma-contig.h>
26
27 #include "hantro_hw.h"
28
29 struct hantro_ctx;
30 struct hantro_codec_ops;
31
32 #define HANTRO_JPEG_ENCODER BIT(0)
33 #define HANTRO_ENCODERS 0x0000ffff
34 #define HANTRO_MPEG2_DECODER BIT(16)
35 #define HANTRO_VP8_DECODER BIT(17)
36 #define HANTRO_H264_DECODER BIT(18)
37 #define HANTRO_DECODERS 0xffff0000
38
39 /**
40 * struct hantro_irq - irq handler and name
41 *
42 * @name: irq name for device tree lookup
43 * @handler: interrupt handler
44 */
45 struct hantro_irq {
46 const char *name;
47 irqreturn_t (*handler)(int irq, void *priv);
48 };
49
50 /**
51 * struct hantro_variant - information about VPU hardware variant
52 *
53 * @enc_offset: Offset from VPU base to encoder registers.
54 * @dec_offset: Offset from VPU base to decoder registers.
55 * @enc_fmts: Encoder formats.
56 * @num_enc_fmts: Number of encoder formats.
57 * @dec_fmts: Decoder formats.
58 * @num_dec_fmts: Number of decoder formats.
59 * @postproc_fmts: Post-processor formats.
60 * @num_postproc_fmts: Number of post-processor formats.
61 * @codec: Supported codecs
62 * @codec_ops: Codec ops.
63 * @init: Initialize hardware.
64 * @runtime_resume: reenable hardware after power gating
65 * @irqs: array of irq names and interrupt handlers
66 * @num_irqs: number of irqs in the array
67 * @clk_names: array of clock names
68 * @num_clocks: number of clocks in the array
69 * @reg_names: array of register range names
70 * @num_regs: number of register range names in the array
71 * @postproc_regs: &struct hantro_postproc_regs pointer
72 */
73 struct hantro_variant {
74 unsigned int enc_offset;
75 unsigned int dec_offset;
76 const struct hantro_fmt *enc_fmts;
77 unsigned int num_enc_fmts;
78 const struct hantro_fmt *dec_fmts;
79 unsigned int num_dec_fmts;
80 const struct hantro_fmt *postproc_fmts;
81 unsigned int num_postproc_fmts;
82 unsigned int codec;
83 const struct hantro_codec_ops *codec_ops;
84 int (*init)(struct hantro_dev *vpu);
85 int (*runtime_resume)(struct hantro_dev *vpu);
86 const struct hantro_irq *irqs;
87 int num_irqs;
88 const char * const *clk_names;
89 int num_clocks;
90 const char * const *reg_names;
91 int num_regs;
92 const struct hantro_postproc_regs *postproc_regs;
93 };
94
95 /**
96 * enum hantro_codec_mode - codec operating mode.
97 * @HANTRO_MODE_NONE: No operating mode. Used for RAW video formats.
98 * @HANTRO_MODE_JPEG_ENC: JPEG encoder.
99 * @HANTRO_MODE_H264_DEC: H264 decoder.
100 * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
101 * @HANTRO_MODE_VP8_DEC: VP8 decoder.
102 */
103 enum hantro_codec_mode {
104 HANTRO_MODE_NONE = -1,
105 HANTRO_MODE_JPEG_ENC,
106 HANTRO_MODE_H264_DEC,
107 HANTRO_MODE_MPEG2_DEC,
108 HANTRO_MODE_VP8_DEC,
109 };
110
111 /*
112 * struct hantro_ctrl - helper type to declare supported controls
113 * @codec: codec id this control belong to (HANTRO_JPEG_ENCODER, etc.)
114 * @cfg: control configuration
115 */
116 struct hantro_ctrl {
117 unsigned int codec;
118 struct v4l2_ctrl_config cfg;
119 };
120
121 /*
122 * struct hantro_func - Hantro VPU functionality
123 *
124 * @id: processing functionality ID (can be
125 * %MEDIA_ENT_F_PROC_VIDEO_ENCODER or
126 * %MEDIA_ENT_F_PROC_VIDEO_DECODER)
127 * @vdev: &struct video_device that exposes the encoder or
128 * decoder functionality
129 * @source_pad: &struct media_pad with the source pad.
130 * @sink: &struct media_entity pointer with the sink entity
131 * @sink_pad: &struct media_pad with the sink pad.
132 * @proc: &struct media_entity pointer with the M2M device itself.
133 * @proc_pads: &struct media_pad with the @proc pads.
134 * @intf_devnode: &struct media_intf devnode pointer with the interface
135 * with controls the M2M device.
136 *
137 * Contains everything needed to attach the video device to the media device.
138 */
139 struct hantro_func {
140 unsigned int id;
141 struct video_device vdev;
142 struct media_pad source_pad;
143 struct media_entity sink;
144 struct media_pad sink_pad;
145 struct media_entity proc;
146 struct media_pad proc_pads[2];
147 struct media_intf_devnode *intf_devnode;
148 };
149
150 static inline struct hantro_func *
hantro_vdev_to_func(struct video_device * vdev)151 hantro_vdev_to_func(struct video_device *vdev)
152 {
153 return container_of(vdev, struct hantro_func, vdev);
154 }
155
156 /**
157 * struct hantro_dev - driver data
158 * @v4l2_dev: V4L2 device to register video devices for.
159 * @m2m_dev: mem2mem device associated to this device.
160 * @mdev: media device associated to this device.
161 * @encoder: encoder functionality.
162 * @decoder: decoder functionality.
163 * @pdev: Pointer to VPU platform device.
164 * @dev: Pointer to device for convenient logging using
165 * dev_ macros.
166 * @clocks: Array of clock handles.
167 * @reg_bases: Mapped addresses of VPU registers.
168 * @enc_base: Mapped address of VPU encoder register for convenience.
169 * @dec_base: Mapped address of VPU decoder register for convenience.
170 * @ctrl_base: Mapped address of VPU control block.
171 * @vpu_mutex: Mutex to synchronize V4L2 calls.
172 * @irqlock: Spinlock to synchronize access to data structures
173 * shared with interrupt handlers.
174 * @variant: Hardware variant-specific parameters.
175 * @watchdog_work: Delayed work for hardware timeout handling.
176 */
177 struct hantro_dev {
178 struct v4l2_device v4l2_dev;
179 struct v4l2_m2m_dev *m2m_dev;
180 struct media_device mdev;
181 struct hantro_func *encoder;
182 struct hantro_func *decoder;
183 struct platform_device *pdev;
184 struct device *dev;
185 struct clk_bulk_data *clocks;
186 void __iomem **reg_bases;
187 void __iomem *enc_base;
188 void __iomem *dec_base;
189 void __iomem *ctrl_base;
190
191 struct mutex vpu_mutex; /* video_device lock */
192 spinlock_t irqlock;
193 const struct hantro_variant *variant;
194 struct delayed_work watchdog_work;
195 };
196
197 /**
198 * struct hantro_ctx - Context (instance) private data.
199 *
200 * @dev: VPU driver data to which the context belongs.
201 * @fh: V4L2 file handler.
202 * @is_encoder: Decoder or encoder context?
203 *
204 * @sequence_cap: Sequence counter for capture queue
205 * @sequence_out: Sequence counter for output queue
206 *
207 * @vpu_src_fmt: Descriptor of active source format.
208 * @src_fmt: V4L2 pixel format of active source format.
209 * @vpu_dst_fmt: Descriptor of active destination format.
210 * @dst_fmt: V4L2 pixel format of active destination format.
211 *
212 * @ctrl_handler: Control handler used to register controls.
213 * @jpeg_quality: User-specified JPEG compression quality.
214 *
215 * @codec_ops: Set of operations related to codec mode.
216 * @postproc: Post-processing context.
217 * @jpeg_enc: JPEG-encoding context.
218 * @mpeg2_dec: MPEG-2-decoding context.
219 * @vp8_dec: VP8-decoding context.
220 */
221 struct hantro_ctx {
222 struct hantro_dev *dev;
223 struct v4l2_fh fh;
224 bool is_encoder;
225
226 u32 sequence_cap;
227 u32 sequence_out;
228
229 const struct hantro_fmt *vpu_src_fmt;
230 struct v4l2_pix_format_mplane src_fmt;
231 const struct hantro_fmt *vpu_dst_fmt;
232 struct v4l2_pix_format_mplane dst_fmt;
233
234 struct v4l2_ctrl_handler ctrl_handler;
235 int jpeg_quality;
236
237 const struct hantro_codec_ops *codec_ops;
238 struct hantro_postproc_ctx postproc;
239
240 /* Specific for particular codec modes. */
241 union {
242 struct hantro_h264_dec_hw_ctx h264_dec;
243 struct hantro_jpeg_enc_hw_ctx jpeg_enc;
244 struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
245 struct hantro_vp8_dec_hw_ctx vp8_dec;
246 };
247 };
248
249 /**
250 * struct hantro_fmt - information about supported video formats.
251 * @name: Human readable name of the format.
252 * @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*.
253 * @codec_mode: Codec mode related to this format. See
254 * enum hantro_codec_mode.
255 * @header_size: Optional header size. Currently used by JPEG encoder.
256 * @max_depth: Maximum depth, for bitstream formats
257 * @enc_fmt: Format identifier for encoder registers.
258 * @frmsize: Supported range of frame sizes (only for bitstream formats).
259 */
260 struct hantro_fmt {
261 char *name;
262 u32 fourcc;
263 enum hantro_codec_mode codec_mode;
264 int header_size;
265 int max_depth;
266 enum hantro_enc_fmt enc_fmt;
267 struct v4l2_frmsize_stepwise frmsize;
268 };
269
270 struct hantro_reg {
271 u32 base;
272 u32 shift;
273 u32 mask;
274 };
275
276 struct hantro_postproc_regs {
277 struct hantro_reg pipeline_en;
278 struct hantro_reg max_burst;
279 struct hantro_reg clk_gate;
280 struct hantro_reg out_swap32;
281 struct hantro_reg out_endian;
282 struct hantro_reg out_luma_base;
283 struct hantro_reg input_width;
284 struct hantro_reg input_height;
285 struct hantro_reg output_width;
286 struct hantro_reg output_height;
287 struct hantro_reg input_fmt;
288 struct hantro_reg output_fmt;
289 struct hantro_reg orig_width;
290 struct hantro_reg display_width;
291 };
292
293 /* Logging helpers */
294
295 /**
296 * debug - Module parameter to control level of debugging messages.
297 *
298 * Level of debugging messages can be controlled by bits of
299 * module parameter called "debug". Meaning of particular
300 * bits is as follows:
301 *
302 * bit 0 - global information: mode, size, init, release
303 * bit 1 - each run start/result information
304 * bit 2 - contents of small controls from userspace
305 * bit 3 - contents of big controls from userspace
306 * bit 4 - detail fmt, ctrl, buffer q/dq information
307 * bit 5 - detail function enter/leave trace information
308 * bit 6 - register write/read information
309 */
310 extern int hantro_debug;
311
312 #define vpu_debug(level, fmt, args...) \
313 do { \
314 if (hantro_debug & BIT(level)) \
315 pr_info("%s:%d: " fmt, \
316 __func__, __LINE__, ##args); \
317 } while (0)
318
319 #define vpu_err(fmt, args...) \
320 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
321
322 /* Structure access helpers. */
fh_to_ctx(struct v4l2_fh * fh)323 static inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh)
324 {
325 return container_of(fh, struct hantro_ctx, fh);
326 }
327
328 /* Register accessors. */
vepu_write_relaxed(struct hantro_dev * vpu,u32 val,u32 reg)329 static inline void vepu_write_relaxed(struct hantro_dev *vpu,
330 u32 val, u32 reg)
331 {
332 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
333 writel_relaxed(val, vpu->enc_base + reg);
334 }
335
vepu_write(struct hantro_dev * vpu,u32 val,u32 reg)336 static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
337 {
338 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
339 writel(val, vpu->enc_base + reg);
340 }
341
vepu_read(struct hantro_dev * vpu,u32 reg)342 static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
343 {
344 u32 val = readl(vpu->enc_base + reg);
345
346 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
347 return val;
348 }
349
vdpu_write_relaxed(struct hantro_dev * vpu,u32 val,u32 reg)350 static inline void vdpu_write_relaxed(struct hantro_dev *vpu,
351 u32 val, u32 reg)
352 {
353 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
354 writel_relaxed(val, vpu->dec_base + reg);
355 }
356
vdpu_write(struct hantro_dev * vpu,u32 val,u32 reg)357 static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
358 {
359 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
360 writel(val, vpu->dec_base + reg);
361 }
362
vdpu_read(struct hantro_dev * vpu,u32 reg)363 static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
364 {
365 u32 val = readl(vpu->dec_base + reg);
366
367 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
368 return val;
369 }
370
vdpu_read_mask(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)371 static inline u32 vdpu_read_mask(struct hantro_dev *vpu,
372 const struct hantro_reg *reg,
373 u32 val)
374 {
375 u32 v;
376
377 v = vdpu_read(vpu, reg->base);
378 v &= ~(reg->mask << reg->shift);
379 v |= ((val & reg->mask) << reg->shift);
380 return v;
381 }
382
hantro_reg_write(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)383 static inline void hantro_reg_write(struct hantro_dev *vpu,
384 const struct hantro_reg *reg,
385 u32 val)
386 {
387 vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
388 }
389
hantro_reg_write_s(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)390 static inline void hantro_reg_write_s(struct hantro_dev *vpu,
391 const struct hantro_reg *reg,
392 u32 val)
393 {
394 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
395 }
396
397 void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
398 dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);
399
400 static inline struct vb2_v4l2_buffer *
hantro_get_src_buf(struct hantro_ctx * ctx)401 hantro_get_src_buf(struct hantro_ctx *ctx)
402 {
403 return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
404 }
405
406 static inline struct vb2_v4l2_buffer *
hantro_get_dst_buf(struct hantro_ctx * ctx)407 hantro_get_dst_buf(struct hantro_ctx *ctx)
408 {
409 return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
410 }
411
412 static inline bool
hantro_needs_postproc(const struct hantro_ctx * ctx,const struct hantro_fmt * fmt)413 hantro_needs_postproc(const struct hantro_ctx *ctx,
414 const struct hantro_fmt *fmt)
415 {
416 return !ctx->is_encoder && fmt->fourcc != V4L2_PIX_FMT_NV12;
417 }
418
419 static inline dma_addr_t
hantro_get_dec_buf_addr(struct hantro_ctx * ctx,struct vb2_buffer * vb)420 hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
421 {
422 if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
423 return ctx->postproc.dec_q[vb->index].dma;
424 return vb2_dma_contig_plane_dma_addr(vb, 0);
425 }
426
427 void hantro_postproc_disable(struct hantro_ctx *ctx);
428 void hantro_postproc_enable(struct hantro_ctx *ctx);
429 void hantro_postproc_free(struct hantro_ctx *ctx);
430 int hantro_postproc_alloc(struct hantro_ctx *ctx);
431
432 #endif /* HANTRO_H_ */
433
