1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Device driver for regulators in HISI PMIC IC
4 *
5 * Copyright (c) 2013 Linaro Ltd.
6 * Copyright (c) 2011 Hisilicon.
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/delay.h>
21 #include <linux/device.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/irq.h>
26 #include <linux/mfd/core.h>
27 #include <linux/mfd/hi6421-spmi-pmic.h>
28 #include <linux/module.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of.h>
33 #include <linux/of_irq.h>
34 #include <linux/platform_device.h>
35 #include <linux/slab.h>
36 #include <linux/spmi.h>
37
38 /* 8-bit register offset in PMIC */
39 #define HISI_MASK_STATE 0xff
40
41 #define HISI_IRQ_ARRAY 2
42 #define HISI_IRQ_NUM (HISI_IRQ_ARRAY * 8)
43
44 #define SOC_PMIC_IRQ_MASK_0_ADDR 0x0202
45 #define SOC_PMIC_IRQ0_ADDR 0x0212
46
47 #define HISI_IRQ_KEY_NUM 0
48 #define HISI_IRQ_KEY_VALUE 0xc0
49 #define HISI_IRQ_KEY_DOWN 7
50 #define HISI_IRQ_KEY_UP 6
51
52 #define HISI_MASK_FIELD 0xFF
53 #define HISI_BITS 8
54
55 /*define the first group interrupt register number*/
56 #define HISI_PMIC_FIRST_GROUP_INT_NUM 2
57
58 static const struct mfd_cell hi6421v600_devs[] = {
59 { .name = "hi6421v600-regulator", },
60 };
61
62 /*
63 * The PMIC register is only 8-bit.
64 * Hisilicon SoC use hardware to map PMIC register into SoC mapping.
65 * At here, we are accessing SoC register with 32-bit.
66 */
hi6421_spmi_pmic_read(struct hi6421_spmi_pmic * pmic,int reg)67 int hi6421_spmi_pmic_read(struct hi6421_spmi_pmic *pmic, int reg)
68 {
69 struct spmi_device *pdev;
70 u8 read_value = 0;
71 u32 ret;
72
73 pdev = to_spmi_device(pmic->dev);
74 if (!pdev) {
75 pr_err("%s: pdev get failed!\n", __func__);
76 return -ENODEV;
77 }
78
79 ret = spmi_ext_register_readl(pdev, reg, &read_value, 1);
80 if (ret) {
81 pr_err("%s: spmi_ext_register_readl failed!\n", __func__);
82 return ret;
83 }
84 return read_value;
85 }
86 EXPORT_SYMBOL(hi6421_spmi_pmic_read);
87
hi6421_spmi_pmic_write(struct hi6421_spmi_pmic * pmic,int reg,u32 val)88 int hi6421_spmi_pmic_write(struct hi6421_spmi_pmic *pmic, int reg, u32 val)
89 {
90 struct spmi_device *pdev;
91 u32 ret;
92
93 pdev = to_spmi_device(pmic->dev);
94 if (!pdev) {
95 pr_err("%s: pdev get failed!\n", __func__);
96 return -ENODEV;
97 }
98
99 ret = spmi_ext_register_writel(pdev, reg, (unsigned char *)&val, 1);
100 if (ret)
101 pr_err("%s: spmi_ext_register_writel failed!\n", __func__);
102
103 return ret;
104 }
105 EXPORT_SYMBOL(hi6421_spmi_pmic_write);
106
hi6421_spmi_pmic_rmw(struct hi6421_spmi_pmic * pmic,int reg,u32 mask,u32 bits)107 int hi6421_spmi_pmic_rmw(struct hi6421_spmi_pmic *pmic, int reg,
108 u32 mask, u32 bits)
109 {
110 unsigned long flags;
111 u32 data;
112 int ret;
113
114 spin_lock_irqsave(&pmic->lock, flags);
115 data = hi6421_spmi_pmic_read(pmic, reg) & ~mask;
116 data |= mask & bits;
117 ret = hi6421_spmi_pmic_write(pmic, reg, data);
118 spin_unlock_irqrestore(&pmic->lock, flags);
119
120 return ret;
121 }
122 EXPORT_SYMBOL(hi6421_spmi_pmic_rmw);
123
hi6421_spmi_irq_handler(int irq,void * data)124 static irqreturn_t hi6421_spmi_irq_handler(int irq, void *data)
125 {
126 struct hi6421_spmi_pmic *pmic = (struct hi6421_spmi_pmic *)data;
127 unsigned long pending;
128 int i, offset;
129
130 for (i = 0; i < HISI_IRQ_ARRAY; i++) {
131 pending = hi6421_spmi_pmic_read(pmic, (i + SOC_PMIC_IRQ0_ADDR));
132 pending &= HISI_MASK_FIELD;
133 if (pending != 0)
134 pr_debug("pending[%d]=0x%lx\n\r", i, pending);
135
136 hi6421_spmi_pmic_write(pmic, (i + SOC_PMIC_IRQ0_ADDR), pending);
137
138 /* solve powerkey order */
139 if ((i == HISI_IRQ_KEY_NUM) &&
140 ((pending & HISI_IRQ_KEY_VALUE) == HISI_IRQ_KEY_VALUE)) {
141 generic_handle_irq(pmic->irqs[HISI_IRQ_KEY_DOWN]);
142 generic_handle_irq(pmic->irqs[HISI_IRQ_KEY_UP]);
143 pending &= (~HISI_IRQ_KEY_VALUE);
144 }
145
146 if (pending) {
147 for_each_set_bit(offset, &pending, HISI_BITS)
148 generic_handle_irq(pmic->irqs[offset + i * HISI_BITS]);
149 }
150 }
151
152 return IRQ_HANDLED;
153 }
154
hi6421_spmi_irq_mask(struct irq_data * d)155 static void hi6421_spmi_irq_mask(struct irq_data *d)
156 {
157 struct hi6421_spmi_pmic *pmic = irq_data_get_irq_chip_data(d);
158 u32 data, offset;
159 unsigned long flags;
160
161 offset = (irqd_to_hwirq(d) >> 3);
162 offset += SOC_PMIC_IRQ_MASK_0_ADDR;
163
164 spin_lock_irqsave(&pmic->lock, flags);
165 data = hi6421_spmi_pmic_read(pmic, offset);
166 data |= (1 << (irqd_to_hwirq(d) & 0x07));
167 hi6421_spmi_pmic_write(pmic, offset, data);
168 spin_unlock_irqrestore(&pmic->lock, flags);
169 }
170
hi6421_spmi_irq_unmask(struct irq_data * d)171 static void hi6421_spmi_irq_unmask(struct irq_data *d)
172 {
173 struct hi6421_spmi_pmic *pmic = irq_data_get_irq_chip_data(d);
174 u32 data, offset;
175 unsigned long flags;
176
177 offset = (irqd_to_hwirq(d) >> 3);
178 offset += SOC_PMIC_IRQ_MASK_0_ADDR;
179
180 spin_lock_irqsave(&pmic->lock, flags);
181 data = hi6421_spmi_pmic_read(pmic, offset);
182 data &= ~(1 << (irqd_to_hwirq(d) & 0x07));
183 hi6421_spmi_pmic_write(pmic, offset, data);
184 spin_unlock_irqrestore(&pmic->lock, flags);
185 }
186
187 static struct irq_chip hi6421_spmi_pmu_irqchip = {
188 .name = "hisi-irq",
189 .irq_mask = hi6421_spmi_irq_mask,
190 .irq_unmask = hi6421_spmi_irq_unmask,
191 .irq_disable = hi6421_spmi_irq_mask,
192 .irq_enable = hi6421_spmi_irq_unmask,
193 };
194
hi6421_spmi_irq_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hw)195 static int hi6421_spmi_irq_map(struct irq_domain *d, unsigned int virq,
196 irq_hw_number_t hw)
197 {
198 struct hi6421_spmi_pmic *pmic = d->host_data;
199
200 irq_set_chip_and_handler_name(virq, &hi6421_spmi_pmu_irqchip,
201 handle_simple_irq, "hisi");
202 irq_set_chip_data(virq, pmic);
203 irq_set_irq_type(virq, IRQ_TYPE_NONE);
204
205 return 0;
206 }
207
208 static const struct irq_domain_ops hi6421_spmi_domain_ops = {
209 .map = hi6421_spmi_irq_map,
210 .xlate = irq_domain_xlate_twocell,
211 };
212
hi6421_spmi_pmic_irq_prc(struct hi6421_spmi_pmic * pmic)213 static void hi6421_spmi_pmic_irq_prc(struct hi6421_spmi_pmic *pmic)
214 {
215 int i, pending;
216
217 for (i = 0 ; i < HISI_IRQ_ARRAY; i++)
218 hi6421_spmi_pmic_write(pmic, SOC_PMIC_IRQ_MASK_0_ADDR + i,
219 HISI_MASK_STATE);
220
221 for (i = 0 ; i < HISI_IRQ_ARRAY; i++) {
222 pending = hi6421_spmi_pmic_read(pmic, SOC_PMIC_IRQ0_ADDR + i);
223
224 pr_debug("PMU IRQ address value:irq[0x%x] = 0x%x\n",
225 SOC_PMIC_IRQ0_ADDR + i, pending);
226 hi6421_spmi_pmic_write(pmic, SOC_PMIC_IRQ0_ADDR + i,
227 HISI_MASK_STATE);
228 }
229 }
230
hi6421_spmi_pmic_probe(struct spmi_device * pdev)231 static int hi6421_spmi_pmic_probe(struct spmi_device *pdev)
232 {
233 struct device *dev = &pdev->dev;
234 struct device_node *np = dev->of_node;
235 struct hi6421_spmi_pmic *pmic;
236 unsigned int virq;
237 int ret, i;
238
239 pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
240 if (!pmic)
241 return -ENOMEM;
242
243 spin_lock_init(&pmic->lock);
244
245 pmic->dev = dev;
246
247 pmic->gpio = of_get_gpio(np, 0);
248 if (pmic->gpio < 0)
249 return pmic->gpio;
250
251 if (!gpio_is_valid(pmic->gpio))
252 return -EINVAL;
253
254 ret = devm_gpio_request_one(dev, pmic->gpio, GPIOF_IN, "pmic");
255 if (ret < 0) {
256 dev_err(dev, "failed to request gpio%d\n", pmic->gpio);
257 return ret;
258 }
259
260 pmic->irq = gpio_to_irq(pmic->gpio);
261
262 hi6421_spmi_pmic_irq_prc(pmic);
263
264 pmic->irqs = devm_kzalloc(dev, HISI_IRQ_NUM * sizeof(int), GFP_KERNEL);
265 if (!pmic->irqs)
266 goto irq_malloc;
267
268 pmic->domain = irq_domain_add_simple(np, HISI_IRQ_NUM, 0,
269 &hi6421_spmi_domain_ops, pmic);
270 if (!pmic->domain) {
271 dev_err(dev, "failed irq domain add simple!\n");
272 ret = -ENODEV;
273 goto irq_malloc;
274 }
275
276 for (i = 0; i < HISI_IRQ_NUM; i++) {
277 virq = irq_create_mapping(pmic->domain, i);
278 if (!virq) {
279 dev_err(dev, "Failed mapping hwirq\n");
280 ret = -ENOSPC;
281 goto irq_malloc;
282 }
283 pmic->irqs[i] = virq;
284 dev_dbg(dev, "%s: pmic->irqs[%d] = %d\n",
285 __func__, i, pmic->irqs[i]);
286 }
287
288 ret = request_threaded_irq(pmic->irq, hi6421_spmi_irq_handler, NULL,
289 IRQF_TRIGGER_LOW | IRQF_SHARED | IRQF_NO_SUSPEND,
290 "pmic", pmic);
291 if (ret < 0) {
292 dev_err(dev, "could not claim pmic IRQ: error %d\n", ret);
293 goto irq_malloc;
294 }
295
296 dev_set_drvdata(&pdev->dev, pmic);
297
298 /*
299 * The logic below will rely that the pmic is already stored at
300 * drvdata.
301 */
302 dev_dbg(&pdev->dev, "SPMI-PMIC: adding children for %pOF\n",
303 pdev->dev.of_node);
304 ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
305 hi6421v600_devs, ARRAY_SIZE(hi6421v600_devs),
306 NULL, 0, NULL);
307 if (!ret)
308 return 0;
309
310 dev_err(dev, "Failed to add child devices: %d\n", ret);
311
312 irq_malloc:
313 free_irq(pmic->irq, pmic);
314
315 return ret;
316 }
317
hi6421_spmi_pmic_remove(struct spmi_device * pdev)318 static void hi6421_spmi_pmic_remove(struct spmi_device *pdev)
319 {
320 struct hi6421_spmi_pmic *pmic = dev_get_drvdata(&pdev->dev);
321
322 free_irq(pmic->irq, pmic);
323 }
324
325 static const struct of_device_id pmic_spmi_id_table[] = {
326 { .compatible = "hisilicon,hi6421-spmi" },
327 { }
328 };
329 MODULE_DEVICE_TABLE(of, pmic_spmi_id_table);
330
331 static struct spmi_driver hi6421_spmi_pmic_driver = {
332 .driver = {
333 .name = "hi6421-spmi-pmic",
334 .of_match_table = pmic_spmi_id_table,
335 },
336 .probe = hi6421_spmi_pmic_probe,
337 .remove = hi6421_spmi_pmic_remove,
338 };
339 module_spmi_driver(hi6421_spmi_pmic_driver);
340
341 MODULE_DESCRIPTION("HiSilicon Hi6421v600 SPMI PMIC driver");
342 MODULE_LICENSE("GPL v2");
343
