1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Marvell
4 *
5 * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
6 *
7 * This file helps PCI controller drivers implement a fake root port
8 * PCI bridge when the HW doesn't provide such a root port PCI
9 * bridge.
10 *
11 * It emulates a PCI bridge by providing a fake PCI configuration
12 * space (and optionally a PCIe capability configuration space) in
13 * memory. By default the read/write operations simply read and update
14 * this fake configuration space in memory. However, PCI controller
15 * drivers can provide through the 'struct pci_sw_bridge_ops'
16 * structure a set of operations to override or complement this
17 * default behavior.
18 */
19
20 #include <linux/pci.h>
21 #include "pci-bridge-emul.h"
22
23 #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF
24 #define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END
25 #define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2)
26
27 /**
28 * struct pci_bridge_reg_behavior - register bits behaviors
29 * @ro: Read-Only bits
30 * @rw: Read-Write bits
31 * @w1c: Write-1-to-Clear bits
32 *
33 * Reads and Writes will be filtered by specified behavior. All other bits not
34 * declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0:
35 * "Reserved register fields must be read only and must return 0 (all 0's for
36 * multi-bit fields) when read".
37 */
38 struct pci_bridge_reg_behavior {
39 /* Read-only bits */
40 u32 ro;
41
42 /* Read-write bits */
43 u32 rw;
44
45 /* Write-1-to-clear bits */
46 u32 w1c;
47 };
48
49 static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
50 [PCI_VENDOR_ID / 4] = { .ro = ~0 },
51 [PCI_COMMAND / 4] = {
52 .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
53 PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
54 PCI_COMMAND_SERR),
55 .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
56 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
57 PCI_COMMAND_FAST_BACK) |
58 (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
59 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
60 .w1c = PCI_STATUS_ERROR_BITS << 16,
61 },
62 [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
63
64 /*
65 * Cache Line Size register: implement as read-only, we do not
66 * pretend implementing "Memory Write and Invalidate"
67 * transactions"
68 *
69 * Latency Timer Register: implemented as read-only, as "A
70 * bridge that is not capable of a burst transfer of more than
71 * two data phases on its primary interface is permitted to
72 * hardwire the Latency Timer to a value of 16 or less"
73 *
74 * Header Type: always read-only
75 *
76 * BIST register: implemented as read-only, as "A bridge that
77 * does not support BIST must implement this register as a
78 * read-only register that returns 0 when read"
79 */
80 [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
81
82 /*
83 * Base Address registers not used must be implemented as
84 * read-only registers that return 0 when read.
85 */
86 [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
87 [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
88
89 [PCI_PRIMARY_BUS / 4] = {
90 /* Primary, secondary and subordinate bus are RW */
91 .rw = GENMASK(24, 0),
92 /* Secondary latency is read-only */
93 .ro = GENMASK(31, 24),
94 },
95
96 [PCI_IO_BASE / 4] = {
97 /* The high four bits of I/O base/limit are RW */
98 .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
99
100 /* The low four bits of I/O base/limit are RO */
101 .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
102 PCI_STATUS_DEVSEL_MASK) << 16) |
103 GENMASK(11, 8) | GENMASK(3, 0)),
104
105 .w1c = PCI_STATUS_ERROR_BITS << 16,
106 },
107
108 [PCI_MEMORY_BASE / 4] = {
109 /* The high 12-bits of mem base/limit are RW */
110 .rw = GENMASK(31, 20) | GENMASK(15, 4),
111
112 /* The low four bits of mem base/limit are RO */
113 .ro = GENMASK(19, 16) | GENMASK(3, 0),
114 },
115
116 [PCI_PREF_MEMORY_BASE / 4] = {
117 /* The high 12-bits of pref mem base/limit are RW */
118 .rw = GENMASK(31, 20) | GENMASK(15, 4),
119
120 /* The low four bits of pref mem base/limit are RO */
121 .ro = GENMASK(19, 16) | GENMASK(3, 0),
122 },
123
124 [PCI_PREF_BASE_UPPER32 / 4] = {
125 .rw = ~0,
126 },
127
128 [PCI_PREF_LIMIT_UPPER32 / 4] = {
129 .rw = ~0,
130 },
131
132 [PCI_IO_BASE_UPPER16 / 4] = {
133 .rw = ~0,
134 },
135
136 [PCI_CAPABILITY_LIST / 4] = {
137 .ro = GENMASK(7, 0),
138 },
139
140 [PCI_ROM_ADDRESS1 / 4] = {
141 .rw = GENMASK(31, 11) | BIT(0),
142 },
143
144 /*
145 * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
146 * are RO, and bridge control (31:16) are a mix of RW, RO,
147 * reserved and W1C bits
148 */
149 [PCI_INTERRUPT_LINE / 4] = {
150 /* Interrupt line is RW */
151 .rw = (GENMASK(7, 0) |
152 ((PCI_BRIDGE_CTL_PARITY |
153 PCI_BRIDGE_CTL_SERR |
154 PCI_BRIDGE_CTL_ISA |
155 PCI_BRIDGE_CTL_VGA |
156 PCI_BRIDGE_CTL_MASTER_ABORT |
157 PCI_BRIDGE_CTL_BUS_RESET |
158 BIT(8) | BIT(9) | BIT(11)) << 16)),
159
160 /* Interrupt pin is RO */
161 .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
162
163 .w1c = BIT(10) << 16,
164 },
165 };
166
167 static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
168 [PCI_CAP_LIST_ID / 4] = {
169 /*
170 * Capability ID, Next Capability Pointer and
171 * Capabilities register are all read-only.
172 */
173 .ro = ~0,
174 },
175
176 [PCI_EXP_DEVCAP / 4] = {
177 .ro = ~0,
178 },
179
180 [PCI_EXP_DEVCTL / 4] = {
181 /* Device control register is RW */
182 .rw = GENMASK(15, 0),
183
184 /*
185 * Device status register has bits 6 and [3:0] W1C, [5:4] RO,
186 * the rest is reserved
187 */
188 .w1c = (BIT(6) | GENMASK(3, 0)) << 16,
189 .ro = GENMASK(5, 4) << 16,
190 },
191
192 [PCI_EXP_LNKCAP / 4] = {
193 /* All bits are RO, except bit 23 which is reserved */
194 .ro = lower_32_bits(~BIT(23)),
195 },
196
197 [PCI_EXP_LNKCTL / 4] = {
198 /*
199 * Link control has bits [15:14], [11:3] and [1:0] RW, the
200 * rest is reserved.
201 *
202 * Link status has bits [13:0] RO, and bits [15:14]
203 * W1C.
204 */
205 .rw = GENMASK(15, 14) | GENMASK(11, 3) | GENMASK(1, 0),
206 .ro = GENMASK(13, 0) << 16,
207 .w1c = GENMASK(15, 14) << 16,
208 },
209
210 [PCI_EXP_SLTCAP / 4] = {
211 .ro = ~0,
212 },
213
214 [PCI_EXP_SLTCTL / 4] = {
215 /*
216 * Slot control has bits [14:0] RW, the rest is
217 * reserved.
218 *
219 * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
220 * rest is reserved.
221 */
222 .rw = GENMASK(14, 0),
223 .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
224 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
225 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
226 .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
227 PCI_EXP_SLTSTA_EIS) << 16,
228 },
229
230 [PCI_EXP_RTCTL / 4] = {
231 /*
232 * Root control has bits [4:0] RW, the rest is
233 * reserved.
234 *
235 * Root capabilities has bit 0 RO, the rest is reserved.
236 */
237 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
238 PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
239 PCI_EXP_RTCTL_CRSSVE),
240 .ro = PCI_EXP_RTCAP_CRSVIS << 16,
241 },
242
243 [PCI_EXP_RTSTA / 4] = {
244 /*
245 * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
246 * is reserved.
247 */
248 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
249 .w1c = PCI_EXP_RTSTA_PME,
250 },
251 };
252
253 /*
254 * Initialize a pci_bridge_emul structure to represent a fake PCI
255 * bridge configuration space. The caller needs to have initialized
256 * the PCI configuration space with whatever values make sense
257 * (typically at least vendor, device, revision), the ->ops pointer,
258 * and optionally ->data and ->has_pcie.
259 */
pci_bridge_emul_init(struct pci_bridge_emul * bridge,unsigned int flags)260 int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
261 unsigned int flags)
262 {
263 bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
264 bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
265 bridge->conf.cache_line_size = 0x10;
266 bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
267 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
268 sizeof(pci_regs_behavior),
269 GFP_KERNEL);
270 if (!bridge->pci_regs_behavior)
271 return -ENOMEM;
272
273 if (bridge->has_pcie) {
274 bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
275 bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
276 /* Set PCIe v2, root port, slot support */
277 bridge->pcie_conf.cap =
278 cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
279 PCI_EXP_FLAGS_SLOT);
280 bridge->pcie_cap_regs_behavior =
281 kmemdup(pcie_cap_regs_behavior,
282 sizeof(pcie_cap_regs_behavior),
283 GFP_KERNEL);
284 if (!bridge->pcie_cap_regs_behavior) {
285 kfree(bridge->pci_regs_behavior);
286 return -ENOMEM;
287 }
288 }
289
290 if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {
291 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
292 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
293 }
294
295 return 0;
296 }
297 EXPORT_SYMBOL_GPL(pci_bridge_emul_init);
298
299 /*
300 * Cleanup a pci_bridge_emul structure that was previously initialized
301 * using pci_bridge_emul_init().
302 */
pci_bridge_emul_cleanup(struct pci_bridge_emul * bridge)303 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
304 {
305 if (bridge->has_pcie)
306 kfree(bridge->pcie_cap_regs_behavior);
307 kfree(bridge->pci_regs_behavior);
308 }
309 EXPORT_SYMBOL_GPL(pci_bridge_emul_cleanup);
310
311 /*
312 * Should be called by the PCI controller driver when reading the PCI
313 * configuration space of the fake bridge. It will call back the
314 * ->ops->read_base or ->ops->read_pcie operations.
315 */
pci_bridge_emul_conf_read(struct pci_bridge_emul * bridge,int where,int size,u32 * value)316 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
317 int size, u32 *value)
318 {
319 int ret;
320 int reg = where & ~3;
321 pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
322 int reg, u32 *value);
323 __le32 *cfgspace;
324 const struct pci_bridge_reg_behavior *behavior;
325
326 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
327 *value = 0;
328 return PCIBIOS_SUCCESSFUL;
329 }
330
331 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
332 *value = 0;
333 return PCIBIOS_SUCCESSFUL;
334 }
335
336 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
337 reg -= PCI_CAP_PCIE_START;
338 read_op = bridge->ops->read_pcie;
339 cfgspace = (__le32 *) &bridge->pcie_conf;
340 behavior = bridge->pcie_cap_regs_behavior;
341 } else {
342 read_op = bridge->ops->read_base;
343 cfgspace = (__le32 *) &bridge->conf;
344 behavior = bridge->pci_regs_behavior;
345 }
346
347 if (read_op)
348 ret = read_op(bridge, reg, value);
349 else
350 ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
351
352 if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
353 *value = le32_to_cpu(cfgspace[reg / 4]);
354
355 /*
356 * Make sure we never return any reserved bit with a value
357 * different from 0.
358 */
359 *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
360 behavior[reg / 4].w1c;
361
362 if (size == 1)
363 *value = (*value >> (8 * (where & 3))) & 0xff;
364 else if (size == 2)
365 *value = (*value >> (8 * (where & 3))) & 0xffff;
366 else if (size != 4)
367 return PCIBIOS_BAD_REGISTER_NUMBER;
368
369 return PCIBIOS_SUCCESSFUL;
370 }
371 EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_read);
372
373 /*
374 * Should be called by the PCI controller driver when writing the PCI
375 * configuration space of the fake bridge. It will call back the
376 * ->ops->write_base or ->ops->write_pcie operations.
377 */
pci_bridge_emul_conf_write(struct pci_bridge_emul * bridge,int where,int size,u32 value)378 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
379 int size, u32 value)
380 {
381 int reg = where & ~3;
382 int mask, ret, old, new, shift;
383 void (*write_op)(struct pci_bridge_emul *bridge, int reg,
384 u32 old, u32 new, u32 mask);
385 __le32 *cfgspace;
386 const struct pci_bridge_reg_behavior *behavior;
387
388 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
389 return PCIBIOS_SUCCESSFUL;
390
391 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
392 return PCIBIOS_SUCCESSFUL;
393
394 shift = (where & 0x3) * 8;
395
396 if (size == 4)
397 mask = 0xffffffff;
398 else if (size == 2)
399 mask = 0xffff << shift;
400 else if (size == 1)
401 mask = 0xff << shift;
402 else
403 return PCIBIOS_BAD_REGISTER_NUMBER;
404
405 ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
406 if (ret != PCIBIOS_SUCCESSFUL)
407 return ret;
408
409 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
410 reg -= PCI_CAP_PCIE_START;
411 write_op = bridge->ops->write_pcie;
412 cfgspace = (__le32 *) &bridge->pcie_conf;
413 behavior = bridge->pcie_cap_regs_behavior;
414 } else {
415 write_op = bridge->ops->write_base;
416 cfgspace = (__le32 *) &bridge->conf;
417 behavior = bridge->pci_regs_behavior;
418 }
419
420 /* Keep all bits, except the RW bits */
421 new = old & (~mask | ~behavior[reg / 4].rw);
422
423 /* Update the value of the RW bits */
424 new |= (value << shift) & (behavior[reg / 4].rw & mask);
425
426 /* Clear the W1C bits */
427 new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
428
429 cfgspace[reg / 4] = cpu_to_le32(new);
430
431 if (write_op)
432 write_op(bridge, reg, old, new, mask);
433
434 return PCIBIOS_SUCCESSFUL;
435 }
436 EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_write);
437
