1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2017, 2020 The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/device.h>
7 #include <linux/module.h>
8 #include <linux/of.h>
9 #include <linux/of_platform.h>
10 #include <linux/nvmem-provider.h>
11 #include <linux/regmap.h>
12
13 #define SDAM_MEM_START 0x40
14 #define REGISTER_MAP_ID 0x40
15 #define REGISTER_MAP_VERSION 0x41
16 #define SDAM_SIZE 0x44
17 #define SDAM_PBS_TRIG_SET 0xE5
18 #define SDAM_PBS_TRIG_CLR 0xE6
19
20 struct sdam_chip {
21 struct platform_device *pdev;
22 struct regmap *regmap;
23 struct nvmem_config sdam_config;
24 unsigned int base;
25 unsigned int size;
26 };
27
28 /* read only register offsets */
29 static const u8 sdam_ro_map[] = {
30 REGISTER_MAP_ID,
31 REGISTER_MAP_VERSION,
32 SDAM_SIZE
33 };
34
sdam_is_valid(struct sdam_chip * sdam,unsigned int offset,size_t len)35 static bool sdam_is_valid(struct sdam_chip *sdam, unsigned int offset,
36 size_t len)
37 {
38 unsigned int sdam_mem_end = SDAM_MEM_START + sdam->size - 1;
39
40 if (!len)
41 return false;
42
43 if (offset >= SDAM_MEM_START && offset <= sdam_mem_end
44 && (offset + len - 1) <= sdam_mem_end)
45 return true;
46 else if ((offset == SDAM_PBS_TRIG_SET || offset == SDAM_PBS_TRIG_CLR)
47 && (len == 1))
48 return true;
49
50 return false;
51 }
52
sdam_is_ro(unsigned int offset,size_t len)53 static bool sdam_is_ro(unsigned int offset, size_t len)
54 {
55 int i;
56
57 for (i = 0; i < ARRAY_SIZE(sdam_ro_map); i++)
58 if (offset <= sdam_ro_map[i] && (offset + len) > sdam_ro_map[i])
59 return true;
60
61 return false;
62 }
63
sdam_read(void * priv,unsigned int offset,void * val,size_t bytes)64 static int sdam_read(void *priv, unsigned int offset, void *val,
65 size_t bytes)
66 {
67 struct sdam_chip *sdam = priv;
68 struct device *dev = &sdam->pdev->dev;
69 int rc;
70
71 if (!sdam_is_valid(sdam, offset, bytes)) {
72 dev_err(dev, "Invalid SDAM offset %#x len=%zd\n",
73 offset, bytes);
74 return -EINVAL;
75 }
76
77 rc = regmap_bulk_read(sdam->regmap, sdam->base + offset, val, bytes);
78 if (rc < 0)
79 dev_err(dev, "Failed to read SDAM offset %#x len=%zd, rc=%d\n",
80 offset, bytes, rc);
81
82 return rc;
83 }
84
sdam_write(void * priv,unsigned int offset,void * val,size_t bytes)85 static int sdam_write(void *priv, unsigned int offset, void *val,
86 size_t bytes)
87 {
88 struct sdam_chip *sdam = priv;
89 struct device *dev = &sdam->pdev->dev;
90 int rc;
91
92 if (!sdam_is_valid(sdam, offset, bytes)) {
93 dev_err(dev, "Invalid SDAM offset %#x len=%zd\n",
94 offset, bytes);
95 return -EINVAL;
96 }
97
98 if (sdam_is_ro(offset, bytes)) {
99 dev_err(dev, "Invalid write offset %#x len=%zd\n",
100 offset, bytes);
101 return -EINVAL;
102 }
103
104 rc = regmap_bulk_write(sdam->regmap, sdam->base + offset, val, bytes);
105 if (rc < 0)
106 dev_err(dev, "Failed to write SDAM offset %#x len=%zd, rc=%d\n",
107 offset, bytes, rc);
108
109 return rc;
110 }
111
sdam_probe(struct platform_device * pdev)112 static int sdam_probe(struct platform_device *pdev)
113 {
114 struct sdam_chip *sdam;
115 struct nvmem_device *nvmem;
116 unsigned int val;
117 int rc;
118
119 sdam = devm_kzalloc(&pdev->dev, sizeof(*sdam), GFP_KERNEL);
120 if (!sdam)
121 return -ENOMEM;
122
123 sdam->regmap = dev_get_regmap(pdev->dev.parent, NULL);
124 if (!sdam->regmap) {
125 dev_err(&pdev->dev, "Failed to get regmap handle\n");
126 return -ENXIO;
127 }
128
129 rc = of_property_read_u32(pdev->dev.of_node, "reg", &sdam->base);
130 if (rc < 0) {
131 dev_err(&pdev->dev, "Failed to get SDAM base, rc=%d\n", rc);
132 return -EINVAL;
133 }
134
135 rc = regmap_read(sdam->regmap, sdam->base + SDAM_SIZE, &val);
136 if (rc < 0) {
137 dev_err(&pdev->dev, "Failed to read SDAM_SIZE rc=%d\n", rc);
138 return -EINVAL;
139 }
140 sdam->size = val * 32;
141
142 sdam->sdam_config.dev = &pdev->dev;
143 sdam->sdam_config.name = "spmi_sdam";
144 sdam->sdam_config.id = NVMEM_DEVID_AUTO;
145 sdam->sdam_config.owner = THIS_MODULE,
146 sdam->sdam_config.stride = 1;
147 sdam->sdam_config.word_size = 1;
148 sdam->sdam_config.reg_read = sdam_read;
149 sdam->sdam_config.reg_write = sdam_write;
150 sdam->sdam_config.priv = sdam;
151
152 nvmem = devm_nvmem_register(&pdev->dev, &sdam->sdam_config);
153 if (IS_ERR(nvmem)) {
154 dev_err(&pdev->dev,
155 "Failed to register SDAM nvmem device rc=%ld\n",
156 PTR_ERR(nvmem));
157 return -ENXIO;
158 }
159 dev_dbg(&pdev->dev,
160 "SDAM base=%#x size=%u registered successfully\n",
161 sdam->base, sdam->size);
162
163 return 0;
164 }
165
166 static const struct of_device_id sdam_match_table[] = {
167 { .compatible = "qcom,spmi-sdam" },
168 {},
169 };
170
171 static struct platform_driver sdam_driver = {
172 .driver = {
173 .name = "qcom,spmi-sdam",
174 .of_match_table = sdam_match_table,
175 },
176 .probe = sdam_probe,
177 };
178
sdam_init(void)179 static int __init sdam_init(void)
180 {
181 return platform_driver_register(&sdam_driver);
182 }
183 subsys_initcall(sdam_init);
184
sdam_exit(void)185 static void __exit sdam_exit(void)
186 {
187 return platform_driver_unregister(&sdam_driver);
188 }
189 module_exit(sdam_exit);
190
191 MODULE_DESCRIPTION("QCOM SPMI SDAM driver");
192 MODULE_LICENSE("GPL v2");
193
