1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i.MX6 OCOTP fusebox driver
4 *
5 * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
6 *
7 * Based on the barebox ocotp driver,
8 * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
9 * Orex Computed Radiography
10 *
11 * Write support based on the fsl_otp driver,
12 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
13 */
14
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/nvmem-provider.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/delay.h>
25
26 #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
27 * OTP Bank0 Word0
28 */
29 #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr
30 * of two consecutive OTP words.
31 */
32
33 #define IMX_OCOTP_ADDR_CTRL 0x0000
34 #define IMX_OCOTP_ADDR_CTRL_SET 0x0004
35 #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
36 #define IMX_OCOTP_ADDR_TIMING 0x0010
37 #define IMX_OCOTP_ADDR_DATA0 0x0020
38 #define IMX_OCOTP_ADDR_DATA1 0x0030
39 #define IMX_OCOTP_ADDR_DATA2 0x0040
40 #define IMX_OCOTP_ADDR_DATA3 0x0050
41
42 #define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF
43 #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100
44 #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200
45 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
46
47 #define IMX_OCOTP_BM_CTRL_ADDR_8MP 0x000001FF
48 #define IMX_OCOTP_BM_CTRL_BUSY_8MP 0x00000200
49 #define IMX_OCOTP_BM_CTRL_ERROR_8MP 0x00000400
50 #define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP 0x00000800
51
52 #define IMX_OCOTP_BM_CTRL_DEFAULT \
53 { \
54 .bm_addr = IMX_OCOTP_BM_CTRL_ADDR, \
55 .bm_busy = IMX_OCOTP_BM_CTRL_BUSY, \
56 .bm_error = IMX_OCOTP_BM_CTRL_ERROR, \
57 .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\
58 }
59
60 #define IMX_OCOTP_BM_CTRL_8MP \
61 { \
62 .bm_addr = IMX_OCOTP_BM_CTRL_ADDR_8MP, \
63 .bm_busy = IMX_OCOTP_BM_CTRL_BUSY_8MP, \
64 .bm_error = IMX_OCOTP_BM_CTRL_ERROR_8MP, \
65 .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP,\
66 }
67
68 #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */
69 #define TIMING_STROBE_READ_NS 37 /* Min time before read */
70 #define TIMING_RELAX_NS 17
71 #define DEF_FSOURCE 1001 /* > 1000 ns */
72 #define DEF_STROBE_PROG 10000 /* IPG clocks */
73 #define IMX_OCOTP_WR_UNLOCK 0x3E770000
74 #define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA
75
76 static DEFINE_MUTEX(ocotp_mutex);
77
78 struct ocotp_priv {
79 struct device *dev;
80 struct clk *clk;
81 void __iomem *base;
82 const struct ocotp_params *params;
83 struct nvmem_config *config;
84 };
85
86 struct ocotp_ctrl_reg {
87 u32 bm_addr;
88 u32 bm_busy;
89 u32 bm_error;
90 u32 bm_rel_shadows;
91 };
92
93 struct ocotp_params {
94 unsigned int nregs;
95 unsigned int bank_address_words;
96 void (*set_timing)(struct ocotp_priv *priv);
97 struct ocotp_ctrl_reg ctrl;
98 };
99
imx_ocotp_wait_for_busy(struct ocotp_priv * priv,u32 flags)100 static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
101 {
102 int count;
103 u32 c, mask;
104 u32 bm_ctrl_busy, bm_ctrl_error;
105 void __iomem *base = priv->base;
106
107 bm_ctrl_busy = priv->params->ctrl.bm_busy;
108 bm_ctrl_error = priv->params->ctrl.bm_error;
109
110 mask = bm_ctrl_busy | bm_ctrl_error | flags;
111
112 for (count = 10000; count >= 0; count--) {
113 c = readl(base + IMX_OCOTP_ADDR_CTRL);
114 if (!(c & mask))
115 break;
116 cpu_relax();
117 }
118
119 if (count < 0) {
120 /* HW_OCOTP_CTRL[ERROR] will be set under the following
121 * conditions:
122 * - A write is performed to a shadow register during a shadow
123 * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
124 * set. In addition, the contents of the shadow register shall
125 * not be updated.
126 * - A write is performed to a shadow register which has been
127 * locked.
128 * - A read is performed to from a shadow register which has
129 * been read locked.
130 * - A program is performed to a fuse word which has been locked
131 * - A read is performed to from a fuse word which has been read
132 * locked.
133 */
134 if (c & bm_ctrl_error)
135 return -EPERM;
136 return -ETIMEDOUT;
137 }
138
139 return 0;
140 }
141
imx_ocotp_clr_err_if_set(struct ocotp_priv * priv)142 static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv)
143 {
144 u32 c, bm_ctrl_error;
145 void __iomem *base = priv->base;
146
147 bm_ctrl_error = priv->params->ctrl.bm_error;
148
149 c = readl(base + IMX_OCOTP_ADDR_CTRL);
150 if (!(c & bm_ctrl_error))
151 return;
152
153 writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
154 }
155
imx_ocotp_read(void * context,unsigned int offset,void * val,size_t bytes)156 static int imx_ocotp_read(void *context, unsigned int offset,
157 void *val, size_t bytes)
158 {
159 struct ocotp_priv *priv = context;
160 unsigned int count;
161 u32 *buf = val;
162 int i, ret;
163 u32 index;
164
165 index = offset >> 2;
166 count = bytes >> 2;
167
168 if (count > (priv->params->nregs - index))
169 count = priv->params->nregs - index;
170
171 mutex_lock(&ocotp_mutex);
172
173 ret = clk_prepare_enable(priv->clk);
174 if (ret < 0) {
175 mutex_unlock(&ocotp_mutex);
176 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
177 return ret;
178 }
179
180 ret = imx_ocotp_wait_for_busy(priv, 0);
181 if (ret < 0) {
182 dev_err(priv->dev, "timeout during read setup\n");
183 goto read_end;
184 }
185
186 for (i = index; i < (index + count); i++) {
187 *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
188 i * IMX_OCOTP_OFFSET_PER_WORD);
189
190 /* 47.3.1.2
191 * For "read locked" registers 0xBADABADA will be returned and
192 * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
193 * software before any new write, read or reload access can be
194 * issued
195 */
196 if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
197 imx_ocotp_clr_err_if_set(priv);
198 }
199
200 read_end:
201 clk_disable_unprepare(priv->clk);
202 mutex_unlock(&ocotp_mutex);
203 return ret;
204 }
205
imx_ocotp_set_imx6_timing(struct ocotp_priv * priv)206 static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
207 {
208 unsigned long clk_rate;
209 unsigned long strobe_read, relax, strobe_prog;
210 u32 timing;
211
212 /* 47.3.1.3.1
213 * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
214 * fields with timing values to match the current frequency of the
215 * ipg_clk. OTP writes will work at maximum bus frequencies as long
216 * as the HW_OCOTP_TIMING parameters are set correctly.
217 *
218 * Note: there are minimum timings required to ensure an OTP fuse burns
219 * correctly that are independent of the ipg_clk. Those values are not
220 * formally documented anywhere however, working from the minimum
221 * timings given in u-boot we can say:
222 *
223 * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10
224 * microseconds feels about right as representative of a minimum time
225 * to physically burn out a fuse.
226 *
227 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before
228 * performing another read is 37 nanoseconds
229 *
230 * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
231 * timing is not entirely clear the documentation says "This
232 * count value specifies the time to add to all default timing
233 * parameters other than the Tpgm and Trd. It is given in number
234 * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG
235 * and STROBE_READ respectively. What the other timing parameters
236 * are though, is not specified. Experience shows a zero RELAX
237 * value will mess up a re-load of the shadow registers post OTP
238 * burn.
239 */
240 clk_rate = clk_get_rate(priv->clk);
241
242 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1;
243 strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS,
244 1000000000);
245 strobe_read += 2 * (relax + 1) - 1;
246 strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US,
247 1000000);
248 strobe_prog += 2 * (relax + 1) - 1;
249
250 timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
251 timing |= strobe_prog & 0x00000FFF;
252 timing |= (relax << 12) & 0x0000F000;
253 timing |= (strobe_read << 16) & 0x003F0000;
254
255 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
256 }
257
imx_ocotp_set_imx7_timing(struct ocotp_priv * priv)258 static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
259 {
260 unsigned long clk_rate;
261 u64 fsource, strobe_prog;
262 u32 timing;
263
264 /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
265 * 6.4.3.3
266 */
267 clk_rate = clk_get_rate(priv->clk);
268 fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
269 NSEC_PER_SEC) + 1;
270 strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
271 NSEC_PER_SEC) + 1;
272
273 timing = strobe_prog & 0x00000FFF;
274 timing |= (fsource << 12) & 0x000FF000;
275
276 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
277 }
278
imx_ocotp_write(void * context,unsigned int offset,void * val,size_t bytes)279 static int imx_ocotp_write(void *context, unsigned int offset, void *val,
280 size_t bytes)
281 {
282 struct ocotp_priv *priv = context;
283 u32 *buf = val;
284 int ret;
285
286 u32 ctrl;
287 u8 waddr;
288 u8 word = 0;
289
290 /* allow only writing one complete OTP word at a time */
291 if ((bytes != priv->config->word_size) ||
292 (offset % priv->config->word_size))
293 return -EINVAL;
294
295 mutex_lock(&ocotp_mutex);
296
297 ret = clk_prepare_enable(priv->clk);
298 if (ret < 0) {
299 mutex_unlock(&ocotp_mutex);
300 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
301 return ret;
302 }
303
304 /* Setup the write timing values */
305 priv->params->set_timing(priv);
306
307 /* 47.3.1.3.2
308 * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
309 * Overlapped accesses are not supported by the controller. Any pending
310 * write or reload must be completed before a write access can be
311 * requested.
312 */
313 ret = imx_ocotp_wait_for_busy(priv, 0);
314 if (ret < 0) {
315 dev_err(priv->dev, "timeout during timing setup\n");
316 goto write_end;
317 }
318
319 /* 47.3.1.3.3
320 * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
321 * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
322 * for each write access. The lock code is documented in the register
323 * description. Both the unlock code and address can be written in the
324 * same operation.
325 */
326 if (priv->params->bank_address_words != 0) {
327 /*
328 * In banked/i.MX7 mode the OTP register bank goes into waddr
329 * see i.MX 7Solo Applications Processor Reference Manual, Rev.
330 * 0.1 section 6.4.3.1
331 */
332 offset = offset / priv->config->word_size;
333 waddr = offset / priv->params->bank_address_words;
334 word = offset & (priv->params->bank_address_words - 1);
335 } else {
336 /*
337 * Non-banked i.MX6 mode.
338 * OTP write/read address specifies one of 128 word address
339 * locations
340 */
341 waddr = offset / 4;
342 }
343
344 ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
345 ctrl &= ~priv->params->ctrl.bm_addr;
346 ctrl |= waddr & priv->params->ctrl.bm_addr;
347 ctrl |= IMX_OCOTP_WR_UNLOCK;
348
349 writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
350
351 /* 47.3.1.3.4
352 * Write the data to the HW_OCOTP_DATA register. This will automatically
353 * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
354 * protect programming same OTP bit twice, before program OCOTP will
355 * automatically read fuse value in OTP and use read value to mask
356 * program data. The controller will use masked program data to program
357 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
358 * fields with 1's will result in that OTP bit being programmed. Bit
359 * fields with 0's will be ignored. At the same time that the write is
360 * accepted, the controller makes an internal copy of
361 * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
362 * sequence is initiated. This copy guarantees that erroneous writes to
363 * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
364 * should also be noted that during the programming HW_OCOTP_DATA will
365 * shift right (with zero fill). This shifting is required to program
366 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
367 * modified.
368 * Note: on i.MX7 there are four data fields to write for banked write
369 * with the fuse blowing operation only taking place after data0
370 * has been written. This is why data0 must always be the last
371 * register written.
372 */
373 if (priv->params->bank_address_words != 0) {
374 /* Banked/i.MX7 mode */
375 switch (word) {
376 case 0:
377 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
378 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
379 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
380 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
381 break;
382 case 1:
383 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
384 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
385 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
386 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
387 break;
388 case 2:
389 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
390 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
391 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
392 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
393 break;
394 case 3:
395 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
396 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
397 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
398 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
399 break;
400 }
401 } else {
402 /* Non-banked i.MX6 mode */
403 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
404 }
405
406 /* 47.4.1.4.5
407 * Once complete, the controller will clear BUSY. A write request to a
408 * protected or locked region will result in no OTP access and no
409 * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
410 * be set. It must be cleared by software before any new write access
411 * can be issued.
412 */
413 ret = imx_ocotp_wait_for_busy(priv, 0);
414 if (ret < 0) {
415 if (ret == -EPERM) {
416 dev_err(priv->dev, "failed write to locked region");
417 imx_ocotp_clr_err_if_set(priv);
418 } else {
419 dev_err(priv->dev, "timeout during data write\n");
420 }
421 goto write_end;
422 }
423
424 /* 47.3.1.4
425 * Write Postamble: Due to internal electrical characteristics of the
426 * OTP during writes, all OTP operations following a write must be
427 * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
428 * the write.
429 */
430 udelay(2);
431
432 /* reload all shadow registers */
433 writel(priv->params->ctrl.bm_rel_shadows,
434 priv->base + IMX_OCOTP_ADDR_CTRL_SET);
435 ret = imx_ocotp_wait_for_busy(priv,
436 priv->params->ctrl.bm_rel_shadows);
437 if (ret < 0)
438 dev_err(priv->dev, "timeout during shadow register reload\n");
439
440 write_end:
441 clk_disable_unprepare(priv->clk);
442 mutex_unlock(&ocotp_mutex);
443 return ret < 0 ? ret : bytes;
444 }
445
446 static struct nvmem_config imx_ocotp_nvmem_config = {
447 .name = "imx-ocotp",
448 .read_only = false,
449 .word_size = 4,
450 .stride = 4,
451 .reg_read = imx_ocotp_read,
452 .reg_write = imx_ocotp_write,
453 };
454
455 static const struct ocotp_params imx6q_params = {
456 .nregs = 128,
457 .bank_address_words = 0,
458 .set_timing = imx_ocotp_set_imx6_timing,
459 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
460 };
461
462 static const struct ocotp_params imx6sl_params = {
463 .nregs = 64,
464 .bank_address_words = 0,
465 .set_timing = imx_ocotp_set_imx6_timing,
466 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
467 };
468
469 static const struct ocotp_params imx6sll_params = {
470 .nregs = 128,
471 .bank_address_words = 0,
472 .set_timing = imx_ocotp_set_imx6_timing,
473 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
474 };
475
476 static const struct ocotp_params imx6sx_params = {
477 .nregs = 128,
478 .bank_address_words = 0,
479 .set_timing = imx_ocotp_set_imx6_timing,
480 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
481 };
482
483 static const struct ocotp_params imx6ul_params = {
484 .nregs = 128,
485 .bank_address_words = 0,
486 .set_timing = imx_ocotp_set_imx6_timing,
487 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
488 };
489
490 static const struct ocotp_params imx6ull_params = {
491 .nregs = 64,
492 .bank_address_words = 0,
493 .set_timing = imx_ocotp_set_imx6_timing,
494 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
495 };
496
497 static const struct ocotp_params imx7d_params = {
498 .nregs = 64,
499 .bank_address_words = 4,
500 .set_timing = imx_ocotp_set_imx7_timing,
501 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
502 };
503
504 static const struct ocotp_params imx7ulp_params = {
505 .nregs = 256,
506 .bank_address_words = 0,
507 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
508 };
509
510 static const struct ocotp_params imx8mq_params = {
511 .nregs = 256,
512 .bank_address_words = 0,
513 .set_timing = imx_ocotp_set_imx6_timing,
514 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
515 };
516
517 static const struct ocotp_params imx8mm_params = {
518 .nregs = 256,
519 .bank_address_words = 0,
520 .set_timing = imx_ocotp_set_imx6_timing,
521 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
522 };
523
524 static const struct ocotp_params imx8mn_params = {
525 .nregs = 256,
526 .bank_address_words = 0,
527 .set_timing = imx_ocotp_set_imx6_timing,
528 .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
529 };
530
531 static const struct ocotp_params imx8mp_params = {
532 .nregs = 384,
533 .bank_address_words = 0,
534 .set_timing = imx_ocotp_set_imx6_timing,
535 .ctrl = IMX_OCOTP_BM_CTRL_8MP,
536 };
537
538 static const struct of_device_id imx_ocotp_dt_ids[] = {
539 { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params },
540 { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
541 { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
542 { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
543 { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params },
544 { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params },
545 { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
546 { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
547 { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params },
548 { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params },
549 { .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params },
550 { .compatible = "fsl,imx8mp-ocotp", .data = &imx8mp_params },
551 { },
552 };
553 MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
554
imx_ocotp_probe(struct platform_device * pdev)555 static int imx_ocotp_probe(struct platform_device *pdev)
556 {
557 struct device *dev = &pdev->dev;
558 struct ocotp_priv *priv;
559 struct nvmem_device *nvmem;
560
561 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
562 if (!priv)
563 return -ENOMEM;
564
565 priv->dev = dev;
566
567 priv->base = devm_platform_ioremap_resource(pdev, 0);
568 if (IS_ERR(priv->base))
569 return PTR_ERR(priv->base);
570
571 priv->clk = devm_clk_get(dev, NULL);
572 if (IS_ERR(priv->clk))
573 return PTR_ERR(priv->clk);
574
575 priv->params = of_device_get_match_data(&pdev->dev);
576 imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
577 imx_ocotp_nvmem_config.dev = dev;
578 imx_ocotp_nvmem_config.priv = priv;
579 priv->config = &imx_ocotp_nvmem_config;
580
581 clk_prepare_enable(priv->clk);
582 imx_ocotp_clr_err_if_set(priv);
583 clk_disable_unprepare(priv->clk);
584
585 nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
586
587 return PTR_ERR_OR_ZERO(nvmem);
588 }
589
590 static struct platform_driver imx_ocotp_driver = {
591 .probe = imx_ocotp_probe,
592 .driver = {
593 .name = "imx_ocotp",
594 .of_match_table = imx_ocotp_dt_ids,
595 },
596 };
597 module_platform_driver(imx_ocotp_driver);
598
599 MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
600 MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
601 MODULE_LICENSE("GPL v2");
602
