1 /****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 9 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 10 * Copyright(c) 2012 - 2014, 2018, 2020 Intel Corporation 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * The full GNU General Public License is included in this distribution 22 * in the file called COPYING. 23 * 24 * Contact Information: 25 * Intel Linux Wireless <linuxwifi@intel.com> 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 * 28 * BSD LICENSE 29 * 30 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH 31 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH 32 * Copyright(c) 2012 - 2014, 2018, 2020 Intel Corporation 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 39 * * Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * * Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in 43 * the documentation and/or other materials provided with the 44 * distribution. 45 * * Neither the name Intel Corporation nor the names of its 46 * contributors may be used to endorse or promote products derived 47 * from this software without specific prior written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 50 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 51 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 52 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 53 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 54 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 55 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 57 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 58 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 59 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 60 * 61 *****************************************************************************/ 62 63 #ifndef __iwl_fw_api_phy_ctxt_h__ 64 #define __iwl_fw_api_phy_ctxt_h__ 65 66 /* Supported bands */ 67 #define PHY_BAND_5 (0) 68 #define PHY_BAND_24 (1) 69 70 /* Supported channel width, vary if there is VHT support */ 71 #define PHY_VHT_CHANNEL_MODE20 (0x0) 72 #define PHY_VHT_CHANNEL_MODE40 (0x1) 73 #define PHY_VHT_CHANNEL_MODE80 (0x2) 74 #define PHY_VHT_CHANNEL_MODE160 (0x3) 75 76 /* 77 * Control channel position: 78 * For legacy set bit means upper channel, otherwise lower. 79 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq 80 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0. 81 * center_freq 82 * | 83 * 40Mhz |_______|_______| 84 * 80Mhz |_______|_______|_______|_______| 85 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______| 86 * code 011 010 001 000 | 100 101 110 111 87 */ 88 #define PHY_VHT_CTRL_POS_1_BELOW (0x0) 89 #define PHY_VHT_CTRL_POS_2_BELOW (0x1) 90 #define PHY_VHT_CTRL_POS_3_BELOW (0x2) 91 #define PHY_VHT_CTRL_POS_4_BELOW (0x3) 92 #define PHY_VHT_CTRL_POS_1_ABOVE (0x4) 93 #define PHY_VHT_CTRL_POS_2_ABOVE (0x5) 94 #define PHY_VHT_CTRL_POS_3_ABOVE (0x6) 95 #define PHY_VHT_CTRL_POS_4_ABOVE (0x7) 96 97 /* 98 * struct iwl_fw_channel_info_v1 - channel information 99 * 100 * @band: PHY_BAND_* 101 * @channel: channel number 102 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 103 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 104 */ 105 struct iwl_fw_channel_info_v1 { 106 u8 band; 107 u8 channel; 108 u8 width; 109 u8 ctrl_pos; 110 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */ 111 112 /* 113 * struct iwl_fw_channel_info - channel information 114 * 115 * @channel: channel number 116 * @band: PHY_BAND_* 117 * @width: PHY_[VHT|LEGACY]_CHANNEL_* 118 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_* 119 * @reserved: for future use and alignment 120 */ 121 struct iwl_fw_channel_info { 122 __le32 channel; 123 u8 band; 124 u8 width; 125 u8 ctrl_pos; 126 u8 reserved; 127 } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */ 128 129 #define PHY_RX_CHAIN_DRIVER_FORCE_POS (0) 130 #define PHY_RX_CHAIN_DRIVER_FORCE_MSK \ 131 (0x1 << PHY_RX_CHAIN_DRIVER_FORCE_POS) 132 #define PHY_RX_CHAIN_VALID_POS (1) 133 #define PHY_RX_CHAIN_VALID_MSK \ 134 (0x7 << PHY_RX_CHAIN_VALID_POS) 135 #define PHY_RX_CHAIN_FORCE_SEL_POS (4) 136 #define PHY_RX_CHAIN_FORCE_SEL_MSK \ 137 (0x7 << PHY_RX_CHAIN_FORCE_SEL_POS) 138 #define PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7) 139 #define PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \ 140 (0x7 << PHY_RX_CHAIN_FORCE_MIMO_SEL_POS) 141 #define PHY_RX_CHAIN_CNT_POS (10) 142 #define PHY_RX_CHAIN_CNT_MSK \ 143 (0x3 << PHY_RX_CHAIN_CNT_POS) 144 #define PHY_RX_CHAIN_MIMO_CNT_POS (12) 145 #define PHY_RX_CHAIN_MIMO_CNT_MSK \ 146 (0x3 << PHY_RX_CHAIN_MIMO_CNT_POS) 147 #define PHY_RX_CHAIN_MIMO_FORCE_POS (14) 148 #define PHY_RX_CHAIN_MIMO_FORCE_MSK \ 149 (0x1 << PHY_RX_CHAIN_MIMO_FORCE_POS) 150 151 /* TODO: fix the value, make it depend on firmware at runtime? */ 152 #define NUM_PHY_CTX 3 153 154 /* TODO: complete missing documentation */ 155 /** 156 * struct iwl_phy_context_cmd_tail - tail of iwl_phy_ctx_cmd for alignment with 157 * various channel structures. 158 * 159 * @txchain_info: ??? 160 * @rxchain_info: ??? 161 * @acquisition_data: ??? 162 * @dsp_cfg_flags: set to 0 163 */ 164 struct iwl_phy_context_cmd_tail { 165 __le32 txchain_info; 166 __le32 rxchain_info; 167 __le32 acquisition_data; 168 __le32 dsp_cfg_flags; 169 } __packed; 170 171 /** 172 * struct iwl_phy_context_cmd - config of the PHY context 173 * ( PHY_CONTEXT_CMD = 0x8 ) 174 * @id_and_color: ID and color of the relevant Binding 175 * @action: action to perform, one of FW_CTXT_ACTION_* 176 * @apply_time: 0 means immediate apply and context switch. 177 * other value means apply new params after X usecs 178 * @tx_param_color: ??? 179 * @ci: channel info 180 * @tail: command tail 181 */ 182 struct iwl_phy_context_cmd_v1 { 183 /* COMMON_INDEX_HDR_API_S_VER_1 */ 184 __le32 id_and_color; 185 __le32 action; 186 /* PHY_CONTEXT_DATA_API_S_VER_3 */ 187 __le32 apply_time; 188 __le32 tx_param_color; 189 struct iwl_fw_channel_info ci; 190 struct iwl_phy_context_cmd_tail tail; 191 } __packed; /* PHY_CONTEXT_CMD_API_VER_1 */ 192 193 /** 194 * struct iwl_phy_context_cmd - config of the PHY context 195 * ( PHY_CONTEXT_CMD = 0x8 ) 196 * @id_and_color: ID and color of the relevant Binding 197 * @action: action to perform, one of FW_CTXT_ACTION_* 198 * @lmac_id: the lmac id the phy context belongs to 199 * @ci: channel info 200 * @rxchain_info: ??? 201 * @dsp_cfg_flags: set to 0 202 * @reserved: reserved to align to 64 bit 203 */ 204 struct iwl_phy_context_cmd { 205 /* COMMON_INDEX_HDR_API_S_VER_1 */ 206 __le32 id_and_color; 207 __le32 action; 208 /* PHY_CONTEXT_DATA_API_S_VER_3 */ 209 struct iwl_fw_channel_info ci; 210 __le32 lmac_id; 211 __le32 rxchain_info; 212 __le32 dsp_cfg_flags; 213 __le32 reserved; 214 } __packed; /* PHY_CONTEXT_CMD_API_VER_3 */ 215 #endif /* __iwl_fw_api_phy_ctxt_h__ */ 216
