1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Marvell 10G 88x3310 PHY driver
4 *
5 * Based upon the ID registers, this PHY appears to be a mixture of IPs
6 * from two different companies.
7 *
8 * There appears to be several different data paths through the PHY which
9 * are automatically managed by the PHY. The following has been determined
10 * via observation and experimentation for a setup using single-lane Serdes:
11 *
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
15 *
16 * With XAUI, observation shows:
17 *
18 * XAUI PHYXS -- <appropriate PCS as above>
19 *
20 * and no switching of the host interface mode occurs.
21 *
22 * If both the fiber and copper ports are connected, the first to gain
23 * link takes priority and the other port is completely locked out.
24 */
25 #include <linux/ctype.h>
26 #include <linux/delay.h>
27 #include <linux/hwmon.h>
28 #include <linux/marvell_phy.h>
29 #include <linux/phy.h>
30 #include <linux/sfp.h>
31
32 #define MV_PHY_ALASKA_NBT_QUIRK_MASK 0xfffffffe
33 #define MV_PHY_ALASKA_NBT_QUIRK_REV (MARVELL_PHY_ID_88X3310 | 0xa)
34
35 enum {
36 MV_PMA_FW_VER0 = 0xc011,
37 MV_PMA_FW_VER1 = 0xc012,
38 MV_PMA_BOOT = 0xc050,
39 MV_PMA_BOOT_FATAL = BIT(0),
40
41 MV_PCS_BASE_T = 0x0000,
42 MV_PCS_BASE_R = 0x1000,
43 MV_PCS_1000BASEX = 0x2000,
44
45 MV_PCS_CSCR1 = 0x8000,
46 MV_PCS_CSCR1_ED_MASK = 0x0300,
47 MV_PCS_CSCR1_ED_OFF = 0x0000,
48 MV_PCS_CSCR1_ED_RX = 0x0200,
49 MV_PCS_CSCR1_ED_NLP = 0x0300,
50 MV_PCS_CSCR1_MDIX_MASK = 0x0060,
51 MV_PCS_CSCR1_MDIX_MDI = 0x0000,
52 MV_PCS_CSCR1_MDIX_MDIX = 0x0020,
53 MV_PCS_CSCR1_MDIX_AUTO = 0x0060,
54
55 MV_PCS_CSSR1 = 0x8008,
56 MV_PCS_CSSR1_SPD1_MASK = 0xc000,
57 MV_PCS_CSSR1_SPD1_SPD2 = 0xc000,
58 MV_PCS_CSSR1_SPD1_1000 = 0x8000,
59 MV_PCS_CSSR1_SPD1_100 = 0x4000,
60 MV_PCS_CSSR1_SPD1_10 = 0x0000,
61 MV_PCS_CSSR1_DUPLEX_FULL= BIT(13),
62 MV_PCS_CSSR1_RESOLVED = BIT(11),
63 MV_PCS_CSSR1_MDIX = BIT(6),
64 MV_PCS_CSSR1_SPD2_MASK = 0x000c,
65 MV_PCS_CSSR1_SPD2_5000 = 0x0008,
66 MV_PCS_CSSR1_SPD2_2500 = 0x0004,
67 MV_PCS_CSSR1_SPD2_10000 = 0x0000,
68
69 /* Temperature read register (88E2110 only) */
70 MV_PCS_TEMP = 0x8042,
71
72 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
73 * registers appear to set themselves to the 0x800X when AN is
74 * restarted, but status registers appear readable from either.
75 */
76 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
77 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
78
79 /* Vendor2 MMD registers */
80 MV_V2_PORT_CTRL = 0xf001,
81 MV_V2_PORT_CTRL_SWRST = BIT(15),
82 MV_V2_PORT_CTRL_PWRDOWN = BIT(11),
83 MV_V2_PORT_MAC_TYPE_MASK = 0x7,
84 MV_V2_PORT_MAC_TYPE_RATE_MATCH = 0x6,
85 /* Temperature control/read registers (88X3310 only) */
86 MV_V2_TEMP_CTRL = 0xf08a,
87 MV_V2_TEMP_CTRL_MASK = 0xc000,
88 MV_V2_TEMP_CTRL_SAMPLE = 0x0000,
89 MV_V2_TEMP_CTRL_DISABLE = 0xc000,
90 MV_V2_TEMP = 0xf08c,
91 MV_V2_TEMP_UNKNOWN = 0x9600, /* unknown function */
92 };
93
94 struct mv3310_priv {
95 u32 firmware_ver;
96 bool rate_match;
97
98 struct device *hwmon_dev;
99 char *hwmon_name;
100 };
101
102 #ifdef CONFIG_HWMON
mv3310_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)103 static umode_t mv3310_hwmon_is_visible(const void *data,
104 enum hwmon_sensor_types type,
105 u32 attr, int channel)
106 {
107 if (type == hwmon_chip && attr == hwmon_chip_update_interval)
108 return 0444;
109 if (type == hwmon_temp && attr == hwmon_temp_input)
110 return 0444;
111 return 0;
112 }
113
mv3310_hwmon_read_temp_reg(struct phy_device * phydev)114 static int mv3310_hwmon_read_temp_reg(struct phy_device *phydev)
115 {
116 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP);
117 }
118
mv2110_hwmon_read_temp_reg(struct phy_device * phydev)119 static int mv2110_hwmon_read_temp_reg(struct phy_device *phydev)
120 {
121 return phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_TEMP);
122 }
123
mv10g_hwmon_read_temp_reg(struct phy_device * phydev)124 static int mv10g_hwmon_read_temp_reg(struct phy_device *phydev)
125 {
126 if (phydev->drv->phy_id == MARVELL_PHY_ID_88X3310)
127 return mv3310_hwmon_read_temp_reg(phydev);
128 else /* MARVELL_PHY_ID_88E2110 */
129 return mv2110_hwmon_read_temp_reg(phydev);
130 }
131
mv3310_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * value)132 static int mv3310_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
133 u32 attr, int channel, long *value)
134 {
135 struct phy_device *phydev = dev_get_drvdata(dev);
136 int temp;
137
138 if (type == hwmon_chip && attr == hwmon_chip_update_interval) {
139 *value = MSEC_PER_SEC;
140 return 0;
141 }
142
143 if (type == hwmon_temp && attr == hwmon_temp_input) {
144 temp = mv10g_hwmon_read_temp_reg(phydev);
145 if (temp < 0)
146 return temp;
147
148 *value = ((temp & 0xff) - 75) * 1000;
149
150 return 0;
151 }
152
153 return -EOPNOTSUPP;
154 }
155
156 static const struct hwmon_ops mv3310_hwmon_ops = {
157 .is_visible = mv3310_hwmon_is_visible,
158 .read = mv3310_hwmon_read,
159 };
160
161 static u32 mv3310_hwmon_chip_config[] = {
162 HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL,
163 0,
164 };
165
166 static const struct hwmon_channel_info mv3310_hwmon_chip = {
167 .type = hwmon_chip,
168 .config = mv3310_hwmon_chip_config,
169 };
170
171 static u32 mv3310_hwmon_temp_config[] = {
172 HWMON_T_INPUT,
173 0,
174 };
175
176 static const struct hwmon_channel_info mv3310_hwmon_temp = {
177 .type = hwmon_temp,
178 .config = mv3310_hwmon_temp_config,
179 };
180
181 static const struct hwmon_channel_info *mv3310_hwmon_info[] = {
182 &mv3310_hwmon_chip,
183 &mv3310_hwmon_temp,
184 NULL,
185 };
186
187 static const struct hwmon_chip_info mv3310_hwmon_chip_info = {
188 .ops = &mv3310_hwmon_ops,
189 .info = mv3310_hwmon_info,
190 };
191
mv3310_hwmon_config(struct phy_device * phydev,bool enable)192 static int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
193 {
194 u16 val;
195 int ret;
196
197 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310)
198 return 0;
199
200 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP,
201 MV_V2_TEMP_UNKNOWN);
202 if (ret < 0)
203 return ret;
204
205 val = enable ? MV_V2_TEMP_CTRL_SAMPLE : MV_V2_TEMP_CTRL_DISABLE;
206
207 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL,
208 MV_V2_TEMP_CTRL_MASK, val);
209 }
210
mv3310_hwmon_probe(struct phy_device * phydev)211 static int mv3310_hwmon_probe(struct phy_device *phydev)
212 {
213 struct device *dev = &phydev->mdio.dev;
214 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
215 int i, j, ret;
216
217 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
218 if (!priv->hwmon_name)
219 return -ENODEV;
220
221 for (i = j = 0; priv->hwmon_name[i]; i++) {
222 if (isalnum(priv->hwmon_name[i])) {
223 if (i != j)
224 priv->hwmon_name[j] = priv->hwmon_name[i];
225 j++;
226 }
227 }
228 priv->hwmon_name[j] = '\0';
229
230 ret = mv3310_hwmon_config(phydev, true);
231 if (ret)
232 return ret;
233
234 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev,
235 priv->hwmon_name, phydev,
236 &mv3310_hwmon_chip_info, NULL);
237
238 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
239 }
240 #else
mv3310_hwmon_config(struct phy_device * phydev,bool enable)241 static inline int mv3310_hwmon_config(struct phy_device *phydev, bool enable)
242 {
243 return 0;
244 }
245
mv3310_hwmon_probe(struct phy_device * phydev)246 static int mv3310_hwmon_probe(struct phy_device *phydev)
247 {
248 return 0;
249 }
250 #endif
251
mv3310_power_down(struct phy_device * phydev)252 static int mv3310_power_down(struct phy_device *phydev)
253 {
254 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
255 MV_V2_PORT_CTRL_PWRDOWN);
256 }
257
mv3310_power_up(struct phy_device * phydev)258 static int mv3310_power_up(struct phy_device *phydev)
259 {
260 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
261 int ret;
262
263 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
264 MV_V2_PORT_CTRL_PWRDOWN);
265
266 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 ||
267 priv->firmware_ver < 0x00030000)
268 return ret;
269
270 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL,
271 MV_V2_PORT_CTRL_SWRST);
272 }
273
mv3310_reset(struct phy_device * phydev,u32 unit)274 static int mv3310_reset(struct phy_device *phydev, u32 unit)
275 {
276 int val, err;
277
278 err = phy_modify_mmd(phydev, MDIO_MMD_PCS, unit + MDIO_CTRL1,
279 MDIO_CTRL1_RESET, MDIO_CTRL1_RESET);
280 if (err < 0)
281 return err;
282
283 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_PCS,
284 unit + MDIO_CTRL1, val,
285 !(val & MDIO_CTRL1_RESET),
286 5000, 100000, true);
287 }
288
mv3310_get_edpd(struct phy_device * phydev,u16 * edpd)289 static int mv3310_get_edpd(struct phy_device *phydev, u16 *edpd)
290 {
291 int val;
292
293 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1);
294 if (val < 0)
295 return val;
296
297 switch (val & MV_PCS_CSCR1_ED_MASK) {
298 case MV_PCS_CSCR1_ED_NLP:
299 *edpd = 1000;
300 break;
301 case MV_PCS_CSCR1_ED_RX:
302 *edpd = ETHTOOL_PHY_EDPD_NO_TX;
303 break;
304 default:
305 *edpd = ETHTOOL_PHY_EDPD_DISABLE;
306 break;
307 }
308 return 0;
309 }
310
mv3310_set_edpd(struct phy_device * phydev,u16 edpd)311 static int mv3310_set_edpd(struct phy_device *phydev, u16 edpd)
312 {
313 u16 val;
314 int err;
315
316 switch (edpd) {
317 case 1000:
318 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
319 val = MV_PCS_CSCR1_ED_NLP;
320 break;
321
322 case ETHTOOL_PHY_EDPD_NO_TX:
323 val = MV_PCS_CSCR1_ED_RX;
324 break;
325
326 case ETHTOOL_PHY_EDPD_DISABLE:
327 val = MV_PCS_CSCR1_ED_OFF;
328 break;
329
330 default:
331 return -EINVAL;
332 }
333
334 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
335 MV_PCS_CSCR1_ED_MASK, val);
336 if (err > 0)
337 err = mv3310_reset(phydev, MV_PCS_BASE_T);
338
339 return err;
340 }
341
mv3310_sfp_insert(void * upstream,const struct sfp_eeprom_id * id)342 static int mv3310_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
343 {
344 struct phy_device *phydev = upstream;
345 __ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
346 phy_interface_t iface;
347
348 sfp_parse_support(phydev->sfp_bus, id, support);
349 iface = sfp_select_interface(phydev->sfp_bus, support);
350
351 if (iface != PHY_INTERFACE_MODE_10GBASER) {
352 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
353 return -EINVAL;
354 }
355 return 0;
356 }
357
358 static const struct sfp_upstream_ops mv3310_sfp_ops = {
359 .attach = phy_sfp_attach,
360 .detach = phy_sfp_detach,
361 .module_insert = mv3310_sfp_insert,
362 };
363
mv3310_probe(struct phy_device * phydev)364 static int mv3310_probe(struct phy_device *phydev)
365 {
366 struct mv3310_priv *priv;
367 u32 mmd_mask = MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
368 int ret;
369
370 if (!phydev->is_c45 ||
371 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask)
372 return -ENODEV;
373
374 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_BOOT);
375 if (ret < 0)
376 return ret;
377
378 if (ret & MV_PMA_BOOT_FATAL) {
379 dev_warn(&phydev->mdio.dev,
380 "PHY failed to boot firmware, status=%04x\n", ret);
381 return -ENODEV;
382 }
383
384 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
385 if (!priv)
386 return -ENOMEM;
387
388 dev_set_drvdata(&phydev->mdio.dev, priv);
389
390 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER0);
391 if (ret < 0)
392 return ret;
393
394 priv->firmware_ver = ret << 16;
395
396 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MV_PMA_FW_VER1);
397 if (ret < 0)
398 return ret;
399
400 priv->firmware_ver |= ret;
401
402 phydev_info(phydev, "Firmware version %u.%u.%u.%u\n",
403 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255,
404 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255);
405
406 /* Powering down the port when not in use saves about 600mW */
407 ret = mv3310_power_down(phydev);
408 if (ret)
409 return ret;
410
411 ret = mv3310_hwmon_probe(phydev);
412 if (ret)
413 return ret;
414
415 return phy_sfp_probe(phydev, &mv3310_sfp_ops);
416 }
417
mv3310_remove(struct phy_device * phydev)418 static void mv3310_remove(struct phy_device *phydev)
419 {
420 mv3310_hwmon_config(phydev, false);
421 }
422
mv3310_suspend(struct phy_device * phydev)423 static int mv3310_suspend(struct phy_device *phydev)
424 {
425 return mv3310_power_down(phydev);
426 }
427
mv3310_resume(struct phy_device * phydev)428 static int mv3310_resume(struct phy_device *phydev)
429 {
430 int ret;
431
432 ret = mv3310_power_up(phydev);
433 if (ret)
434 return ret;
435
436 return mv3310_hwmon_config(phydev, true);
437 }
438
439 /* Some PHYs in the Alaska family such as the 88X3310 and the 88E2010
440 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
441 * support 2.5GBASET and 5GBASET. For these models, we can still read their
442 * 2.5G/5G extended abilities register (1.21). We detect these models based on
443 * the PMA device identifier, with a mask matching models known to have this
444 * issue
445 */
mv3310_has_pma_ngbaset_quirk(struct phy_device * phydev)446 static bool mv3310_has_pma_ngbaset_quirk(struct phy_device *phydev)
447 {
448 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD))
449 return false;
450
451 /* Only some revisions of the 88X3310 family PMA seem to be impacted */
452 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] &
453 MV_PHY_ALASKA_NBT_QUIRK_MASK) == MV_PHY_ALASKA_NBT_QUIRK_REV;
454 }
455
mv3310_config_init(struct phy_device * phydev)456 static int mv3310_config_init(struct phy_device *phydev)
457 {
458 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
459 int err;
460 int val;
461
462 /* Check that the PHY interface type is compatible */
463 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
464 phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
465 phydev->interface != PHY_INTERFACE_MODE_XAUI &&
466 phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
467 phydev->interface != PHY_INTERFACE_MODE_10GBASER)
468 return -ENODEV;
469
470 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
471
472 /* Power up so reset works */
473 err = mv3310_power_up(phydev);
474 if (err)
475 return err;
476
477 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL);
478 if (val < 0)
479 return val;
480 priv->rate_match = ((val & MV_V2_PORT_MAC_TYPE_MASK) ==
481 MV_V2_PORT_MAC_TYPE_RATE_MATCH);
482
483 /* Enable EDPD mode - saving 600mW */
484 return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
485 }
486
mv3310_get_features(struct phy_device * phydev)487 static int mv3310_get_features(struct phy_device *phydev)
488 {
489 int ret, val;
490
491 ret = genphy_c45_pma_read_abilities(phydev);
492 if (ret)
493 return ret;
494
495 if (mv3310_has_pma_ngbaset_quirk(phydev)) {
496 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD,
497 MDIO_PMA_NG_EXTABLE);
498 if (val < 0)
499 return val;
500
501 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
502 phydev->supported,
503 val & MDIO_PMA_NG_EXTABLE_2_5GBT);
504
505 linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
506 phydev->supported,
507 val & MDIO_PMA_NG_EXTABLE_5GBT);
508 }
509
510 return 0;
511 }
512
mv3310_config_mdix(struct phy_device * phydev)513 static int mv3310_config_mdix(struct phy_device *phydev)
514 {
515 u16 val;
516 int err;
517
518 switch (phydev->mdix_ctrl) {
519 case ETH_TP_MDI_AUTO:
520 val = MV_PCS_CSCR1_MDIX_AUTO;
521 break;
522 case ETH_TP_MDI_X:
523 val = MV_PCS_CSCR1_MDIX_MDIX;
524 break;
525 case ETH_TP_MDI:
526 val = MV_PCS_CSCR1_MDIX_MDI;
527 break;
528 default:
529 return -EINVAL;
530 }
531
532 err = phy_modify_mmd_changed(phydev, MDIO_MMD_PCS, MV_PCS_CSCR1,
533 MV_PCS_CSCR1_MDIX_MASK, val);
534 if (err > 0)
535 err = mv3310_reset(phydev, MV_PCS_BASE_T);
536
537 return err;
538 }
539
mv3310_config_aneg(struct phy_device * phydev)540 static int mv3310_config_aneg(struct phy_device *phydev)
541 {
542 bool changed = false;
543 u16 reg;
544 int ret;
545
546 ret = mv3310_config_mdix(phydev);
547 if (ret < 0)
548 return ret;
549
550 if (phydev->autoneg == AUTONEG_DISABLE)
551 return genphy_c45_pma_setup_forced(phydev);
552
553 ret = genphy_c45_an_config_aneg(phydev);
554 if (ret < 0)
555 return ret;
556 if (ret > 0)
557 changed = true;
558
559 /* Clause 45 has no standardized support for 1000BaseT, therefore
560 * use vendor registers for this mode.
561 */
562 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
563 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MV_AN_CTRL1000,
564 ADVERTISE_1000FULL | ADVERTISE_1000HALF, reg);
565 if (ret < 0)
566 return ret;
567 if (ret > 0)
568 changed = true;
569
570 return genphy_c45_check_and_restart_aneg(phydev, changed);
571 }
572
mv3310_aneg_done(struct phy_device * phydev)573 static int mv3310_aneg_done(struct phy_device *phydev)
574 {
575 int val;
576
577 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
578 if (val < 0)
579 return val;
580
581 if (val & MDIO_STAT1_LSTATUS)
582 return 1;
583
584 return genphy_c45_aneg_done(phydev);
585 }
586
mv3310_update_interface(struct phy_device * phydev)587 static void mv3310_update_interface(struct phy_device *phydev)
588 {
589 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev);
590
591 /* In "XFI with Rate Matching" mode the PHY interface is fixed at
592 * 10Gb. The PHY adapts the rate to actual wire speed with help of
593 * internal 16KB buffer.
594 */
595 if (priv->rate_match) {
596 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
597 return;
598 }
599
600 if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
601 phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
602 phydev->interface == PHY_INTERFACE_MODE_10GBASER) &&
603 phydev->link) {
604 /* The PHY automatically switches its serdes interface (and
605 * active PHYXS instance) between Cisco SGMII, 10GBase-R and
606 * 2500BaseX modes according to the speed. Florian suggests
607 * setting phydev->interface to communicate this to the MAC.
608 * Only do this if we are already in one of the above modes.
609 */
610 switch (phydev->speed) {
611 case SPEED_10000:
612 phydev->interface = PHY_INTERFACE_MODE_10GBASER;
613 break;
614 case SPEED_2500:
615 phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
616 break;
617 case SPEED_1000:
618 case SPEED_100:
619 case SPEED_10:
620 phydev->interface = PHY_INTERFACE_MODE_SGMII;
621 break;
622 default:
623 break;
624 }
625 }
626 }
627
628 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
mv3310_read_status_10gbaser(struct phy_device * phydev)629 static int mv3310_read_status_10gbaser(struct phy_device *phydev)
630 {
631 phydev->link = 1;
632 phydev->speed = SPEED_10000;
633 phydev->duplex = DUPLEX_FULL;
634
635 return 0;
636 }
637
mv3310_read_status_copper(struct phy_device * phydev)638 static int mv3310_read_status_copper(struct phy_device *phydev)
639 {
640 int cssr1, speed, val;
641
642 val = genphy_c45_read_link(phydev);
643 if (val < 0)
644 return val;
645
646 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
647 if (val < 0)
648 return val;
649
650 cssr1 = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_CSSR1);
651 if (cssr1 < 0)
652 return val;
653
654 /* If the link settings are not resolved, mark the link down */
655 if (!(cssr1 & MV_PCS_CSSR1_RESOLVED)) {
656 phydev->link = 0;
657 return 0;
658 }
659
660 /* Read the copper link settings */
661 speed = cssr1 & MV_PCS_CSSR1_SPD1_MASK;
662 if (speed == MV_PCS_CSSR1_SPD1_SPD2)
663 speed |= cssr1 & MV_PCS_CSSR1_SPD2_MASK;
664
665 switch (speed) {
666 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_10000:
667 phydev->speed = SPEED_10000;
668 break;
669
670 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_5000:
671 phydev->speed = SPEED_5000;
672 break;
673
674 case MV_PCS_CSSR1_SPD1_SPD2 | MV_PCS_CSSR1_SPD2_2500:
675 phydev->speed = SPEED_2500;
676 break;
677
678 case MV_PCS_CSSR1_SPD1_1000:
679 phydev->speed = SPEED_1000;
680 break;
681
682 case MV_PCS_CSSR1_SPD1_100:
683 phydev->speed = SPEED_100;
684 break;
685
686 case MV_PCS_CSSR1_SPD1_10:
687 phydev->speed = SPEED_10;
688 break;
689 }
690
691 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ?
692 DUPLEX_FULL : DUPLEX_HALF;
693 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ?
694 ETH_TP_MDI_X : ETH_TP_MDI;
695
696 if (val & MDIO_AN_STAT1_COMPLETE) {
697 val = genphy_c45_read_lpa(phydev);
698 if (val < 0)
699 return val;
700
701 /* Read the link partner's 1G advertisement */
702 val = phy_read_mmd(phydev, MDIO_MMD_AN, MV_AN_STAT1000);
703 if (val < 0)
704 return val;
705
706 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
707
708 /* Update the pause status */
709 phy_resolve_aneg_pause(phydev);
710 }
711
712 return 0;
713 }
714
mv3310_read_status(struct phy_device * phydev)715 static int mv3310_read_status(struct phy_device *phydev)
716 {
717 int err, val;
718
719 phydev->speed = SPEED_UNKNOWN;
720 phydev->duplex = DUPLEX_UNKNOWN;
721 linkmode_zero(phydev->lp_advertising);
722 phydev->link = 0;
723 phydev->pause = 0;
724 phydev->asym_pause = 0;
725 phydev->mdix = ETH_TP_MDI_INVALID;
726
727 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MV_PCS_BASE_R + MDIO_STAT1);
728 if (val < 0)
729 return val;
730
731 if (val & MDIO_STAT1_LSTATUS)
732 err = mv3310_read_status_10gbaser(phydev);
733 else
734 err = mv3310_read_status_copper(phydev);
735 if (err < 0)
736 return err;
737
738 if (phydev->link)
739 mv3310_update_interface(phydev);
740
741 return 0;
742 }
743
mv3310_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)744 static int mv3310_get_tunable(struct phy_device *phydev,
745 struct ethtool_tunable *tuna, void *data)
746 {
747 switch (tuna->id) {
748 case ETHTOOL_PHY_EDPD:
749 return mv3310_get_edpd(phydev, data);
750 default:
751 return -EOPNOTSUPP;
752 }
753 }
754
mv3310_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)755 static int mv3310_set_tunable(struct phy_device *phydev,
756 struct ethtool_tunable *tuna, const void *data)
757 {
758 switch (tuna->id) {
759 case ETHTOOL_PHY_EDPD:
760 return mv3310_set_edpd(phydev, *(u16 *)data);
761 default:
762 return -EOPNOTSUPP;
763 }
764 }
765
766 static struct phy_driver mv3310_drivers[] = {
767 {
768 .phy_id = MARVELL_PHY_ID_88X3310,
769 .phy_id_mask = MARVELL_PHY_ID_MASK,
770 .name = "mv88x3310",
771 .get_features = mv3310_get_features,
772 .config_init = mv3310_config_init,
773 .probe = mv3310_probe,
774 .suspend = mv3310_suspend,
775 .resume = mv3310_resume,
776 .config_aneg = mv3310_config_aneg,
777 .aneg_done = mv3310_aneg_done,
778 .read_status = mv3310_read_status,
779 .get_tunable = mv3310_get_tunable,
780 .set_tunable = mv3310_set_tunable,
781 .remove = mv3310_remove,
782 },
783 {
784 .phy_id = MARVELL_PHY_ID_88E2110,
785 .phy_id_mask = MARVELL_PHY_ID_MASK,
786 .name = "mv88x2110",
787 .probe = mv3310_probe,
788 .suspend = mv3310_suspend,
789 .resume = mv3310_resume,
790 .config_init = mv3310_config_init,
791 .config_aneg = mv3310_config_aneg,
792 .aneg_done = mv3310_aneg_done,
793 .read_status = mv3310_read_status,
794 .get_tunable = mv3310_get_tunable,
795 .set_tunable = mv3310_set_tunable,
796 .remove = mv3310_remove,
797 },
798 };
799
800 module_phy_driver(mv3310_drivers);
801
802 static struct mdio_device_id __maybe_unused mv3310_tbl[] = {
803 { MARVELL_PHY_ID_88X3310, MARVELL_PHY_ID_MASK },
804 { MARVELL_PHY_ID_88E2110, MARVELL_PHY_ID_MASK },
805 { },
806 };
807 MODULE_DEVICE_TABLE(mdio, mv3310_tbl);
808 MODULE_DESCRIPTION("Marvell Alaska X 10Gigabit Ethernet PHY driver (MV88X3310)");
809 MODULE_LICENSE("GPL");
810
