1 /*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include "en.h"
34 #include "en/port.h"
35 #include "en/xsk/pool.h"
36 #include "lib/clock.h"
37
mlx5e_ethtool_get_drvinfo(struct mlx5e_priv * priv,struct ethtool_drvinfo * drvinfo)38 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
39 struct ethtool_drvinfo *drvinfo)
40 {
41 struct mlx5_core_dev *mdev = priv->mdev;
42
43 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
44 strlcpy(drvinfo->version, DRIVER_VERSION,
45 sizeof(drvinfo->version));
46 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
47 "%d.%d.%04d (%.16s)",
48 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
49 mdev->board_id);
50 strlcpy(drvinfo->bus_info, dev_name(mdev->device),
51 sizeof(drvinfo->bus_info));
52 }
53
mlx5e_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)54 static void mlx5e_get_drvinfo(struct net_device *dev,
55 struct ethtool_drvinfo *drvinfo)
56 {
57 struct mlx5e_priv *priv = netdev_priv(dev);
58
59 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
60 }
61
62 struct ptys2ethtool_config {
63 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
64 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
65 };
66
67 static
68 struct ptys2ethtool_config ptys2legacy_ethtool_table[MLX5E_LINK_MODES_NUMBER];
69 static
70 struct ptys2ethtool_config ptys2ext_ethtool_table[MLX5E_EXT_LINK_MODES_NUMBER];
71
72 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, table, ...) \
73 ({ \
74 struct ptys2ethtool_config *cfg; \
75 const unsigned int modes[] = { __VA_ARGS__ }; \
76 unsigned int i, bit, idx; \
77 cfg = &ptys2##table##_ethtool_table[reg_]; \
78 bitmap_zero(cfg->supported, \
79 __ETHTOOL_LINK_MODE_MASK_NBITS); \
80 bitmap_zero(cfg->advertised, \
81 __ETHTOOL_LINK_MODE_MASK_NBITS); \
82 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
83 bit = modes[i] % 64; \
84 idx = modes[i] / 64; \
85 __set_bit(bit, &cfg->supported[idx]); \
86 __set_bit(bit, &cfg->advertised[idx]); \
87 } \
88 })
89
mlx5e_build_ptys2ethtool_map(void)90 void mlx5e_build_ptys2ethtool_map(void)
91 {
92 memset(ptys2legacy_ethtool_table, 0, sizeof(ptys2legacy_ethtool_table));
93 memset(ptys2ext_ethtool_table, 0, sizeof(ptys2ext_ethtool_table));
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, legacy,
95 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, legacy,
97 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, legacy,
99 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, legacy,
101 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, legacy,
103 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, legacy,
105 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, legacy,
107 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, legacy,
109 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, legacy,
111 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, legacy,
113 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, legacy,
115 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, legacy,
117 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, legacy,
119 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, legacy,
121 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, legacy,
123 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, legacy,
125 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, legacy,
127 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, legacy,
129 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, legacy,
131 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, legacy,
133 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, legacy,
135 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
136 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, legacy,
137 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
138 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, legacy,
139 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
140 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, legacy,
141 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
142 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, legacy,
143 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
144 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_SGMII_100M, ext,
145 ETHTOOL_LINK_MODE_100baseT_Full_BIT);
146 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_X_SGMII, ext,
147 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
148 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
149 ETHTOOL_LINK_MODE_1000baseX_Full_BIT);
150 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_5GBASE_R, ext,
151 ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
152 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_XFI_XAUI_1, ext,
153 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
154 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
155 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
156 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
157 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
158 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
159 ETHTOOL_LINK_MODE_10000baseER_Full_BIT);
160 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_XLAUI_4_XLPPI_4, ext,
161 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
162 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
163 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
164 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
165 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GAUI_1_25GBASE_CR_KR, ext,
166 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
167 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
168 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
169 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
170 ext,
171 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
172 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
173 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
174 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR, ext,
175 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
176 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
177 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
178 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
179 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT);
180 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_CAUI_4_100GBASE_CR4_KR4, ext,
181 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
182 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
183 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
184 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
185 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_2_100GBASE_CR2_KR2, ext,
186 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
187 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
188 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
189 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
190 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT);
191 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_4_200GBASE_CR4_KR4, ext,
192 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
193 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
194 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
195 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
196 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT);
197 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GAUI_1_100GBASE_CR_KR, ext,
198 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
199 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
200 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
201 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
202 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT);
203 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_2_200GBASE_CR2_KR2, ext,
204 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
205 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
206 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
207 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
208 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT);
209 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_4_400GBASE_CR4_KR4, ext,
210 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
211 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
212 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
213 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
214 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT);
215 }
216
mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev * mdev,struct ptys2ethtool_config ** arr,u32 * size)217 static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev,
218 struct ptys2ethtool_config **arr,
219 u32 *size)
220 {
221 bool ext = mlx5e_ptys_ext_supported(mdev);
222
223 *arr = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
224 *size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
225 ARRAY_SIZE(ptys2legacy_ethtool_table);
226 }
227
228 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
229
230 struct pflag_desc {
231 char name[ETH_GSTRING_LEN];
232 mlx5e_pflag_handler handler;
233 };
234
235 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS];
236
mlx5e_ethtool_get_sset_count(struct mlx5e_priv * priv,int sset)237 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
238 {
239 switch (sset) {
240 case ETH_SS_STATS:
241 return mlx5e_stats_total_num(priv);
242 case ETH_SS_PRIV_FLAGS:
243 return MLX5E_NUM_PFLAGS;
244 case ETH_SS_TEST:
245 return mlx5e_self_test_num(priv);
246 default:
247 return -EOPNOTSUPP;
248 }
249 }
250
mlx5e_get_sset_count(struct net_device * dev,int sset)251 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
252 {
253 struct mlx5e_priv *priv = netdev_priv(dev);
254
255 return mlx5e_ethtool_get_sset_count(priv, sset);
256 }
257
mlx5e_ethtool_get_strings(struct mlx5e_priv * priv,u32 stringset,u8 * data)258 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
259 {
260 int i;
261
262 switch (stringset) {
263 case ETH_SS_PRIV_FLAGS:
264 for (i = 0; i < MLX5E_NUM_PFLAGS; i++)
265 strcpy(data + i * ETH_GSTRING_LEN,
266 mlx5e_priv_flags[i].name);
267 break;
268
269 case ETH_SS_TEST:
270 for (i = 0; i < mlx5e_self_test_num(priv); i++)
271 strcpy(data + i * ETH_GSTRING_LEN,
272 mlx5e_self_tests[i]);
273 break;
274
275 case ETH_SS_STATS:
276 mlx5e_stats_fill_strings(priv, data);
277 break;
278 }
279 }
280
mlx5e_get_strings(struct net_device * dev,u32 stringset,u8 * data)281 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
282 {
283 struct mlx5e_priv *priv = netdev_priv(dev);
284
285 mlx5e_ethtool_get_strings(priv, stringset, data);
286 }
287
mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv * priv,struct ethtool_stats * stats,u64 * data)288 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
289 struct ethtool_stats *stats, u64 *data)
290 {
291 int idx = 0;
292
293 mutex_lock(&priv->state_lock);
294 mlx5e_stats_update(priv);
295 mutex_unlock(&priv->state_lock);
296
297 mlx5e_stats_fill(priv, data, idx);
298 }
299
mlx5e_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)300 static void mlx5e_get_ethtool_stats(struct net_device *dev,
301 struct ethtool_stats *stats,
302 u64 *data)
303 {
304 struct mlx5e_priv *priv = netdev_priv(dev);
305
306 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
307 }
308
mlx5e_ethtool_get_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param)309 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
310 struct ethtool_ringparam *param)
311 {
312 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
313 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
314 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
315 param->tx_pending = 1 << priv->channels.params.log_sq_size;
316 }
317
mlx5e_get_ringparam(struct net_device * dev,struct ethtool_ringparam * param)318 static void mlx5e_get_ringparam(struct net_device *dev,
319 struct ethtool_ringparam *param)
320 {
321 struct mlx5e_priv *priv = netdev_priv(dev);
322
323 mlx5e_ethtool_get_ringparam(priv, param);
324 }
325
mlx5e_ethtool_set_ringparam(struct mlx5e_priv * priv,struct ethtool_ringparam * param)326 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
327 struct ethtool_ringparam *param)
328 {
329 struct mlx5e_channels new_channels = {};
330 u8 log_rq_size;
331 u8 log_sq_size;
332 int err = 0;
333
334 if (param->rx_jumbo_pending) {
335 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
336 __func__);
337 return -EINVAL;
338 }
339 if (param->rx_mini_pending) {
340 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
341 __func__);
342 return -EINVAL;
343 }
344
345 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
346 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
347 __func__, param->rx_pending,
348 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
349 return -EINVAL;
350 }
351
352 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
353 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
354 __func__, param->tx_pending,
355 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
356 return -EINVAL;
357 }
358
359 log_rq_size = order_base_2(param->rx_pending);
360 log_sq_size = order_base_2(param->tx_pending);
361
362 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
363 log_sq_size == priv->channels.params.log_sq_size)
364 return 0;
365
366 mutex_lock(&priv->state_lock);
367
368 new_channels.params = priv->channels.params;
369 new_channels.params.log_rq_mtu_frames = log_rq_size;
370 new_channels.params.log_sq_size = log_sq_size;
371
372 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
373 priv->channels.params = new_channels.params;
374 goto unlock;
375 }
376
377 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
378
379 unlock:
380 mutex_unlock(&priv->state_lock);
381
382 return err;
383 }
384
mlx5e_set_ringparam(struct net_device * dev,struct ethtool_ringparam * param)385 static int mlx5e_set_ringparam(struct net_device *dev,
386 struct ethtool_ringparam *param)
387 {
388 struct mlx5e_priv *priv = netdev_priv(dev);
389
390 return mlx5e_ethtool_set_ringparam(priv, param);
391 }
392
mlx5e_ethtool_get_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)393 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
394 struct ethtool_channels *ch)
395 {
396 mutex_lock(&priv->state_lock);
397
398 ch->max_combined = priv->max_nch;
399 ch->combined_count = priv->channels.params.num_channels;
400 if (priv->xsk.refcnt) {
401 /* The upper half are XSK queues. */
402 ch->max_combined *= 2;
403 ch->combined_count *= 2;
404 }
405
406 mutex_unlock(&priv->state_lock);
407 }
408
mlx5e_get_channels(struct net_device * dev,struct ethtool_channels * ch)409 static void mlx5e_get_channels(struct net_device *dev,
410 struct ethtool_channels *ch)
411 {
412 struct mlx5e_priv *priv = netdev_priv(dev);
413
414 mlx5e_ethtool_get_channels(priv, ch);
415 }
416
mlx5e_ethtool_set_channels(struct mlx5e_priv * priv,struct ethtool_channels * ch)417 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
418 struct ethtool_channels *ch)
419 {
420 struct mlx5e_params *cur_params = &priv->channels.params;
421 unsigned int count = ch->combined_count;
422 struct mlx5e_channels new_channels = {};
423 bool arfs_enabled;
424 int err = 0;
425
426 if (!count) {
427 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
428 __func__);
429 return -EINVAL;
430 }
431
432 if (cur_params->num_channels == count)
433 return 0;
434
435 mutex_lock(&priv->state_lock);
436
437 /* Don't allow changing the number of channels if there is an active
438 * XSK, because the numeration of the XSK and regular RQs will change.
439 */
440 if (priv->xsk.refcnt) {
441 err = -EINVAL;
442 netdev_err(priv->netdev, "%s: AF_XDP is active, cannot change the number of channels\n",
443 __func__);
444 goto out;
445 }
446
447 new_channels.params = priv->channels.params;
448 new_channels.params.num_channels = count;
449
450 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
451 *cur_params = new_channels.params;
452 err = mlx5e_num_channels_changed(priv);
453 goto out;
454 }
455
456 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
457 if (arfs_enabled)
458 mlx5e_arfs_disable(priv);
459
460 /* Switch to new channels, set new parameters and close old ones */
461 err = mlx5e_safe_switch_channels(priv, &new_channels,
462 mlx5e_num_channels_changed_ctx, NULL);
463
464 if (arfs_enabled) {
465 int err2 = mlx5e_arfs_enable(priv);
466
467 if (err2)
468 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
469 __func__, err2);
470 }
471
472 out:
473 mutex_unlock(&priv->state_lock);
474
475 return err;
476 }
477
mlx5e_set_channels(struct net_device * dev,struct ethtool_channels * ch)478 static int mlx5e_set_channels(struct net_device *dev,
479 struct ethtool_channels *ch)
480 {
481 struct mlx5e_priv *priv = netdev_priv(dev);
482
483 return mlx5e_ethtool_set_channels(priv, ch);
484 }
485
mlx5e_ethtool_get_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)486 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
487 struct ethtool_coalesce *coal)
488 {
489 struct dim_cq_moder *rx_moder, *tx_moder;
490
491 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
492 return -EOPNOTSUPP;
493
494 rx_moder = &priv->channels.params.rx_cq_moderation;
495 coal->rx_coalesce_usecs = rx_moder->usec;
496 coal->rx_max_coalesced_frames = rx_moder->pkts;
497 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
498
499 tx_moder = &priv->channels.params.tx_cq_moderation;
500 coal->tx_coalesce_usecs = tx_moder->usec;
501 coal->tx_max_coalesced_frames = tx_moder->pkts;
502 coal->use_adaptive_tx_coalesce = priv->channels.params.tx_dim_enabled;
503
504 return 0;
505 }
506
mlx5e_get_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal)507 static int mlx5e_get_coalesce(struct net_device *netdev,
508 struct ethtool_coalesce *coal)
509 {
510 struct mlx5e_priv *priv = netdev_priv(netdev);
511
512 return mlx5e_ethtool_get_coalesce(priv, coal);
513 }
514
515 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
516 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
517
518 static void
mlx5e_set_priv_channels_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)519 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
520 {
521 struct mlx5_core_dev *mdev = priv->mdev;
522 int tc;
523 int i;
524
525 for (i = 0; i < priv->channels.num; ++i) {
526 struct mlx5e_channel *c = priv->channels.c[i];
527
528 for (tc = 0; tc < c->num_tc; tc++) {
529 mlx5_core_modify_cq_moderation(mdev,
530 &c->sq[tc].cq.mcq,
531 coal->tx_coalesce_usecs,
532 coal->tx_max_coalesced_frames);
533 }
534
535 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
536 coal->rx_coalesce_usecs,
537 coal->rx_max_coalesced_frames);
538 }
539 }
540
mlx5e_ethtool_set_coalesce(struct mlx5e_priv * priv,struct ethtool_coalesce * coal)541 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
542 struct ethtool_coalesce *coal)
543 {
544 struct dim_cq_moder *rx_moder, *tx_moder;
545 struct mlx5_core_dev *mdev = priv->mdev;
546 struct mlx5e_channels new_channels = {};
547 bool reset_rx, reset_tx;
548 int err = 0;
549
550 if (!MLX5_CAP_GEN(mdev, cq_moderation))
551 return -EOPNOTSUPP;
552
553 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
554 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
555 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
556 __func__, MLX5E_MAX_COAL_TIME);
557 return -ERANGE;
558 }
559
560 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
561 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
562 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
563 __func__, MLX5E_MAX_COAL_FRAMES);
564 return -ERANGE;
565 }
566
567 mutex_lock(&priv->state_lock);
568 new_channels.params = priv->channels.params;
569
570 rx_moder = &new_channels.params.rx_cq_moderation;
571 rx_moder->usec = coal->rx_coalesce_usecs;
572 rx_moder->pkts = coal->rx_max_coalesced_frames;
573 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
574
575 tx_moder = &new_channels.params.tx_cq_moderation;
576 tx_moder->usec = coal->tx_coalesce_usecs;
577 tx_moder->pkts = coal->tx_max_coalesced_frames;
578 new_channels.params.tx_dim_enabled = !!coal->use_adaptive_tx_coalesce;
579
580 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
581 priv->channels.params = new_channels.params;
582 goto out;
583 }
584 /* we are opened */
585
586 reset_rx = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled;
587 reset_tx = !!coal->use_adaptive_tx_coalesce != priv->channels.params.tx_dim_enabled;
588
589 if (!reset_rx && !reset_tx) {
590 mlx5e_set_priv_channels_coalesce(priv, coal);
591 priv->channels.params = new_channels.params;
592 goto out;
593 }
594
595 if (reset_rx) {
596 u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
597 MLX5E_PFLAG_RX_CQE_BASED_MODER);
598
599 mlx5e_reset_rx_moderation(&new_channels.params, mode);
600 }
601 if (reset_tx) {
602 u8 mode = MLX5E_GET_PFLAG(&new_channels.params,
603 MLX5E_PFLAG_TX_CQE_BASED_MODER);
604
605 mlx5e_reset_tx_moderation(&new_channels.params, mode);
606 }
607
608 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
609
610 out:
611 mutex_unlock(&priv->state_lock);
612 return err;
613 }
614
mlx5e_set_coalesce(struct net_device * netdev,struct ethtool_coalesce * coal)615 static int mlx5e_set_coalesce(struct net_device *netdev,
616 struct ethtool_coalesce *coal)
617 {
618 struct mlx5e_priv *priv = netdev_priv(netdev);
619
620 return mlx5e_ethtool_set_coalesce(priv, coal);
621 }
622
ptys2ethtool_supported_link(struct mlx5_core_dev * mdev,unsigned long * supported_modes,u32 eth_proto_cap)623 static void ptys2ethtool_supported_link(struct mlx5_core_dev *mdev,
624 unsigned long *supported_modes,
625 u32 eth_proto_cap)
626 {
627 unsigned long proto_cap = eth_proto_cap;
628 struct ptys2ethtool_config *table;
629 u32 max_size;
630 int proto;
631
632 mlx5e_ethtool_get_speed_arr(mdev, &table, &max_size);
633 for_each_set_bit(proto, &proto_cap, max_size)
634 bitmap_or(supported_modes, supported_modes,
635 table[proto].supported,
636 __ETHTOOL_LINK_MODE_MASK_NBITS);
637 }
638
ptys2ethtool_adver_link(unsigned long * advertising_modes,u32 eth_proto_cap,bool ext)639 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
640 u32 eth_proto_cap, bool ext)
641 {
642 unsigned long proto_cap = eth_proto_cap;
643 struct ptys2ethtool_config *table;
644 u32 max_size;
645 int proto;
646
647 table = ext ? ptys2ext_ethtool_table : ptys2legacy_ethtool_table;
648 max_size = ext ? ARRAY_SIZE(ptys2ext_ethtool_table) :
649 ARRAY_SIZE(ptys2legacy_ethtool_table);
650
651 for_each_set_bit(proto, &proto_cap, max_size)
652 bitmap_or(advertising_modes, advertising_modes,
653 table[proto].advertised,
654 __ETHTOOL_LINK_MODE_MASK_NBITS);
655 }
656
657 static const u32 pplm_fec_2_ethtool[] = {
658 [MLX5E_FEC_NOFEC] = ETHTOOL_FEC_OFF,
659 [MLX5E_FEC_FIRECODE] = ETHTOOL_FEC_BASER,
660 [MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,
661 [MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,
662 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,
663 };
664
pplm2ethtool_fec(u_long fec_mode,unsigned long size)665 static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)
666 {
667 int mode = 0;
668
669 if (!fec_mode)
670 return ETHTOOL_FEC_AUTO;
671
672 mode = find_first_bit(&fec_mode, size);
673
674 if (mode < ARRAY_SIZE(pplm_fec_2_ethtool))
675 return pplm_fec_2_ethtool[mode];
676
677 return 0;
678 }
679
680 #define MLX5E_ADVERTISE_SUPPORTED_FEC(mlx5_fec, ethtool_fec) \
681 do { \
682 if (mlx5e_fec_in_caps(dev, 1 << (mlx5_fec))) \
683 __set_bit(ethtool_fec, \
684 link_ksettings->link_modes.supported);\
685 } while (0)
686
687 static const u32 pplm_fec_2_ethtool_linkmodes[] = {
688 [MLX5E_FEC_NOFEC] = ETHTOOL_LINK_MODE_FEC_NONE_BIT,
689 [MLX5E_FEC_FIRECODE] = ETHTOOL_LINK_MODE_FEC_BASER_BIT,
690 [MLX5E_FEC_RS_528_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
691 [MLX5E_FEC_RS_544_514] = ETHTOOL_LINK_MODE_FEC_RS_BIT,
692 [MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_LINK_MODE_FEC_LLRS_BIT,
693 };
694
get_fec_supported_advertised(struct mlx5_core_dev * dev,struct ethtool_link_ksettings * link_ksettings)695 static int get_fec_supported_advertised(struct mlx5_core_dev *dev,
696 struct ethtool_link_ksettings *link_ksettings)
697 {
698 unsigned long active_fec_long;
699 u32 active_fec;
700 u32 bitn;
701 int err;
702
703 err = mlx5e_get_fec_mode(dev, &active_fec, NULL);
704 if (err)
705 return (err == -EOPNOTSUPP) ? 0 : err;
706
707 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_NOFEC,
708 ETHTOOL_LINK_MODE_FEC_NONE_BIT);
709 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_FIRECODE,
710 ETHTOOL_LINK_MODE_FEC_BASER_BIT);
711 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_RS_528_514,
712 ETHTOOL_LINK_MODE_FEC_RS_BIT);
713 MLX5E_ADVERTISE_SUPPORTED_FEC(MLX5E_FEC_LLRS_272_257_1,
714 ETHTOOL_LINK_MODE_FEC_LLRS_BIT);
715
716 active_fec_long = active_fec;
717 /* active fec is a bit set, find out which bit is set and
718 * advertise the corresponding ethtool bit
719 */
720 bitn = find_first_bit(&active_fec_long, sizeof(active_fec_long) * BITS_PER_BYTE);
721 if (bitn < ARRAY_SIZE(pplm_fec_2_ethtool_linkmodes))
722 __set_bit(pplm_fec_2_ethtool_linkmodes[bitn],
723 link_ksettings->link_modes.advertising);
724
725 return 0;
726 }
727
ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings * link_ksettings,u32 eth_proto_cap,u8 connector_type,bool ext)728 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
729 u32 eth_proto_cap,
730 u8 connector_type, bool ext)
731 {
732 if ((!connector_type && !ext) || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
733 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
734 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
735 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
736 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
737 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
738 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
739 ethtool_link_ksettings_add_link_mode(link_ksettings,
740 supported,
741 FIBRE);
742 ethtool_link_ksettings_add_link_mode(link_ksettings,
743 advertising,
744 FIBRE);
745 }
746
747 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
748 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
749 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
750 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
751 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
752 ethtool_link_ksettings_add_link_mode(link_ksettings,
753 supported,
754 Backplane);
755 ethtool_link_ksettings_add_link_mode(link_ksettings,
756 advertising,
757 Backplane);
758 }
759 return;
760 }
761
762 switch (connector_type) {
763 case MLX5E_PORT_TP:
764 ethtool_link_ksettings_add_link_mode(link_ksettings,
765 supported, TP);
766 ethtool_link_ksettings_add_link_mode(link_ksettings,
767 advertising, TP);
768 break;
769 case MLX5E_PORT_AUI:
770 ethtool_link_ksettings_add_link_mode(link_ksettings,
771 supported, AUI);
772 ethtool_link_ksettings_add_link_mode(link_ksettings,
773 advertising, AUI);
774 break;
775 case MLX5E_PORT_BNC:
776 ethtool_link_ksettings_add_link_mode(link_ksettings,
777 supported, BNC);
778 ethtool_link_ksettings_add_link_mode(link_ksettings,
779 advertising, BNC);
780 break;
781 case MLX5E_PORT_MII:
782 ethtool_link_ksettings_add_link_mode(link_ksettings,
783 supported, MII);
784 ethtool_link_ksettings_add_link_mode(link_ksettings,
785 advertising, MII);
786 break;
787 case MLX5E_PORT_FIBRE:
788 ethtool_link_ksettings_add_link_mode(link_ksettings,
789 supported, FIBRE);
790 ethtool_link_ksettings_add_link_mode(link_ksettings,
791 advertising, FIBRE);
792 break;
793 case MLX5E_PORT_DA:
794 ethtool_link_ksettings_add_link_mode(link_ksettings,
795 supported, Backplane);
796 ethtool_link_ksettings_add_link_mode(link_ksettings,
797 advertising, Backplane);
798 break;
799 case MLX5E_PORT_NONE:
800 case MLX5E_PORT_OTHER:
801 default:
802 break;
803 }
804 }
805
get_speed_duplex(struct net_device * netdev,u32 eth_proto_oper,bool force_legacy,u16 data_rate_oper,struct ethtool_link_ksettings * link_ksettings)806 static void get_speed_duplex(struct net_device *netdev,
807 u32 eth_proto_oper, bool force_legacy,
808 u16 data_rate_oper,
809 struct ethtool_link_ksettings *link_ksettings)
810 {
811 struct mlx5e_priv *priv = netdev_priv(netdev);
812 u32 speed = SPEED_UNKNOWN;
813 u8 duplex = DUPLEX_UNKNOWN;
814
815 if (!netif_carrier_ok(netdev))
816 goto out;
817
818 speed = mlx5e_port_ptys2speed(priv->mdev, eth_proto_oper, force_legacy);
819 if (!speed) {
820 if (data_rate_oper)
821 speed = 100 * data_rate_oper;
822 else
823 speed = SPEED_UNKNOWN;
824 goto out;
825 }
826
827 duplex = DUPLEX_FULL;
828
829 out:
830 link_ksettings->base.speed = speed;
831 link_ksettings->base.duplex = duplex;
832 }
833
get_supported(struct mlx5_core_dev * mdev,u32 eth_proto_cap,struct ethtool_link_ksettings * link_ksettings)834 static void get_supported(struct mlx5_core_dev *mdev, u32 eth_proto_cap,
835 struct ethtool_link_ksettings *link_ksettings)
836 {
837 unsigned long *supported = link_ksettings->link_modes.supported;
838 ptys2ethtool_supported_link(mdev, supported, eth_proto_cap);
839
840 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
841 }
842
get_advertising(u32 eth_proto_cap,u8 tx_pause,u8 rx_pause,struct ethtool_link_ksettings * link_ksettings,bool ext)843 static void get_advertising(u32 eth_proto_cap, u8 tx_pause, u8 rx_pause,
844 struct ethtool_link_ksettings *link_ksettings,
845 bool ext)
846 {
847 unsigned long *advertising = link_ksettings->link_modes.advertising;
848 ptys2ethtool_adver_link(advertising, eth_proto_cap, ext);
849
850 if (rx_pause)
851 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
852 if (tx_pause ^ rx_pause)
853 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
854 }
855
856 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
857 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
858 [MLX5E_PORT_NONE] = PORT_NONE,
859 [MLX5E_PORT_TP] = PORT_TP,
860 [MLX5E_PORT_AUI] = PORT_AUI,
861 [MLX5E_PORT_BNC] = PORT_BNC,
862 [MLX5E_PORT_MII] = PORT_MII,
863 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
864 [MLX5E_PORT_DA] = PORT_DA,
865 [MLX5E_PORT_OTHER] = PORT_OTHER,
866 };
867
get_connector_port(u32 eth_proto,u8 connector_type,bool ext)868 static u8 get_connector_port(u32 eth_proto, u8 connector_type, bool ext)
869 {
870 if ((connector_type || ext) && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
871 return ptys2connector_type[connector_type];
872
873 if (eth_proto &
874 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
875 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
876 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
877 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
878 return PORT_FIBRE;
879 }
880
881 if (eth_proto &
882 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
883 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
884 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
885 return PORT_DA;
886 }
887
888 if (eth_proto &
889 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
890 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
891 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
892 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
893 return PORT_NONE;
894 }
895
896 return PORT_OTHER;
897 }
898
get_lp_advertising(struct mlx5_core_dev * mdev,u32 eth_proto_lp,struct ethtool_link_ksettings * link_ksettings)899 static void get_lp_advertising(struct mlx5_core_dev *mdev, u32 eth_proto_lp,
900 struct ethtool_link_ksettings *link_ksettings)
901 {
902 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
903 bool ext = mlx5e_ptys_ext_supported(mdev);
904
905 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp, ext);
906 }
907
mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv * priv,struct ethtool_link_ksettings * link_ksettings)908 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
909 struct ethtool_link_ksettings *link_ksettings)
910 {
911 struct mlx5_core_dev *mdev = priv->mdev;
912 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
913 u32 eth_proto_admin;
914 u8 an_disable_admin;
915 u16 data_rate_oper;
916 u32 eth_proto_oper;
917 u32 eth_proto_cap;
918 u8 connector_type;
919 u32 rx_pause = 0;
920 u32 tx_pause = 0;
921 u32 eth_proto_lp;
922 bool admin_ext;
923 u8 an_status;
924 bool ext;
925 int err;
926
927 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
928 if (err) {
929 netdev_err(priv->netdev, "%s: query port ptys failed: %d\n",
930 __func__, err);
931 goto err_query_regs;
932 }
933 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
934 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
935 eth_proto_capability);
936 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
937 eth_proto_admin);
938 /* Fields: eth_proto_admin and ext_eth_proto_admin are
939 * mutually exclusive. Hence try reading legacy advertising
940 * when extended advertising is zero.
941 * admin_ext indicates which proto_admin (ext vs. legacy)
942 * should be read and interpreted
943 */
944 admin_ext = ext;
945 if (ext && !eth_proto_admin) {
946 eth_proto_admin = MLX5_GET_ETH_PROTO(ptys_reg, out, false,
947 eth_proto_admin);
948 admin_ext = false;
949 }
950
951 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, admin_ext,
952 eth_proto_oper);
953 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
954 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
955 an_status = MLX5_GET(ptys_reg, out, an_status);
956 connector_type = MLX5_GET(ptys_reg, out, connector_type);
957 data_rate_oper = MLX5_GET(ptys_reg, out, data_rate_oper);
958
959 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
960
961 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
962 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
963
964 get_supported(mdev, eth_proto_cap, link_ksettings);
965 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings,
966 admin_ext);
967 get_speed_duplex(priv->netdev, eth_proto_oper, !admin_ext,
968 data_rate_oper, link_ksettings);
969
970 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
971
972 link_ksettings->base.port = get_connector_port(eth_proto_oper,
973 connector_type, ext);
974 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
975 connector_type, ext);
976 get_lp_advertising(mdev, eth_proto_lp, link_ksettings);
977
978 if (an_status == MLX5_AN_COMPLETE)
979 ethtool_link_ksettings_add_link_mode(link_ksettings,
980 lp_advertising, Autoneg);
981
982 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
983 AUTONEG_ENABLE;
984 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
985 Autoneg);
986
987 err = get_fec_supported_advertised(mdev, link_ksettings);
988 if (err) {
989 netdev_dbg(priv->netdev, "%s: FEC caps query failed: %d\n",
990 __func__, err);
991 err = 0; /* don't fail caps query because of FEC error */
992 }
993
994 if (!an_disable_admin)
995 ethtool_link_ksettings_add_link_mode(link_ksettings,
996 advertising, Autoneg);
997
998 err_query_regs:
999 return err;
1000 }
1001
mlx5e_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * link_ksettings)1002 static int mlx5e_get_link_ksettings(struct net_device *netdev,
1003 struct ethtool_link_ksettings *link_ksettings)
1004 {
1005 struct mlx5e_priv *priv = netdev_priv(netdev);
1006
1007 return mlx5e_ethtool_get_link_ksettings(priv, link_ksettings);
1008 }
1009
mlx5e_ethtool2ptys_adver_link(const unsigned long * link_modes)1010 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
1011 {
1012 u32 i, ptys_modes = 0;
1013
1014 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1015 if (*ptys2legacy_ethtool_table[i].advertised == 0)
1016 continue;
1017 if (bitmap_intersects(ptys2legacy_ethtool_table[i].advertised,
1018 link_modes,
1019 __ETHTOOL_LINK_MODE_MASK_NBITS))
1020 ptys_modes |= MLX5E_PROT_MASK(i);
1021 }
1022
1023 return ptys_modes;
1024 }
1025
mlx5e_ethtool2ptys_ext_adver_link(const unsigned long * link_modes)1026 static u32 mlx5e_ethtool2ptys_ext_adver_link(const unsigned long *link_modes)
1027 {
1028 u32 i, ptys_modes = 0;
1029 unsigned long modes[2];
1030
1031 for (i = 0; i < MLX5E_EXT_LINK_MODES_NUMBER; ++i) {
1032 if (ptys2ext_ethtool_table[i].advertised[0] == 0 &&
1033 ptys2ext_ethtool_table[i].advertised[1] == 0)
1034 continue;
1035 memset(modes, 0, sizeof(modes));
1036 bitmap_and(modes, ptys2ext_ethtool_table[i].advertised,
1037 link_modes, __ETHTOOL_LINK_MODE_MASK_NBITS);
1038
1039 if (modes[0] == ptys2ext_ethtool_table[i].advertised[0] &&
1040 modes[1] == ptys2ext_ethtool_table[i].advertised[1])
1041 ptys_modes |= MLX5E_PROT_MASK(i);
1042 }
1043 return ptys_modes;
1044 }
1045
ext_link_mode_requested(const unsigned long * adver)1046 static bool ext_link_mode_requested(const unsigned long *adver)
1047 {
1048 #define MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT ETHTOOL_LINK_MODE_50000baseKR_Full_BIT
1049 int size = __ETHTOOL_LINK_MODE_MASK_NBITS - MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT;
1050 __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = {0,};
1051
1052 bitmap_set(modes, MLX5E_MIN_PTYS_EXT_LINK_MODE_BIT, size);
1053 return bitmap_intersects(modes, adver, __ETHTOOL_LINK_MODE_MASK_NBITS);
1054 }
1055
ext_requested(u8 autoneg,const unsigned long * adver,bool ext_supported)1056 static bool ext_requested(u8 autoneg, const unsigned long *adver, bool ext_supported)
1057 {
1058 bool ext_link_mode = ext_link_mode_requested(adver);
1059
1060 return autoneg == AUTONEG_ENABLE ? ext_link_mode : ext_supported;
1061 }
1062
mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv * priv,const struct ethtool_link_ksettings * link_ksettings)1063 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1064 const struct ethtool_link_ksettings *link_ksettings)
1065 {
1066 struct mlx5_core_dev *mdev = priv->mdev;
1067 struct mlx5e_port_eth_proto eproto;
1068 const unsigned long *adver;
1069 bool an_changes = false;
1070 u8 an_disable_admin;
1071 bool ext_supported;
1072 u8 an_disable_cap;
1073 bool an_disable;
1074 u32 link_modes;
1075 u8 an_status;
1076 u8 autoneg;
1077 u32 speed;
1078 bool ext;
1079 int err;
1080
1081 u32 (*ethtool2ptys_adver_func)(const unsigned long *adver);
1082
1083 adver = link_ksettings->link_modes.advertising;
1084 autoneg = link_ksettings->base.autoneg;
1085 speed = link_ksettings->base.speed;
1086
1087 ext_supported = mlx5e_ptys_ext_supported(mdev);
1088 ext = ext_requested(autoneg, adver, ext_supported);
1089 if (!ext_supported && ext)
1090 return -EOPNOTSUPP;
1091
1092 ethtool2ptys_adver_func = ext ? mlx5e_ethtool2ptys_ext_adver_link :
1093 mlx5e_ethtool2ptys_adver_link;
1094 err = mlx5_port_query_eth_proto(mdev, 1, ext, &eproto);
1095 if (err) {
1096 netdev_err(priv->netdev, "%s: query port eth proto failed: %d\n",
1097 __func__, err);
1098 goto out;
1099 }
1100 link_modes = autoneg == AUTONEG_ENABLE ? ethtool2ptys_adver_func(adver) :
1101 mlx5e_port_speed2linkmodes(mdev, speed, !ext);
1102
1103 if ((link_modes & MLX5E_PROT_MASK(MLX5E_56GBASE_R4)) &&
1104 autoneg != AUTONEG_ENABLE) {
1105 netdev_err(priv->netdev, "%s: 56G link speed requires autoneg enabled\n",
1106 __func__);
1107 err = -EINVAL;
1108 goto out;
1109 }
1110
1111 link_modes = link_modes & eproto.cap;
1112 if (!link_modes) {
1113 netdev_err(priv->netdev, "%s: Not supported link mode(s) requested",
1114 __func__);
1115 err = -EINVAL;
1116 goto out;
1117 }
1118
1119 mlx5_port_query_eth_autoneg(mdev, &an_status, &an_disable_cap,
1120 &an_disable_admin);
1121
1122 an_disable = autoneg == AUTONEG_DISABLE;
1123 an_changes = ((!an_disable && an_disable_admin) ||
1124 (an_disable && !an_disable_admin));
1125
1126 if (!an_changes && link_modes == eproto.admin)
1127 goto out;
1128
1129 mlx5_port_set_eth_ptys(mdev, an_disable, link_modes, ext);
1130 mlx5_toggle_port_link(mdev);
1131
1132 out:
1133 return err;
1134 }
1135
mlx5e_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * link_ksettings)1136 static int mlx5e_set_link_ksettings(struct net_device *netdev,
1137 const struct ethtool_link_ksettings *link_ksettings)
1138 {
1139 struct mlx5e_priv *priv = netdev_priv(netdev);
1140
1141 return mlx5e_ethtool_set_link_ksettings(priv, link_ksettings);
1142 }
1143
mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv * priv)1144 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv)
1145 {
1146 return sizeof(priv->rss_params.toeplitz_hash_key);
1147 }
1148
mlx5e_get_rxfh_key_size(struct net_device * netdev)1149 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1150 {
1151 struct mlx5e_priv *priv = netdev_priv(netdev);
1152
1153 return mlx5e_ethtool_get_rxfh_key_size(priv);
1154 }
1155
mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv * priv)1156 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv)
1157 {
1158 return MLX5E_INDIR_RQT_SIZE;
1159 }
1160
mlx5e_get_rxfh_indir_size(struct net_device * netdev)1161 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1162 {
1163 struct mlx5e_priv *priv = netdev_priv(netdev);
1164
1165 return mlx5e_ethtool_get_rxfh_indir_size(priv);
1166 }
1167
mlx5e_get_rxfh(struct net_device * netdev,u32 * indir,u8 * key,u8 * hfunc)1168 int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1169 u8 *hfunc)
1170 {
1171 struct mlx5e_priv *priv = netdev_priv(netdev);
1172 struct mlx5e_rss_params *rss = &priv->rss_params;
1173
1174 if (indir)
1175 memcpy(indir, rss->indirection_rqt,
1176 sizeof(rss->indirection_rqt));
1177
1178 if (key)
1179 memcpy(key, rss->toeplitz_hash_key,
1180 sizeof(rss->toeplitz_hash_key));
1181
1182 if (hfunc)
1183 *hfunc = rss->hfunc;
1184
1185 return 0;
1186 }
1187
mlx5e_set_rxfh(struct net_device * dev,const u32 * indir,const u8 * key,const u8 hfunc)1188 int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
1189 const u8 *key, const u8 hfunc)
1190 {
1191 struct mlx5e_priv *priv = netdev_priv(dev);
1192 struct mlx5e_rss_params *rss = &priv->rss_params;
1193 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1194 bool refresh_tirs = false;
1195 bool refresh_rqt = false;
1196 void *in;
1197
1198 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1199 (hfunc != ETH_RSS_HASH_XOR) &&
1200 (hfunc != ETH_RSS_HASH_TOP))
1201 return -EINVAL;
1202
1203 in = kvzalloc(inlen, GFP_KERNEL);
1204 if (!in)
1205 return -ENOMEM;
1206
1207 mutex_lock(&priv->state_lock);
1208
1209 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != rss->hfunc) {
1210 rss->hfunc = hfunc;
1211 refresh_rqt = true;
1212 refresh_tirs = true;
1213 }
1214
1215 if (indir) {
1216 memcpy(rss->indirection_rqt, indir,
1217 sizeof(rss->indirection_rqt));
1218 refresh_rqt = true;
1219 }
1220
1221 if (key) {
1222 memcpy(rss->toeplitz_hash_key, key,
1223 sizeof(rss->toeplitz_hash_key));
1224 refresh_tirs = refresh_tirs || rss->hfunc == ETH_RSS_HASH_TOP;
1225 }
1226
1227 if (refresh_rqt && test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1228 struct mlx5e_redirect_rqt_param rrp = {
1229 .is_rss = true,
1230 {
1231 .rss = {
1232 .hfunc = rss->hfunc,
1233 .channels = &priv->channels,
1234 },
1235 },
1236 };
1237 u32 rqtn = priv->indir_rqt.rqtn;
1238
1239 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1240 }
1241
1242 if (refresh_tirs)
1243 mlx5e_modify_tirs_hash(priv, in);
1244
1245 mutex_unlock(&priv->state_lock);
1246
1247 kvfree(in);
1248
1249 return 0;
1250 }
1251
1252 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1253 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1254 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1255 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1256 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1257 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1258 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1259
mlx5e_get_pfc_prevention_tout(struct net_device * netdev,u16 * pfc_prevention_tout)1260 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1261 u16 *pfc_prevention_tout)
1262 {
1263 struct mlx5e_priv *priv = netdev_priv(netdev);
1264 struct mlx5_core_dev *mdev = priv->mdev;
1265
1266 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1267 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1268 return -EOPNOTSUPP;
1269
1270 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1271 }
1272
mlx5e_set_pfc_prevention_tout(struct net_device * netdev,u16 pfc_preven)1273 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1274 u16 pfc_preven)
1275 {
1276 struct mlx5e_priv *priv = netdev_priv(netdev);
1277 struct mlx5_core_dev *mdev = priv->mdev;
1278 u16 critical_tout;
1279 u16 minor;
1280
1281 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1282 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1283 return -EOPNOTSUPP;
1284
1285 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1286 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1287 pfc_preven;
1288
1289 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1290 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1291 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1292 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1293 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1294 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1295 return -EINVAL;
1296 }
1297
1298 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1299 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1300 minor);
1301 }
1302
mlx5e_get_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,void * data)1303 static int mlx5e_get_tunable(struct net_device *dev,
1304 const struct ethtool_tunable *tuna,
1305 void *data)
1306 {
1307 int err;
1308
1309 switch (tuna->id) {
1310 case ETHTOOL_PFC_PREVENTION_TOUT:
1311 err = mlx5e_get_pfc_prevention_tout(dev, data);
1312 break;
1313 default:
1314 err = -EINVAL;
1315 break;
1316 }
1317
1318 return err;
1319 }
1320
mlx5e_set_tunable(struct net_device * dev,const struct ethtool_tunable * tuna,const void * data)1321 static int mlx5e_set_tunable(struct net_device *dev,
1322 const struct ethtool_tunable *tuna,
1323 const void *data)
1324 {
1325 struct mlx5e_priv *priv = netdev_priv(dev);
1326 int err;
1327
1328 mutex_lock(&priv->state_lock);
1329
1330 switch (tuna->id) {
1331 case ETHTOOL_PFC_PREVENTION_TOUT:
1332 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1333 break;
1334 default:
1335 err = -EINVAL;
1336 break;
1337 }
1338
1339 mutex_unlock(&priv->state_lock);
1340 return err;
1341 }
1342
mlx5e_get_pause_stats(struct net_device * netdev,struct ethtool_pause_stats * pause_stats)1343 static void mlx5e_get_pause_stats(struct net_device *netdev,
1344 struct ethtool_pause_stats *pause_stats)
1345 {
1346 struct mlx5e_priv *priv = netdev_priv(netdev);
1347
1348 mlx5e_stats_pause_get(priv, pause_stats);
1349 }
1350
mlx5e_ethtool_get_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1351 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1352 struct ethtool_pauseparam *pauseparam)
1353 {
1354 struct mlx5_core_dev *mdev = priv->mdev;
1355 int err;
1356
1357 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1358 &pauseparam->tx_pause);
1359 if (err) {
1360 netdev_err(priv->netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1361 __func__, err);
1362 }
1363 }
1364
mlx5e_get_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1365 static void mlx5e_get_pauseparam(struct net_device *netdev,
1366 struct ethtool_pauseparam *pauseparam)
1367 {
1368 struct mlx5e_priv *priv = netdev_priv(netdev);
1369
1370 mlx5e_ethtool_get_pauseparam(priv, pauseparam);
1371 }
1372
mlx5e_ethtool_set_pauseparam(struct mlx5e_priv * priv,struct ethtool_pauseparam * pauseparam)1373 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1374 struct ethtool_pauseparam *pauseparam)
1375 {
1376 struct mlx5_core_dev *mdev = priv->mdev;
1377 int err;
1378
1379 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
1380 return -EOPNOTSUPP;
1381
1382 if (pauseparam->autoneg)
1383 return -EINVAL;
1384
1385 err = mlx5_set_port_pause(mdev,
1386 pauseparam->rx_pause ? 1 : 0,
1387 pauseparam->tx_pause ? 1 : 0);
1388 if (err) {
1389 netdev_err(priv->netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1390 __func__, err);
1391 }
1392
1393 return err;
1394 }
1395
mlx5e_set_pauseparam(struct net_device * netdev,struct ethtool_pauseparam * pauseparam)1396 static int mlx5e_set_pauseparam(struct net_device *netdev,
1397 struct ethtool_pauseparam *pauseparam)
1398 {
1399 struct mlx5e_priv *priv = netdev_priv(netdev);
1400
1401 return mlx5e_ethtool_set_pauseparam(priv, pauseparam);
1402 }
1403
mlx5e_ethtool_get_ts_info(struct mlx5e_priv * priv,struct ethtool_ts_info * info)1404 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1405 struct ethtool_ts_info *info)
1406 {
1407 struct mlx5_core_dev *mdev = priv->mdev;
1408
1409 info->phc_index = mlx5_clock_get_ptp_index(mdev);
1410
1411 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
1412 info->phc_index == -1)
1413 return 0;
1414
1415 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
1416 SOF_TIMESTAMPING_RX_HARDWARE |
1417 SOF_TIMESTAMPING_RAW_HARDWARE;
1418
1419 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1420 BIT(HWTSTAMP_TX_ON);
1421
1422 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1423 BIT(HWTSTAMP_FILTER_ALL);
1424
1425 return 0;
1426 }
1427
mlx5e_get_ts_info(struct net_device * dev,struct ethtool_ts_info * info)1428 static int mlx5e_get_ts_info(struct net_device *dev,
1429 struct ethtool_ts_info *info)
1430 {
1431 struct mlx5e_priv *priv = netdev_priv(dev);
1432
1433 return mlx5e_ethtool_get_ts_info(priv, info);
1434 }
1435
mlx5e_get_wol_supported(struct mlx5_core_dev * mdev)1436 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1437 {
1438 __u32 ret = 0;
1439
1440 if (MLX5_CAP_GEN(mdev, wol_g))
1441 ret |= WAKE_MAGIC;
1442
1443 if (MLX5_CAP_GEN(mdev, wol_s))
1444 ret |= WAKE_MAGICSECURE;
1445
1446 if (MLX5_CAP_GEN(mdev, wol_a))
1447 ret |= WAKE_ARP;
1448
1449 if (MLX5_CAP_GEN(mdev, wol_b))
1450 ret |= WAKE_BCAST;
1451
1452 if (MLX5_CAP_GEN(mdev, wol_m))
1453 ret |= WAKE_MCAST;
1454
1455 if (MLX5_CAP_GEN(mdev, wol_u))
1456 ret |= WAKE_UCAST;
1457
1458 if (MLX5_CAP_GEN(mdev, wol_p))
1459 ret |= WAKE_PHY;
1460
1461 return ret;
1462 }
1463
mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)1464 static __u32 mlx5e_reformat_wol_mode_mlx5_to_linux(u8 mode)
1465 {
1466 __u32 ret = 0;
1467
1468 if (mode & MLX5_WOL_MAGIC)
1469 ret |= WAKE_MAGIC;
1470
1471 if (mode & MLX5_WOL_SECURED_MAGIC)
1472 ret |= WAKE_MAGICSECURE;
1473
1474 if (mode & MLX5_WOL_ARP)
1475 ret |= WAKE_ARP;
1476
1477 if (mode & MLX5_WOL_BROADCAST)
1478 ret |= WAKE_BCAST;
1479
1480 if (mode & MLX5_WOL_MULTICAST)
1481 ret |= WAKE_MCAST;
1482
1483 if (mode & MLX5_WOL_UNICAST)
1484 ret |= WAKE_UCAST;
1485
1486 if (mode & MLX5_WOL_PHY_ACTIVITY)
1487 ret |= WAKE_PHY;
1488
1489 return ret;
1490 }
1491
mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)1492 static u8 mlx5e_reformat_wol_mode_linux_to_mlx5(__u32 mode)
1493 {
1494 u8 ret = 0;
1495
1496 if (mode & WAKE_MAGIC)
1497 ret |= MLX5_WOL_MAGIC;
1498
1499 if (mode & WAKE_MAGICSECURE)
1500 ret |= MLX5_WOL_SECURED_MAGIC;
1501
1502 if (mode & WAKE_ARP)
1503 ret |= MLX5_WOL_ARP;
1504
1505 if (mode & WAKE_BCAST)
1506 ret |= MLX5_WOL_BROADCAST;
1507
1508 if (mode & WAKE_MCAST)
1509 ret |= MLX5_WOL_MULTICAST;
1510
1511 if (mode & WAKE_UCAST)
1512 ret |= MLX5_WOL_UNICAST;
1513
1514 if (mode & WAKE_PHY)
1515 ret |= MLX5_WOL_PHY_ACTIVITY;
1516
1517 return ret;
1518 }
1519
mlx5e_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1520 static void mlx5e_get_wol(struct net_device *netdev,
1521 struct ethtool_wolinfo *wol)
1522 {
1523 struct mlx5e_priv *priv = netdev_priv(netdev);
1524 struct mlx5_core_dev *mdev = priv->mdev;
1525 u8 mlx5_wol_mode;
1526 int err;
1527
1528 memset(wol, 0, sizeof(*wol));
1529
1530 wol->supported = mlx5e_get_wol_supported(mdev);
1531 if (!wol->supported)
1532 return;
1533
1534 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1535 if (err)
1536 return;
1537
1538 wol->wolopts = mlx5e_reformat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1539 }
1540
mlx5e_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)1541 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1542 {
1543 struct mlx5e_priv *priv = netdev_priv(netdev);
1544 struct mlx5_core_dev *mdev = priv->mdev;
1545 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1546 u32 mlx5_wol_mode;
1547
1548 if (!wol_supported)
1549 return -EOPNOTSUPP;
1550
1551 if (wol->wolopts & ~wol_supported)
1552 return -EINVAL;
1553
1554 mlx5_wol_mode = mlx5e_reformat_wol_mode_linux_to_mlx5(wol->wolopts);
1555
1556 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1557 }
1558
mlx5e_get_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1559 static int mlx5e_get_fecparam(struct net_device *netdev,
1560 struct ethtool_fecparam *fecparam)
1561 {
1562 struct mlx5e_priv *priv = netdev_priv(netdev);
1563 struct mlx5_core_dev *mdev = priv->mdev;
1564 u16 fec_configured;
1565 u32 fec_active;
1566 int err;
1567
1568 err = mlx5e_get_fec_mode(mdev, &fec_active, &fec_configured);
1569
1570 if (err)
1571 return err;
1572
1573 fecparam->active_fec = pplm2ethtool_fec((unsigned long)fec_active,
1574 sizeof(unsigned long) * BITS_PER_BYTE);
1575
1576 if (!fecparam->active_fec)
1577 return -EOPNOTSUPP;
1578
1579 fecparam->fec = pplm2ethtool_fec((unsigned long)fec_configured,
1580 sizeof(unsigned long) * BITS_PER_BYTE);
1581
1582 return 0;
1583 }
1584
mlx5e_set_fecparam(struct net_device * netdev,struct ethtool_fecparam * fecparam)1585 static int mlx5e_set_fecparam(struct net_device *netdev,
1586 struct ethtool_fecparam *fecparam)
1587 {
1588 struct mlx5e_priv *priv = netdev_priv(netdev);
1589 struct mlx5_core_dev *mdev = priv->mdev;
1590 u16 fec_policy = 0;
1591 int mode;
1592 int err;
1593
1594 if (bitmap_weight((unsigned long *)&fecparam->fec,
1595 ETHTOOL_FEC_LLRS_BIT + 1) > 1)
1596 return -EOPNOTSUPP;
1597
1598 for (mode = 0; mode < ARRAY_SIZE(pplm_fec_2_ethtool); mode++) {
1599 if (!(pplm_fec_2_ethtool[mode] & fecparam->fec))
1600 continue;
1601 fec_policy |= (1 << mode);
1602 break;
1603 }
1604
1605 err = mlx5e_set_fec_mode(mdev, fec_policy);
1606
1607 if (err)
1608 return err;
1609
1610 mlx5_toggle_port_link(mdev);
1611
1612 return 0;
1613 }
1614
mlx5e_get_msglevel(struct net_device * dev)1615 static u32 mlx5e_get_msglevel(struct net_device *dev)
1616 {
1617 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1618 }
1619
mlx5e_set_msglevel(struct net_device * dev,u32 val)1620 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1621 {
1622 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1623 }
1624
mlx5e_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)1625 static int mlx5e_set_phys_id(struct net_device *dev,
1626 enum ethtool_phys_id_state state)
1627 {
1628 struct mlx5e_priv *priv = netdev_priv(dev);
1629 struct mlx5_core_dev *mdev = priv->mdev;
1630 u16 beacon_duration;
1631
1632 if (!MLX5_CAP_GEN(mdev, beacon_led))
1633 return -EOPNOTSUPP;
1634
1635 switch (state) {
1636 case ETHTOOL_ID_ACTIVE:
1637 beacon_duration = MLX5_BEACON_DURATION_INF;
1638 break;
1639 case ETHTOOL_ID_INACTIVE:
1640 beacon_duration = MLX5_BEACON_DURATION_OFF;
1641 break;
1642 default:
1643 return -EOPNOTSUPP;
1644 }
1645
1646 return mlx5_set_port_beacon(mdev, beacon_duration);
1647 }
1648
mlx5e_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)1649 static int mlx5e_get_module_info(struct net_device *netdev,
1650 struct ethtool_modinfo *modinfo)
1651 {
1652 struct mlx5e_priv *priv = netdev_priv(netdev);
1653 struct mlx5_core_dev *dev = priv->mdev;
1654 int size_read = 0;
1655 u8 data[4] = {0};
1656
1657 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1658 if (size_read < 2)
1659 return -EIO;
1660
1661 /* data[0] = identifier byte */
1662 switch (data[0]) {
1663 case MLX5_MODULE_ID_QSFP:
1664 modinfo->type = ETH_MODULE_SFF_8436;
1665 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1666 break;
1667 case MLX5_MODULE_ID_QSFP_PLUS:
1668 case MLX5_MODULE_ID_QSFP28:
1669 /* data[1] = revision id */
1670 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1671 modinfo->type = ETH_MODULE_SFF_8636;
1672 modinfo->eeprom_len = ETH_MODULE_SFF_8636_MAX_LEN;
1673 } else {
1674 modinfo->type = ETH_MODULE_SFF_8436;
1675 modinfo->eeprom_len = ETH_MODULE_SFF_8436_MAX_LEN;
1676 }
1677 break;
1678 case MLX5_MODULE_ID_SFP:
1679 modinfo->type = ETH_MODULE_SFF_8472;
1680 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1681 break;
1682 default:
1683 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1684 __func__, data[0]);
1685 return -EINVAL;
1686 }
1687
1688 return 0;
1689 }
1690
mlx5e_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)1691 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1692 struct ethtool_eeprom *ee,
1693 u8 *data)
1694 {
1695 struct mlx5e_priv *priv = netdev_priv(netdev);
1696 struct mlx5_core_dev *mdev = priv->mdev;
1697 int offset = ee->offset;
1698 int size_read;
1699 int i = 0;
1700
1701 if (!ee->len)
1702 return -EINVAL;
1703
1704 memset(data, 0, ee->len);
1705
1706 while (i < ee->len) {
1707 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1708 data + i);
1709
1710 if (!size_read)
1711 /* Done reading */
1712 return 0;
1713
1714 if (size_read < 0) {
1715 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1716 __func__, size_read);
1717 return 0;
1718 }
1719
1720 i += size_read;
1721 offset += size_read;
1722 }
1723
1724 return 0;
1725 }
1726
mlx5e_ethtool_flash_device(struct mlx5e_priv * priv,struct ethtool_flash * flash)1727 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1728 struct ethtool_flash *flash)
1729 {
1730 struct mlx5_core_dev *mdev = priv->mdev;
1731 struct net_device *dev = priv->netdev;
1732 const struct firmware *fw;
1733 int err;
1734
1735 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1736 return -EOPNOTSUPP;
1737
1738 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1739 if (err)
1740 return err;
1741
1742 dev_hold(dev);
1743 rtnl_unlock();
1744
1745 err = mlx5_firmware_flash(mdev, fw, NULL);
1746 release_firmware(fw);
1747
1748 rtnl_lock();
1749 dev_put(dev);
1750 return err;
1751 }
1752
mlx5e_flash_device(struct net_device * dev,struct ethtool_flash * flash)1753 static int mlx5e_flash_device(struct net_device *dev,
1754 struct ethtool_flash *flash)
1755 {
1756 struct mlx5e_priv *priv = netdev_priv(dev);
1757
1758 return mlx5e_ethtool_flash_device(priv, flash);
1759 }
1760
set_pflag_cqe_based_moder(struct net_device * netdev,bool enable,bool is_rx_cq)1761 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1762 bool is_rx_cq)
1763 {
1764 struct mlx5e_priv *priv = netdev_priv(netdev);
1765 struct mlx5_core_dev *mdev = priv->mdev;
1766 struct mlx5e_channels new_channels = {};
1767 bool mode_changed;
1768 u8 cq_period_mode, current_cq_period_mode;
1769
1770 cq_period_mode = enable ?
1771 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1772 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1773 current_cq_period_mode = is_rx_cq ?
1774 priv->channels.params.rx_cq_moderation.cq_period_mode :
1775 priv->channels.params.tx_cq_moderation.cq_period_mode;
1776 mode_changed = cq_period_mode != current_cq_period_mode;
1777
1778 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1779 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1780 return -EOPNOTSUPP;
1781
1782 if (!mode_changed)
1783 return 0;
1784
1785 new_channels.params = priv->channels.params;
1786 if (is_rx_cq)
1787 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1788 else
1789 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1790
1791 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1792 priv->channels.params = new_channels.params;
1793 return 0;
1794 }
1795
1796 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1797 }
1798
set_pflag_tx_cqe_based_moder(struct net_device * netdev,bool enable)1799 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1800 {
1801 return set_pflag_cqe_based_moder(netdev, enable, false);
1802 }
1803
set_pflag_rx_cqe_based_moder(struct net_device * netdev,bool enable)1804 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1805 {
1806 return set_pflag_cqe_based_moder(netdev, enable, true);
1807 }
1808
mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv * priv,bool new_val)1809 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1810 {
1811 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1812 struct mlx5e_channels new_channels = {};
1813 int err = 0;
1814
1815 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1816 return new_val ? -EOPNOTSUPP : 0;
1817
1818 if (curr_val == new_val)
1819 return 0;
1820
1821 new_channels.params = priv->channels.params;
1822 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1823
1824 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1825 priv->channels.params = new_channels.params;
1826 return 0;
1827 }
1828
1829 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1830 if (err)
1831 return err;
1832
1833 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1834 MLX5E_GET_PFLAG(&priv->channels.params,
1835 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1836
1837 return 0;
1838 }
1839
set_pflag_rx_cqe_compress(struct net_device * netdev,bool enable)1840 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1841 bool enable)
1842 {
1843 struct mlx5e_priv *priv = netdev_priv(netdev);
1844 struct mlx5_core_dev *mdev = priv->mdev;
1845
1846 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1847 return -EOPNOTSUPP;
1848
1849 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1850 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1851 return -EINVAL;
1852 }
1853
1854 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1855 priv->channels.params.rx_cqe_compress_def = enable;
1856
1857 return 0;
1858 }
1859
set_pflag_rx_striding_rq(struct net_device * netdev,bool enable)1860 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1861 {
1862 struct mlx5e_priv *priv = netdev_priv(netdev);
1863 struct mlx5_core_dev *mdev = priv->mdev;
1864 struct mlx5e_channels new_channels = {};
1865
1866 if (enable) {
1867 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1868 return -EOPNOTSUPP;
1869 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1870 return -EINVAL;
1871 } else if (priv->channels.params.lro_en) {
1872 netdev_warn(netdev, "Can't set legacy RQ with LRO, disable LRO first\n");
1873 return -EINVAL;
1874 }
1875
1876 new_channels.params = priv->channels.params;
1877
1878 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1879 mlx5e_set_rq_type(mdev, &new_channels.params);
1880
1881 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1882 priv->channels.params = new_channels.params;
1883 return 0;
1884 }
1885
1886 return mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1887 }
1888
set_pflag_rx_no_csum_complete(struct net_device * netdev,bool enable)1889 static int set_pflag_rx_no_csum_complete(struct net_device *netdev, bool enable)
1890 {
1891 struct mlx5e_priv *priv = netdev_priv(netdev);
1892 struct mlx5e_channels *channels = &priv->channels;
1893 struct mlx5e_channel *c;
1894 int i;
1895
1896 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) ||
1897 priv->channels.params.xdp_prog)
1898 return 0;
1899
1900 for (i = 0; i < channels->num; i++) {
1901 c = channels->c[i];
1902 if (enable)
1903 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1904 else
1905 __clear_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
1906 }
1907
1908 return 0;
1909 }
1910
set_pflag_tx_mpwqe_common(struct net_device * netdev,u32 flag,bool enable)1911 static int set_pflag_tx_mpwqe_common(struct net_device *netdev, u32 flag, bool enable)
1912 {
1913 struct mlx5e_priv *priv = netdev_priv(netdev);
1914 struct mlx5_core_dev *mdev = priv->mdev;
1915 struct mlx5e_channels new_channels = {};
1916 int err;
1917
1918 if (enable && !MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1919 return -EOPNOTSUPP;
1920
1921 new_channels.params = priv->channels.params;
1922
1923 MLX5E_SET_PFLAG(&new_channels.params, flag, enable);
1924
1925 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1926 priv->channels.params = new_channels.params;
1927 return 0;
1928 }
1929
1930 err = mlx5e_safe_switch_channels(priv, &new_channels, NULL, NULL);
1931 return err;
1932 }
1933
set_pflag_xdp_tx_mpwqe(struct net_device * netdev,bool enable)1934 static int set_pflag_xdp_tx_mpwqe(struct net_device *netdev, bool enable)
1935 {
1936 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_XDP_TX_MPWQE, enable);
1937 }
1938
set_pflag_skb_tx_mpwqe(struct net_device * netdev,bool enable)1939 static int set_pflag_skb_tx_mpwqe(struct net_device *netdev, bool enable)
1940 {
1941 return set_pflag_tx_mpwqe_common(netdev, MLX5E_PFLAG_SKB_TX_MPWQE, enable);
1942 }
1943
1944 static const struct pflag_desc mlx5e_priv_flags[MLX5E_NUM_PFLAGS] = {
1945 { "rx_cqe_moder", set_pflag_rx_cqe_based_moder },
1946 { "tx_cqe_moder", set_pflag_tx_cqe_based_moder },
1947 { "rx_cqe_compress", set_pflag_rx_cqe_compress },
1948 { "rx_striding_rq", set_pflag_rx_striding_rq },
1949 { "rx_no_csum_complete", set_pflag_rx_no_csum_complete },
1950 { "xdp_tx_mpwqe", set_pflag_xdp_tx_mpwqe },
1951 { "skb_tx_mpwqe", set_pflag_skb_tx_mpwqe },
1952 };
1953
mlx5e_handle_pflag(struct net_device * netdev,u32 wanted_flags,enum mlx5e_priv_flag flag)1954 static int mlx5e_handle_pflag(struct net_device *netdev,
1955 u32 wanted_flags,
1956 enum mlx5e_priv_flag flag)
1957 {
1958 struct mlx5e_priv *priv = netdev_priv(netdev);
1959 bool enable = !!(wanted_flags & BIT(flag));
1960 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1961 int err;
1962
1963 if (!(changes & BIT(flag)))
1964 return 0;
1965
1966 err = mlx5e_priv_flags[flag].handler(netdev, enable);
1967 if (err) {
1968 netdev_err(netdev, "%s private flag '%s' failed err %d\n",
1969 enable ? "Enable" : "Disable", mlx5e_priv_flags[flag].name, err);
1970 return err;
1971 }
1972
1973 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1974 return 0;
1975 }
1976
mlx5e_set_priv_flags(struct net_device * netdev,u32 pflags)1977 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1978 {
1979 struct mlx5e_priv *priv = netdev_priv(netdev);
1980 enum mlx5e_priv_flag pflag;
1981 int err;
1982
1983 mutex_lock(&priv->state_lock);
1984
1985 for (pflag = 0; pflag < MLX5E_NUM_PFLAGS; pflag++) {
1986 err = mlx5e_handle_pflag(netdev, pflags, pflag);
1987 if (err)
1988 break;
1989 }
1990
1991 mutex_unlock(&priv->state_lock);
1992
1993 /* Need to fix some features.. */
1994 netdev_update_features(netdev);
1995
1996 return err;
1997 }
1998
mlx5e_get_priv_flags(struct net_device * netdev)1999 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
2000 {
2001 struct mlx5e_priv *priv = netdev_priv(netdev);
2002
2003 return priv->channels.params.pflags;
2004 }
2005
mlx5e_get_rxnfc(struct net_device * dev,struct ethtool_rxnfc * info,u32 * rule_locs)2006 int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2007 u32 *rule_locs)
2008 {
2009 struct mlx5e_priv *priv = netdev_priv(dev);
2010
2011 /* ETHTOOL_GRXRINGS is needed by ethtool -x which is not part
2012 * of rxnfc. We keep this logic out of mlx5e_ethtool_get_rxnfc,
2013 * to avoid breaking "ethtool -x" when mlx5e_ethtool_get_rxnfc
2014 * is compiled out via CONFIG_MLX5_EN_RXNFC=n.
2015 */
2016 if (info->cmd == ETHTOOL_GRXRINGS) {
2017 info->data = priv->channels.params.num_channels;
2018 return 0;
2019 }
2020
2021 return mlx5e_ethtool_get_rxnfc(dev, info, rule_locs);
2022 }
2023
mlx5e_set_rxnfc(struct net_device * dev,struct ethtool_rxnfc * cmd)2024 int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2025 {
2026 return mlx5e_ethtool_set_rxnfc(dev, cmd);
2027 }
2028
2029 const struct ethtool_ops mlx5e_ethtool_ops = {
2030 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2031 ETHTOOL_COALESCE_MAX_FRAMES |
2032 ETHTOOL_COALESCE_USE_ADAPTIVE,
2033 .get_drvinfo = mlx5e_get_drvinfo,
2034 .get_link = ethtool_op_get_link,
2035 .get_strings = mlx5e_get_strings,
2036 .get_sset_count = mlx5e_get_sset_count,
2037 .get_ethtool_stats = mlx5e_get_ethtool_stats,
2038 .get_ringparam = mlx5e_get_ringparam,
2039 .set_ringparam = mlx5e_set_ringparam,
2040 .get_channels = mlx5e_get_channels,
2041 .set_channels = mlx5e_set_channels,
2042 .get_coalesce = mlx5e_get_coalesce,
2043 .set_coalesce = mlx5e_set_coalesce,
2044 .get_link_ksettings = mlx5e_get_link_ksettings,
2045 .set_link_ksettings = mlx5e_set_link_ksettings,
2046 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
2047 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2048 .get_rxfh = mlx5e_get_rxfh,
2049 .set_rxfh = mlx5e_set_rxfh,
2050 .get_rxnfc = mlx5e_get_rxnfc,
2051 .set_rxnfc = mlx5e_set_rxnfc,
2052 .get_tunable = mlx5e_get_tunable,
2053 .set_tunable = mlx5e_set_tunable,
2054 .get_pause_stats = mlx5e_get_pause_stats,
2055 .get_pauseparam = mlx5e_get_pauseparam,
2056 .set_pauseparam = mlx5e_set_pauseparam,
2057 .get_ts_info = mlx5e_get_ts_info,
2058 .set_phys_id = mlx5e_set_phys_id,
2059 .get_wol = mlx5e_get_wol,
2060 .set_wol = mlx5e_set_wol,
2061 .get_module_info = mlx5e_get_module_info,
2062 .get_module_eeprom = mlx5e_get_module_eeprom,
2063 .flash_device = mlx5e_flash_device,
2064 .get_priv_flags = mlx5e_get_priv_flags,
2065 .set_priv_flags = mlx5e_set_priv_flags,
2066 .self_test = mlx5e_self_test,
2067 .get_msglevel = mlx5e_get_msglevel,
2068 .set_msglevel = mlx5e_set_msglevel,
2069 .get_fecparam = mlx5e_get_fecparam,
2070 .set_fecparam = mlx5e_set_fecparam,
2071 };
2072
