1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 CGX driver 3 * 4 * Copyright (C) 2018 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __CGX_FW_INTF_H__ 12 #define __CGX_FW_INTF_H__ 13 14 #include <linux/bitops.h> 15 #include <linux/bitfield.h> 16 17 #define CGX_FIRMWARE_MAJOR_VER 1 18 #define CGX_FIRMWARE_MINOR_VER 0 19 20 #define CGX_EVENT_ACK 1UL 21 22 /* CGX error types. set for cmd response status as CGX_STAT_FAIL */ 23 enum cgx_error_type { 24 CGX_ERR_NONE, 25 CGX_ERR_LMAC_NOT_ENABLED, 26 CGX_ERR_LMAC_MODE_INVALID, 27 CGX_ERR_REQUEST_ID_INVALID, 28 CGX_ERR_PREV_ACK_NOT_CLEAR, 29 CGX_ERR_PHY_LINK_DOWN, 30 CGX_ERR_PCS_RESET_FAIL, 31 CGX_ERR_AN_CPT_FAIL, 32 CGX_ERR_TX_NOT_IDLE, 33 CGX_ERR_RX_NOT_IDLE, 34 CGX_ERR_SPUX_BR_BLKLOCK_FAIL, 35 CGX_ERR_SPUX_RX_ALIGN_FAIL, 36 CGX_ERR_SPUX_TX_FAULT, 37 CGX_ERR_SPUX_RX_FAULT, 38 CGX_ERR_SPUX_RESET_FAIL, 39 CGX_ERR_SPUX_AN_RESET_FAIL, 40 CGX_ERR_SPUX_USX_AN_RESET_FAIL, 41 CGX_ERR_SMUX_RX_LINK_NOT_OK, 42 CGX_ERR_PCS_RECV_LINK_FAIL, 43 CGX_ERR_TRAINING_FAIL, 44 CGX_ERR_RX_EQU_FAIL, 45 CGX_ERR_SPUX_BER_FAIL, 46 CGX_ERR_SPUX_RSFEC_ALGN_FAIL, /* = 22 */ 47 }; 48 49 /* LINK speed types */ 50 enum cgx_link_speed { 51 CGX_LINK_NONE, 52 CGX_LINK_10M, 53 CGX_LINK_100M, 54 CGX_LINK_1G, 55 CGX_LINK_2HG, 56 CGX_LINK_5G, 57 CGX_LINK_10G, 58 CGX_LINK_20G, 59 CGX_LINK_25G, 60 CGX_LINK_40G, 61 CGX_LINK_50G, 62 CGX_LINK_100G, 63 CGX_LINK_SPEED_MAX, 64 }; 65 66 /* REQUEST ID types. Input to firmware */ 67 enum cgx_cmd_id { 68 CGX_CMD_NONE, 69 CGX_CMD_GET_FW_VER, 70 CGX_CMD_GET_MAC_ADDR, 71 CGX_CMD_SET_MTU, 72 CGX_CMD_GET_LINK_STS, /* optional to user */ 73 CGX_CMD_LINK_BRING_UP, 74 CGX_CMD_LINK_BRING_DOWN, 75 CGX_CMD_INTERNAL_LBK, 76 CGX_CMD_EXTERNAL_LBK, 77 CGX_CMD_HIGIG, 78 CGX_CMD_LINK_STATE_CHANGE, 79 CGX_CMD_MODE_CHANGE, /* hot plug support */ 80 CGX_CMD_INTF_SHUTDOWN, 81 CGX_CMD_GET_MKEX_PRFL_SIZE, 82 CGX_CMD_GET_MKEX_PRFL_ADDR, 83 CGX_CMD_GET_FWD_BASE, /* get base address of shared FW data */ 84 }; 85 86 /* async event ids */ 87 enum cgx_evt_id { 88 CGX_EVT_NONE, 89 CGX_EVT_LINK_CHANGE, 90 }; 91 92 /* event types - cause of interrupt */ 93 enum cgx_evt_type { 94 CGX_EVT_ASYNC, 95 CGX_EVT_CMD_RESP 96 }; 97 98 enum cgx_stat { 99 CGX_STAT_SUCCESS, 100 CGX_STAT_FAIL 101 }; 102 103 enum cgx_cmd_own { 104 CGX_CMD_OWN_NS, 105 CGX_CMD_OWN_FIRMWARE, 106 }; 107 108 /* m - bit mask 109 * y - value to be written in the bitrange 110 * x - input value whose bitrange to be modified 111 */ 112 #define FIELD_SET(m, y, x) \ 113 (((x) & ~(m)) | \ 114 FIELD_PREP((m), (y))) 115 116 /* scratchx(0) CSR used for ATF->non-secure SW communication. 117 * This acts as the status register 118 * Provides details on command ack/status, command response, error details 119 */ 120 #define EVTREG_ACK BIT_ULL(0) 121 #define EVTREG_EVT_TYPE BIT_ULL(1) 122 #define EVTREG_STAT BIT_ULL(2) 123 #define EVTREG_ID GENMASK_ULL(8, 3) 124 125 /* Response to command IDs with command status as CGX_STAT_FAIL 126 * 127 * Not applicable for commands : 128 * CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE 129 */ 130 #define EVTREG_ERRTYPE GENMASK_ULL(18, 9) 131 132 /* Response to cmd ID as CGX_CMD_GET_FW_VER with cmd status as 133 * CGX_STAT_SUCCESS 134 */ 135 #define RESP_MAJOR_VER GENMASK_ULL(12, 9) 136 #define RESP_MINOR_VER GENMASK_ULL(16, 13) 137 138 /* Response to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as 139 * CGX_STAT_SUCCESS 140 */ 141 #define RESP_MAC_ADDR GENMASK_ULL(56, 9) 142 143 /* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_SIZE with cmd status as 144 * CGX_STAT_SUCCESS 145 */ 146 #define RESP_MKEX_PRFL_SIZE GENMASK_ULL(63, 9) 147 148 /* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_ADDR with cmd status as 149 * CGX_STAT_SUCCESS 150 */ 151 #define RESP_MKEX_PRFL_ADDR GENMASK_ULL(63, 9) 152 153 /* Response to cmd ID as CGX_CMD_GET_FWD_BASE with cmd status as 154 * CGX_STAT_SUCCESS 155 */ 156 #define RESP_FWD_BASE GENMASK_ULL(56, 9) 157 158 /* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE 159 * status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS 160 * 161 * In case of CGX_STAT_FAIL, it indicates CGX configuration failed 162 * when processing link up/down/change command. 163 * Both err_type and current link status will be updated 164 * 165 * In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current 166 * link status will be updated 167 */ 168 struct cgx_lnk_sts { 169 uint64_t reserved1:9; 170 uint64_t link_up:1; 171 uint64_t full_duplex:1; 172 uint64_t speed:4; /* cgx_link_speed */ 173 uint64_t err_type:10; 174 uint64_t reserved2:39; 175 }; 176 177 #define RESP_LINKSTAT_UP GENMASK_ULL(9, 9) 178 #define RESP_LINKSTAT_FDUPLEX GENMASK_ULL(10, 10) 179 #define RESP_LINKSTAT_SPEED GENMASK_ULL(14, 11) 180 #define RESP_LINKSTAT_ERRTYPE GENMASK_ULL(24, 15) 181 182 /* scratchx(1) CSR used for non-secure SW->ATF communication 183 * This CSR acts as a command register 184 */ 185 #define CMDREG_OWN BIT_ULL(0) 186 #define CMDREG_ID GENMASK_ULL(7, 2) 187 188 /* Any command using enable/disable as an argument need 189 * to set this bitfield. 190 * Ex: Loopback, HiGig... 191 */ 192 #define CMDREG_ENABLE BIT_ULL(8) 193 194 /* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */ 195 #define CMDMTU_SIZE GENMASK_ULL(23, 8) 196 197 /* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */ 198 #define CMDLINKCHANGE_LINKUP BIT_ULL(8) 199 #define CMDLINKCHANGE_FULLDPLX BIT_ULL(9) 200 #define CMDLINKCHANGE_SPEED GENMASK_ULL(13, 10) 201 202 #endif /* __CGX_FW_INTF_H__ */ 203
