1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2019 Macronix International Co., Ltd.
4 *
5 * Author:
6 * Mason Yang <masonccyang@mxic.com.tw>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/rawnand.h>
16 #include <linux/mtd/nand_ecc.h>
17 #include <linux/platform_device.h>
18
19 #include "internals.h"
20
21 #define HC_CFG 0x0
22 #define HC_CFG_IF_CFG(x) ((x) << 27)
23 #define HC_CFG_DUAL_SLAVE BIT(31)
24 #define HC_CFG_INDIVIDUAL BIT(30)
25 #define HC_CFG_NIO(x) (((x) / 4) << 27)
26 #define HC_CFG_TYPE(s, t) ((t) << (23 + ((s) * 2)))
27 #define HC_CFG_TYPE_SPI_NOR 0
28 #define HC_CFG_TYPE_SPI_NAND 1
29 #define HC_CFG_TYPE_SPI_RAM 2
30 #define HC_CFG_TYPE_RAW_NAND 3
31 #define HC_CFG_SLV_ACT(x) ((x) << 21)
32 #define HC_CFG_CLK_PH_EN BIT(20)
33 #define HC_CFG_CLK_POL_INV BIT(19)
34 #define HC_CFG_BIG_ENDIAN BIT(18)
35 #define HC_CFG_DATA_PASS BIT(17)
36 #define HC_CFG_IDLE_SIO_LVL(x) ((x) << 16)
37 #define HC_CFG_MAN_START_EN BIT(3)
38 #define HC_CFG_MAN_START BIT(2)
39 #define HC_CFG_MAN_CS_EN BIT(1)
40 #define HC_CFG_MAN_CS_ASSERT BIT(0)
41
42 #define INT_STS 0x4
43 #define INT_STS_EN 0x8
44 #define INT_SIG_EN 0xc
45 #define INT_STS_ALL GENMASK(31, 0)
46 #define INT_RDY_PIN BIT(26)
47 #define INT_RDY_SR BIT(25)
48 #define INT_LNR_SUSP BIT(24)
49 #define INT_ECC_ERR BIT(17)
50 #define INT_CRC_ERR BIT(16)
51 #define INT_LWR_DIS BIT(12)
52 #define INT_LRD_DIS BIT(11)
53 #define INT_SDMA_INT BIT(10)
54 #define INT_DMA_FINISH BIT(9)
55 #define INT_RX_NOT_FULL BIT(3)
56 #define INT_RX_NOT_EMPTY BIT(2)
57 #define INT_TX_NOT_FULL BIT(1)
58 #define INT_TX_EMPTY BIT(0)
59
60 #define HC_EN 0x10
61 #define HC_EN_BIT BIT(0)
62
63 #define TXD(x) (0x14 + ((x) * 4))
64 #define RXD 0x24
65
66 #define SS_CTRL(s) (0x30 + ((s) * 4))
67 #define LRD_CFG 0x44
68 #define LWR_CFG 0x80
69 #define RWW_CFG 0x70
70 #define OP_READ BIT(23)
71 #define OP_DUMMY_CYC(x) ((x) << 17)
72 #define OP_ADDR_BYTES(x) ((x) << 14)
73 #define OP_CMD_BYTES(x) (((x) - 1) << 13)
74 #define OP_OCTA_CRC_EN BIT(12)
75 #define OP_DQS_EN BIT(11)
76 #define OP_ENHC_EN BIT(10)
77 #define OP_PREAMBLE_EN BIT(9)
78 #define OP_DATA_DDR BIT(8)
79 #define OP_DATA_BUSW(x) ((x) << 6)
80 #define OP_ADDR_DDR BIT(5)
81 #define OP_ADDR_BUSW(x) ((x) << 3)
82 #define OP_CMD_DDR BIT(2)
83 #define OP_CMD_BUSW(x) (x)
84 #define OP_BUSW_1 0
85 #define OP_BUSW_2 1
86 #define OP_BUSW_4 2
87 #define OP_BUSW_8 3
88
89 #define OCTA_CRC 0x38
90 #define OCTA_CRC_IN_EN(s) BIT(3 + ((s) * 16))
91 #define OCTA_CRC_CHUNK(s, x) ((fls((x) / 32)) << (1 + ((s) * 16)))
92 #define OCTA_CRC_OUT_EN(s) BIT(0 + ((s) * 16))
93
94 #define ONFI_DIN_CNT(s) (0x3c + (s))
95
96 #define LRD_CTRL 0x48
97 #define RWW_CTRL 0x74
98 #define LWR_CTRL 0x84
99 #define LMODE_EN BIT(31)
100 #define LMODE_SLV_ACT(x) ((x) << 21)
101 #define LMODE_CMD1(x) ((x) << 8)
102 #define LMODE_CMD0(x) (x)
103
104 #define LRD_ADDR 0x4c
105 #define LWR_ADDR 0x88
106 #define LRD_RANGE 0x50
107 #define LWR_RANGE 0x8c
108
109 #define AXI_SLV_ADDR 0x54
110
111 #define DMAC_RD_CFG 0x58
112 #define DMAC_WR_CFG 0x94
113 #define DMAC_CFG_PERIPH_EN BIT(31)
114 #define DMAC_CFG_ALLFLUSH_EN BIT(30)
115 #define DMAC_CFG_LASTFLUSH_EN BIT(29)
116 #define DMAC_CFG_QE(x) (((x) + 1) << 16)
117 #define DMAC_CFG_BURST_LEN(x) (((x) + 1) << 12)
118 #define DMAC_CFG_BURST_SZ(x) ((x) << 8)
119 #define DMAC_CFG_DIR_READ BIT(1)
120 #define DMAC_CFG_START BIT(0)
121
122 #define DMAC_RD_CNT 0x5c
123 #define DMAC_WR_CNT 0x98
124
125 #define SDMA_ADDR 0x60
126
127 #define DMAM_CFG 0x64
128 #define DMAM_CFG_START BIT(31)
129 #define DMAM_CFG_CONT BIT(30)
130 #define DMAM_CFG_SDMA_GAP(x) (fls((x) / 8192) << 2)
131 #define DMAM_CFG_DIR_READ BIT(1)
132 #define DMAM_CFG_EN BIT(0)
133
134 #define DMAM_CNT 0x68
135
136 #define LNR_TIMER_TH 0x6c
137
138 #define RDM_CFG0 0x78
139 #define RDM_CFG0_POLY(x) (x)
140
141 #define RDM_CFG1 0x7c
142 #define RDM_CFG1_RDM_EN BIT(31)
143 #define RDM_CFG1_SEED(x) (x)
144
145 #define LWR_SUSP_CTRL 0x90
146 #define LWR_SUSP_CTRL_EN BIT(31)
147
148 #define DMAS_CTRL 0x9c
149 #define DMAS_CTRL_EN BIT(31)
150 #define DMAS_CTRL_DIR_READ BIT(30)
151
152 #define DATA_STROB 0xa0
153 #define DATA_STROB_EDO_EN BIT(2)
154 #define DATA_STROB_INV_POL BIT(1)
155 #define DATA_STROB_DELAY_2CYC BIT(0)
156
157 #define IDLY_CODE(x) (0xa4 + ((x) * 4))
158 #define IDLY_CODE_VAL(x, v) ((v) << (((x) % 4) * 8))
159
160 #define GPIO 0xc4
161 #define GPIO_PT(x) BIT(3 + ((x) * 16))
162 #define GPIO_RESET(x) BIT(2 + ((x) * 16))
163 #define GPIO_HOLDB(x) BIT(1 + ((x) * 16))
164 #define GPIO_WPB(x) BIT((x) * 16)
165
166 #define HC_VER 0xd0
167
168 #define HW_TEST(x) (0xe0 + ((x) * 4))
169
170 #define MXIC_NFC_MAX_CLK_HZ 50000000
171 #define IRQ_TIMEOUT 1000
172
173 struct mxic_nand_ctlr {
174 struct clk *ps_clk;
175 struct clk *send_clk;
176 struct clk *send_dly_clk;
177 struct completion complete;
178 void __iomem *regs;
179 struct nand_controller controller;
180 struct device *dev;
181 struct nand_chip chip;
182 };
183
mxic_nfc_clk_enable(struct mxic_nand_ctlr * nfc)184 static int mxic_nfc_clk_enable(struct mxic_nand_ctlr *nfc)
185 {
186 int ret;
187
188 ret = clk_prepare_enable(nfc->ps_clk);
189 if (ret)
190 return ret;
191
192 ret = clk_prepare_enable(nfc->send_clk);
193 if (ret)
194 goto err_ps_clk;
195
196 ret = clk_prepare_enable(nfc->send_dly_clk);
197 if (ret)
198 goto err_send_dly_clk;
199
200 return ret;
201
202 err_send_dly_clk:
203 clk_disable_unprepare(nfc->send_clk);
204 err_ps_clk:
205 clk_disable_unprepare(nfc->ps_clk);
206
207 return ret;
208 }
209
mxic_nfc_clk_disable(struct mxic_nand_ctlr * nfc)210 static void mxic_nfc_clk_disable(struct mxic_nand_ctlr *nfc)
211 {
212 clk_disable_unprepare(nfc->send_clk);
213 clk_disable_unprepare(nfc->send_dly_clk);
214 clk_disable_unprepare(nfc->ps_clk);
215 }
216
mxic_nfc_set_input_delay(struct mxic_nand_ctlr * nfc,u8 idly_code)217 static void mxic_nfc_set_input_delay(struct mxic_nand_ctlr *nfc, u8 idly_code)
218 {
219 writel(IDLY_CODE_VAL(0, idly_code) |
220 IDLY_CODE_VAL(1, idly_code) |
221 IDLY_CODE_VAL(2, idly_code) |
222 IDLY_CODE_VAL(3, idly_code),
223 nfc->regs + IDLY_CODE(0));
224 writel(IDLY_CODE_VAL(4, idly_code) |
225 IDLY_CODE_VAL(5, idly_code) |
226 IDLY_CODE_VAL(6, idly_code) |
227 IDLY_CODE_VAL(7, idly_code),
228 nfc->regs + IDLY_CODE(1));
229 }
230
mxic_nfc_clk_setup(struct mxic_nand_ctlr * nfc,unsigned long freq)231 static int mxic_nfc_clk_setup(struct mxic_nand_ctlr *nfc, unsigned long freq)
232 {
233 int ret;
234
235 ret = clk_set_rate(nfc->send_clk, freq);
236 if (ret)
237 return ret;
238
239 ret = clk_set_rate(nfc->send_dly_clk, freq);
240 if (ret)
241 return ret;
242
243 /*
244 * A constant delay range from 0x0 ~ 0x1F for input delay,
245 * the unit is 78 ps, the max input delay is 2.418 ns.
246 */
247 mxic_nfc_set_input_delay(nfc, 0xf);
248
249 /*
250 * Phase degree = 360 * freq * output-delay
251 * where output-delay is a constant value 1 ns in FPGA.
252 *
253 * Get Phase degree = 360 * freq * 1 ns
254 * = 360 * freq * 1 sec / 1000000000
255 * = 9 * freq / 25000000
256 */
257 ret = clk_set_phase(nfc->send_dly_clk, 9 * freq / 25000000);
258 if (ret)
259 return ret;
260
261 return 0;
262 }
263
mxic_nfc_set_freq(struct mxic_nand_ctlr * nfc,unsigned long freq)264 static int mxic_nfc_set_freq(struct mxic_nand_ctlr *nfc, unsigned long freq)
265 {
266 int ret;
267
268 if (freq > MXIC_NFC_MAX_CLK_HZ)
269 freq = MXIC_NFC_MAX_CLK_HZ;
270
271 mxic_nfc_clk_disable(nfc);
272 ret = mxic_nfc_clk_setup(nfc, freq);
273 if (ret)
274 return ret;
275
276 ret = mxic_nfc_clk_enable(nfc);
277 if (ret)
278 return ret;
279
280 return 0;
281 }
282
mxic_nfc_isr(int irq,void * dev_id)283 static irqreturn_t mxic_nfc_isr(int irq, void *dev_id)
284 {
285 struct mxic_nand_ctlr *nfc = dev_id;
286 u32 sts;
287
288 sts = readl(nfc->regs + INT_STS);
289 if (sts & INT_RDY_PIN)
290 complete(&nfc->complete);
291 else
292 return IRQ_NONE;
293
294 return IRQ_HANDLED;
295 }
296
mxic_nfc_hw_init(struct mxic_nand_ctlr * nfc)297 static void mxic_nfc_hw_init(struct mxic_nand_ctlr *nfc)
298 {
299 writel(HC_CFG_NIO(8) | HC_CFG_TYPE(1, HC_CFG_TYPE_RAW_NAND) |
300 HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN |
301 HC_CFG_IDLE_SIO_LVL(1), nfc->regs + HC_CFG);
302 writel(INT_STS_ALL, nfc->regs + INT_STS_EN);
303 writel(INT_RDY_PIN, nfc->regs + INT_SIG_EN);
304 writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
305 writel(0, nfc->regs + LRD_CFG);
306 writel(0, nfc->regs + LRD_CTRL);
307 writel(0x0, nfc->regs + HC_EN);
308 }
309
mxic_nfc_cs_enable(struct mxic_nand_ctlr * nfc)310 static void mxic_nfc_cs_enable(struct mxic_nand_ctlr *nfc)
311 {
312 writel(readl(nfc->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
313 nfc->regs + HC_CFG);
314 writel(HC_CFG_MAN_CS_ASSERT | readl(nfc->regs + HC_CFG),
315 nfc->regs + HC_CFG);
316 }
317
mxic_nfc_cs_disable(struct mxic_nand_ctlr * nfc)318 static void mxic_nfc_cs_disable(struct mxic_nand_ctlr *nfc)
319 {
320 writel(~HC_CFG_MAN_CS_ASSERT & readl(nfc->regs + HC_CFG),
321 nfc->regs + HC_CFG);
322 }
323
mxic_nfc_wait_ready(struct nand_chip * chip)324 static int mxic_nfc_wait_ready(struct nand_chip *chip)
325 {
326 struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip);
327 int ret;
328
329 ret = wait_for_completion_timeout(&nfc->complete,
330 msecs_to_jiffies(IRQ_TIMEOUT));
331 if (!ret) {
332 dev_err(nfc->dev, "nand device timeout\n");
333 return -ETIMEDOUT;
334 }
335
336 return 0;
337 }
338
mxic_nfc_data_xfer(struct mxic_nand_ctlr * nfc,const void * txbuf,void * rxbuf,unsigned int len)339 static int mxic_nfc_data_xfer(struct mxic_nand_ctlr *nfc, const void *txbuf,
340 void *rxbuf, unsigned int len)
341 {
342 unsigned int pos = 0;
343
344 while (pos < len) {
345 unsigned int nbytes = len - pos;
346 u32 data = 0xffffffff;
347 u32 sts;
348 int ret;
349
350 if (nbytes > 4)
351 nbytes = 4;
352
353 if (txbuf)
354 memcpy(&data, txbuf + pos, nbytes);
355
356 ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
357 sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
358 if (ret)
359 return ret;
360
361 writel(data, nfc->regs + TXD(nbytes % 4));
362
363 ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
364 sts & INT_TX_EMPTY, 0, USEC_PER_SEC);
365 if (ret)
366 return ret;
367
368 ret = readl_poll_timeout(nfc->regs + INT_STS, sts,
369 sts & INT_RX_NOT_EMPTY, 0,
370 USEC_PER_SEC);
371 if (ret)
372 return ret;
373
374 data = readl(nfc->regs + RXD);
375 if (rxbuf) {
376 data >>= (8 * (4 - nbytes));
377 memcpy(rxbuf + pos, &data, nbytes);
378 }
379 if (readl(nfc->regs + INT_STS) & INT_RX_NOT_EMPTY)
380 dev_warn(nfc->dev, "RX FIFO not empty\n");
381
382 pos += nbytes;
383 }
384
385 return 0;
386 }
387
mxic_nfc_exec_op(struct nand_chip * chip,const struct nand_operation * op,bool check_only)388 static int mxic_nfc_exec_op(struct nand_chip *chip,
389 const struct nand_operation *op, bool check_only)
390 {
391 struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip);
392 const struct nand_op_instr *instr = NULL;
393 int ret = 0;
394 unsigned int op_id;
395
396 if (check_only)
397 return 0;
398
399 mxic_nfc_cs_enable(nfc);
400 init_completion(&nfc->complete);
401 for (op_id = 0; op_id < op->ninstrs; op_id++) {
402 instr = &op->instrs[op_id];
403
404 switch (instr->type) {
405 case NAND_OP_CMD_INSTR:
406 writel(0, nfc->regs + HC_EN);
407 writel(HC_EN_BIT, nfc->regs + HC_EN);
408 writel(OP_CMD_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
409 OP_CMD_BYTES(0), nfc->regs + SS_CTRL(0));
410
411 ret = mxic_nfc_data_xfer(nfc,
412 &instr->ctx.cmd.opcode,
413 NULL, 1);
414 break;
415
416 case NAND_OP_ADDR_INSTR:
417 writel(OP_ADDR_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
418 OP_ADDR_BYTES(instr->ctx.addr.naddrs),
419 nfc->regs + SS_CTRL(0));
420 ret = mxic_nfc_data_xfer(nfc,
421 instr->ctx.addr.addrs, NULL,
422 instr->ctx.addr.naddrs);
423 break;
424
425 case NAND_OP_DATA_IN_INSTR:
426 writel(0x0, nfc->regs + ONFI_DIN_CNT(0));
427 writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F) |
428 OP_READ, nfc->regs + SS_CTRL(0));
429 ret = mxic_nfc_data_xfer(nfc, NULL,
430 instr->ctx.data.buf.in,
431 instr->ctx.data.len);
432 break;
433
434 case NAND_OP_DATA_OUT_INSTR:
435 writel(instr->ctx.data.len,
436 nfc->regs + ONFI_DIN_CNT(0));
437 writel(OP_DATA_BUSW(OP_BUSW_8) | OP_DUMMY_CYC(0x3F),
438 nfc->regs + SS_CTRL(0));
439 ret = mxic_nfc_data_xfer(nfc,
440 instr->ctx.data.buf.out, NULL,
441 instr->ctx.data.len);
442 break;
443
444 case NAND_OP_WAITRDY_INSTR:
445 ret = mxic_nfc_wait_ready(chip);
446 break;
447 }
448 }
449 mxic_nfc_cs_disable(nfc);
450
451 return ret;
452 }
453
mxic_nfc_setup_interface(struct nand_chip * chip,int chipnr,const struct nand_interface_config * conf)454 static int mxic_nfc_setup_interface(struct nand_chip *chip, int chipnr,
455 const struct nand_interface_config *conf)
456 {
457 struct mxic_nand_ctlr *nfc = nand_get_controller_data(chip);
458 const struct nand_sdr_timings *sdr;
459 unsigned long freq;
460 int ret;
461
462 sdr = nand_get_sdr_timings(conf);
463 if (IS_ERR(sdr))
464 return PTR_ERR(sdr);
465
466 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
467 return 0;
468
469 freq = NSEC_PER_SEC / (sdr->tRC_min / 1000);
470
471 ret = mxic_nfc_set_freq(nfc, freq);
472 if (ret)
473 dev_err(nfc->dev, "set freq:%ld failed\n", freq);
474
475 if (sdr->tRC_min < 30000)
476 writel(DATA_STROB_EDO_EN, nfc->regs + DATA_STROB);
477
478 return 0;
479 }
480
481 static const struct nand_controller_ops mxic_nand_controller_ops = {
482 .exec_op = mxic_nfc_exec_op,
483 .setup_interface = mxic_nfc_setup_interface,
484 };
485
mxic_nfc_probe(struct platform_device * pdev)486 static int mxic_nfc_probe(struct platform_device *pdev)
487 {
488 struct device_node *nand_np, *np = pdev->dev.of_node;
489 struct mtd_info *mtd;
490 struct mxic_nand_ctlr *nfc;
491 struct nand_chip *nand_chip;
492 int err;
493 int irq;
494
495 nfc = devm_kzalloc(&pdev->dev, sizeof(struct mxic_nand_ctlr),
496 GFP_KERNEL);
497 if (!nfc)
498 return -ENOMEM;
499
500 nfc->ps_clk = devm_clk_get(&pdev->dev, "ps");
501 if (IS_ERR(nfc->ps_clk))
502 return PTR_ERR(nfc->ps_clk);
503
504 nfc->send_clk = devm_clk_get(&pdev->dev, "send");
505 if (IS_ERR(nfc->send_clk))
506 return PTR_ERR(nfc->send_clk);
507
508 nfc->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly");
509 if (IS_ERR(nfc->send_dly_clk))
510 return PTR_ERR(nfc->send_dly_clk);
511
512 nfc->regs = devm_platform_ioremap_resource(pdev, 0);
513 if (IS_ERR(nfc->regs))
514 return PTR_ERR(nfc->regs);
515
516 nand_chip = &nfc->chip;
517 mtd = nand_to_mtd(nand_chip);
518 mtd->dev.parent = &pdev->dev;
519
520 for_each_child_of_node(np, nand_np)
521 nand_set_flash_node(nand_chip, nand_np);
522
523 nand_chip->priv = nfc;
524 nfc->dev = &pdev->dev;
525 nfc->controller.ops = &mxic_nand_controller_ops;
526 nand_controller_init(&nfc->controller);
527 nand_chip->controller = &nfc->controller;
528
529 irq = platform_get_irq(pdev, 0);
530 if (irq < 0)
531 return irq;
532
533 mxic_nfc_hw_init(nfc);
534
535 err = devm_request_irq(&pdev->dev, irq, mxic_nfc_isr,
536 0, "mxic-nfc", nfc);
537 if (err)
538 goto fail;
539
540 err = nand_scan(nand_chip, 1);
541 if (err)
542 goto fail;
543
544 err = mtd_device_register(mtd, NULL, 0);
545 if (err)
546 goto fail;
547
548 platform_set_drvdata(pdev, nfc);
549 return 0;
550
551 fail:
552 mxic_nfc_clk_disable(nfc);
553 return err;
554 }
555
mxic_nfc_remove(struct platform_device * pdev)556 static int mxic_nfc_remove(struct platform_device *pdev)
557 {
558 struct mxic_nand_ctlr *nfc = platform_get_drvdata(pdev);
559 struct nand_chip *chip = &nfc->chip;
560 int ret;
561
562 ret = mtd_device_unregister(nand_to_mtd(chip));
563 WARN_ON(ret);
564 nand_cleanup(chip);
565
566 mxic_nfc_clk_disable(nfc);
567 return 0;
568 }
569
570 static const struct of_device_id mxic_nfc_of_ids[] = {
571 { .compatible = "mxic,multi-itfc-v009-nand-controller", },
572 {},
573 };
574 MODULE_DEVICE_TABLE(of, mxic_nfc_of_ids);
575
576 static struct platform_driver mxic_nfc_driver = {
577 .probe = mxic_nfc_probe,
578 .remove = mxic_nfc_remove,
579 .driver = {
580 .name = "mxic-nfc",
581 .of_match_table = mxic_nfc_of_ids,
582 },
583 };
584 module_platform_driver(mxic_nfc_driver);
585
586 MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");
587 MODULE_DESCRIPTION("Macronix raw NAND controller driver");
588 MODULE_LICENSE("GPL v2");
589
