1 /*
2 * MOXA ART MMC host driver.
3 *
4 * Copyright (C) 2014 Jonas Jensen
5 *
6 * Jonas Jensen <jonas.jensen@gmail.com>
7 *
8 * Based on code from
9 * Moxa Technologies Co., Ltd. <www.moxa.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/blkdev.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmaengine.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/sd.h>
27 #include <linux/sched.h>
28 #include <linux/io.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/clk.h>
32 #include <linux/bitops.h>
33 #include <linux/of_dma.h>
34 #include <linux/spinlock.h>
35
36 #define REG_COMMAND 0
37 #define REG_ARGUMENT 4
38 #define REG_RESPONSE0 8
39 #define REG_RESPONSE1 12
40 #define REG_RESPONSE2 16
41 #define REG_RESPONSE3 20
42 #define REG_RESPONSE_COMMAND 24
43 #define REG_DATA_CONTROL 28
44 #define REG_DATA_TIMER 32
45 #define REG_DATA_LENGTH 36
46 #define REG_STATUS 40
47 #define REG_CLEAR 44
48 #define REG_INTERRUPT_MASK 48
49 #define REG_POWER_CONTROL 52
50 #define REG_CLOCK_CONTROL 56
51 #define REG_BUS_WIDTH 60
52 #define REG_DATA_WINDOW 64
53 #define REG_FEATURE 68
54 #define REG_REVISION 72
55
56 /* REG_COMMAND */
57 #define CMD_SDC_RESET BIT(10)
58 #define CMD_EN BIT(9)
59 #define CMD_APP_CMD BIT(8)
60 #define CMD_LONG_RSP BIT(7)
61 #define CMD_NEED_RSP BIT(6)
62 #define CMD_IDX_MASK 0x3f
63
64 /* REG_RESPONSE_COMMAND */
65 #define RSP_CMD_APP BIT(6)
66 #define RSP_CMD_IDX_MASK 0x3f
67
68 /* REG_DATA_CONTROL */
69 #define DCR_DATA_FIFO_RESET BIT(8)
70 #define DCR_DATA_THRES BIT(7)
71 #define DCR_DATA_EN BIT(6)
72 #define DCR_DMA_EN BIT(5)
73 #define DCR_DATA_WRITE BIT(4)
74 #define DCR_BLK_SIZE 0x0f
75
76 /* REG_DATA_LENGTH */
77 #define DATA_LEN_MASK 0xffffff
78
79 /* REG_STATUS */
80 #define WRITE_PROT BIT(12)
81 #define CARD_DETECT BIT(11)
82 /* 1-10 below can be sent to either registers, interrupt or clear. */
83 #define CARD_CHANGE BIT(10)
84 #define FIFO_ORUN BIT(9)
85 #define FIFO_URUN BIT(8)
86 #define DATA_END BIT(7)
87 #define CMD_SENT BIT(6)
88 #define DATA_CRC_OK BIT(5)
89 #define RSP_CRC_OK BIT(4)
90 #define DATA_TIMEOUT BIT(3)
91 #define RSP_TIMEOUT BIT(2)
92 #define DATA_CRC_FAIL BIT(1)
93 #define RSP_CRC_FAIL BIT(0)
94
95 #define MASK_RSP (RSP_TIMEOUT | RSP_CRC_FAIL | \
96 RSP_CRC_OK | CARD_DETECT | CMD_SENT)
97
98 #define MASK_DATA (DATA_CRC_OK | DATA_END | \
99 DATA_CRC_FAIL | DATA_TIMEOUT)
100
101 #define MASK_INTR_PIO (FIFO_URUN | FIFO_ORUN | CARD_CHANGE)
102
103 /* REG_POWER_CONTROL */
104 #define SD_POWER_ON BIT(4)
105 #define SD_POWER_MASK 0x0f
106
107 /* REG_CLOCK_CONTROL */
108 #define CLK_HISPD BIT(9)
109 #define CLK_OFF BIT(8)
110 #define CLK_SD BIT(7)
111 #define CLK_DIV_MASK 0x7f
112
113 /* REG_BUS_WIDTH */
114 #define BUS_WIDTH_8 BIT(2)
115 #define BUS_WIDTH_4 BIT(1)
116 #define BUS_WIDTH_1 BIT(0)
117
118 #define MMC_VDD_360 23
119 #define MIN_POWER (MMC_VDD_360 - SD_POWER_MASK)
120 #define MAX_RETRIES 500000
121
122 struct moxart_host {
123 spinlock_t lock;
124
125 void __iomem *base;
126
127 phys_addr_t reg_phys;
128
129 struct dma_chan *dma_chan_tx;
130 struct dma_chan *dma_chan_rx;
131 struct dma_async_tx_descriptor *tx_desc;
132 struct mmc_host *mmc;
133 struct mmc_request *mrq;
134 struct scatterlist *cur_sg;
135 struct completion dma_complete;
136 struct completion pio_complete;
137
138 u32 num_sg;
139 u32 data_remain;
140 u32 data_len;
141 u32 fifo_width;
142 u32 timeout;
143 u32 rate;
144
145 long sysclk;
146
147 bool have_dma;
148 bool is_removed;
149 };
150
moxart_init_sg(struct moxart_host * host,struct mmc_data * data)151 static inline void moxart_init_sg(struct moxart_host *host,
152 struct mmc_data *data)
153 {
154 host->cur_sg = data->sg;
155 host->num_sg = data->sg_len;
156 host->data_remain = host->cur_sg->length;
157
158 if (host->data_remain > host->data_len)
159 host->data_remain = host->data_len;
160 }
161
moxart_next_sg(struct moxart_host * host)162 static inline int moxart_next_sg(struct moxart_host *host)
163 {
164 int remain;
165 struct mmc_data *data = host->mrq->cmd->data;
166
167 host->cur_sg++;
168 host->num_sg--;
169
170 if (host->num_sg > 0) {
171 host->data_remain = host->cur_sg->length;
172 remain = host->data_len - data->bytes_xfered;
173 if (remain > 0 && remain < host->data_remain)
174 host->data_remain = remain;
175 }
176
177 return host->num_sg;
178 }
179
moxart_wait_for_status(struct moxart_host * host,u32 mask,u32 * status)180 static int moxart_wait_for_status(struct moxart_host *host,
181 u32 mask, u32 *status)
182 {
183 int ret = -ETIMEDOUT;
184 u32 i;
185
186 for (i = 0; i < MAX_RETRIES; i++) {
187 *status = readl(host->base + REG_STATUS);
188 if (!(*status & mask)) {
189 udelay(5);
190 continue;
191 }
192 writel(*status & mask, host->base + REG_CLEAR);
193 ret = 0;
194 break;
195 }
196
197 if (ret)
198 dev_err(mmc_dev(host->mmc), "timed out waiting for status\n");
199
200 return ret;
201 }
202
203
moxart_send_command(struct moxart_host * host,struct mmc_command * cmd)204 static void moxart_send_command(struct moxart_host *host,
205 struct mmc_command *cmd)
206 {
207 u32 status, cmdctrl;
208
209 writel(RSP_TIMEOUT | RSP_CRC_OK |
210 RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR);
211 writel(cmd->arg, host->base + REG_ARGUMENT);
212
213 cmdctrl = cmd->opcode & CMD_IDX_MASK;
214 if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND ||
215 cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS ||
216 cmdctrl == SD_APP_SEND_NUM_WR_BLKS)
217 cmdctrl |= CMD_APP_CMD;
218
219 if (cmd->flags & MMC_RSP_PRESENT)
220 cmdctrl |= CMD_NEED_RSP;
221
222 if (cmd->flags & MMC_RSP_136)
223 cmdctrl |= CMD_LONG_RSP;
224
225 writel(cmdctrl | CMD_EN, host->base + REG_COMMAND);
226
227 if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT)
228 cmd->error = -ETIMEDOUT;
229
230 if (status & RSP_TIMEOUT) {
231 cmd->error = -ETIMEDOUT;
232 return;
233 }
234 if (status & RSP_CRC_FAIL) {
235 cmd->error = -EIO;
236 return;
237 }
238 if (status & RSP_CRC_OK) {
239 if (cmd->flags & MMC_RSP_136) {
240 cmd->resp[3] = readl(host->base + REG_RESPONSE0);
241 cmd->resp[2] = readl(host->base + REG_RESPONSE1);
242 cmd->resp[1] = readl(host->base + REG_RESPONSE2);
243 cmd->resp[0] = readl(host->base + REG_RESPONSE3);
244 } else {
245 cmd->resp[0] = readl(host->base + REG_RESPONSE0);
246 }
247 }
248 }
249
moxart_dma_complete(void * param)250 static void moxart_dma_complete(void *param)
251 {
252 struct moxart_host *host = param;
253
254 complete(&host->dma_complete);
255 }
256
moxart_transfer_dma(struct mmc_data * data,struct moxart_host * host)257 static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host)
258 {
259 u32 len, dir_slave;
260 long dma_time;
261 struct dma_async_tx_descriptor *desc = NULL;
262 struct dma_chan *dma_chan;
263
264 if (host->data_len == data->bytes_xfered)
265 return;
266
267 if (data->flags & MMC_DATA_WRITE) {
268 dma_chan = host->dma_chan_tx;
269 dir_slave = DMA_MEM_TO_DEV;
270 } else {
271 dma_chan = host->dma_chan_rx;
272 dir_slave = DMA_DEV_TO_MEM;
273 }
274
275 len = dma_map_sg(dma_chan->device->dev, data->sg,
276 data->sg_len, mmc_get_dma_dir(data));
277
278 if (len > 0) {
279 desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
280 len, dir_slave,
281 DMA_PREP_INTERRUPT |
282 DMA_CTRL_ACK);
283 } else {
284 dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
285 }
286
287 if (desc) {
288 host->tx_desc = desc;
289 desc->callback = moxart_dma_complete;
290 desc->callback_param = host;
291 dmaengine_submit(desc);
292 dma_async_issue_pending(dma_chan);
293 }
294
295 data->bytes_xfered += host->data_remain;
296
297 dma_time = wait_for_completion_interruptible_timeout(
298 &host->dma_complete, host->timeout);
299
300 dma_unmap_sg(dma_chan->device->dev,
301 data->sg, data->sg_len,
302 mmc_get_dma_dir(data));
303 }
304
305
moxart_transfer_pio(struct moxart_host * host)306 static void moxart_transfer_pio(struct moxart_host *host)
307 {
308 struct mmc_data *data = host->mrq->cmd->data;
309 u32 *sgp, len = 0, remain, status;
310
311 if (host->data_len == data->bytes_xfered)
312 return;
313
314 sgp = sg_virt(host->cur_sg);
315 remain = host->data_remain;
316
317 if (data->flags & MMC_DATA_WRITE) {
318 while (remain > 0) {
319 if (moxart_wait_for_status(host, FIFO_URUN, &status)
320 == -ETIMEDOUT) {
321 data->error = -ETIMEDOUT;
322 complete(&host->pio_complete);
323 return;
324 }
325 for (len = 0; len < remain && len < host->fifo_width;) {
326 iowrite32(*sgp, host->base + REG_DATA_WINDOW);
327 sgp++;
328 len += 4;
329 }
330 remain -= len;
331 }
332
333 } else {
334 while (remain > 0) {
335 if (moxart_wait_for_status(host, FIFO_ORUN, &status)
336 == -ETIMEDOUT) {
337 data->error = -ETIMEDOUT;
338 complete(&host->pio_complete);
339 return;
340 }
341 for (len = 0; len < remain && len < host->fifo_width;) {
342 /* SCR data must be read in big endian. */
343 if (data->mrq->cmd->opcode == SD_APP_SEND_SCR)
344 *sgp = ioread32be(host->base +
345 REG_DATA_WINDOW);
346 else
347 *sgp = ioread32(host->base +
348 REG_DATA_WINDOW);
349 sgp++;
350 len += 4;
351 }
352 remain -= len;
353 }
354 }
355
356 data->bytes_xfered += host->data_remain - remain;
357 host->data_remain = remain;
358
359 if (host->data_len != data->bytes_xfered)
360 moxart_next_sg(host);
361 else
362 complete(&host->pio_complete);
363 }
364
moxart_prepare_data(struct moxart_host * host)365 static void moxart_prepare_data(struct moxart_host *host)
366 {
367 struct mmc_data *data = host->mrq->cmd->data;
368 u32 datactrl;
369 int blksz_bits;
370
371 if (!data)
372 return;
373
374 host->data_len = data->blocks * data->blksz;
375 blksz_bits = ffs(data->blksz) - 1;
376 BUG_ON(1 << blksz_bits != data->blksz);
377
378 moxart_init_sg(host, data);
379
380 datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE);
381
382 if (data->flags & MMC_DATA_WRITE)
383 datactrl |= DCR_DATA_WRITE;
384
385 if ((host->data_len > host->fifo_width) && host->have_dma)
386 datactrl |= DCR_DMA_EN;
387
388 writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL);
389 writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR);
390 writel(host->rate, host->base + REG_DATA_TIMER);
391 writel(host->data_len, host->base + REG_DATA_LENGTH);
392 writel(datactrl, host->base + REG_DATA_CONTROL);
393 }
394
moxart_request(struct mmc_host * mmc,struct mmc_request * mrq)395 static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq)
396 {
397 struct moxart_host *host = mmc_priv(mmc);
398 long pio_time;
399 unsigned long flags;
400 u32 status;
401
402 spin_lock_irqsave(&host->lock, flags);
403
404 init_completion(&host->dma_complete);
405 init_completion(&host->pio_complete);
406
407 host->mrq = mrq;
408
409 if (readl(host->base + REG_STATUS) & CARD_DETECT) {
410 mrq->cmd->error = -ETIMEDOUT;
411 goto request_done;
412 }
413
414 moxart_prepare_data(host);
415 moxart_send_command(host, host->mrq->cmd);
416
417 if (mrq->cmd->data) {
418 if ((host->data_len > host->fifo_width) && host->have_dma) {
419
420 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
421
422 spin_unlock_irqrestore(&host->lock, flags);
423
424 moxart_transfer_dma(mrq->cmd->data, host);
425
426 spin_lock_irqsave(&host->lock, flags);
427 } else {
428
429 writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK);
430
431 spin_unlock_irqrestore(&host->lock, flags);
432
433 /* PIO transfers start from interrupt. */
434 pio_time = wait_for_completion_interruptible_timeout(
435 &host->pio_complete, host->timeout);
436
437 spin_lock_irqsave(&host->lock, flags);
438 }
439
440 if (host->is_removed) {
441 dev_err(mmc_dev(host->mmc), "card removed\n");
442 mrq->cmd->error = -ETIMEDOUT;
443 goto request_done;
444 }
445
446 if (moxart_wait_for_status(host, MASK_DATA, &status)
447 == -ETIMEDOUT) {
448 mrq->cmd->data->error = -ETIMEDOUT;
449 goto request_done;
450 }
451
452 if (status & DATA_CRC_FAIL)
453 mrq->cmd->data->error = -ETIMEDOUT;
454
455 if (mrq->cmd->data->stop)
456 moxart_send_command(host, mrq->cmd->data->stop);
457 }
458
459 request_done:
460 spin_unlock_irqrestore(&host->lock, flags);
461 mmc_request_done(host->mmc, mrq);
462 }
463
moxart_irq(int irq,void * devid)464 static irqreturn_t moxart_irq(int irq, void *devid)
465 {
466 struct moxart_host *host = (struct moxart_host *)devid;
467 u32 status;
468 unsigned long flags;
469
470 spin_lock_irqsave(&host->lock, flags);
471
472 status = readl(host->base + REG_STATUS);
473 if (status & CARD_CHANGE) {
474 host->is_removed = status & CARD_DETECT;
475 if (host->is_removed && host->have_dma) {
476 dmaengine_terminate_all(host->dma_chan_tx);
477 dmaengine_terminate_all(host->dma_chan_rx);
478 }
479 host->mrq = NULL;
480 writel(MASK_INTR_PIO, host->base + REG_CLEAR);
481 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);
482 mmc_detect_change(host->mmc, 0);
483 }
484 if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq)
485 moxart_transfer_pio(host);
486
487 spin_unlock_irqrestore(&host->lock, flags);
488
489 return IRQ_HANDLED;
490 }
491
moxart_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)492 static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
493 {
494 struct moxart_host *host = mmc_priv(mmc);
495 unsigned long flags;
496 u8 power, div;
497 u32 ctrl;
498
499 spin_lock_irqsave(&host->lock, flags);
500
501 if (ios->clock) {
502 for (div = 0; div < CLK_DIV_MASK; ++div) {
503 if (ios->clock >= host->sysclk / (2 * (div + 1)))
504 break;
505 }
506 ctrl = CLK_SD | div;
507 host->rate = host->sysclk / (2 * (div + 1));
508 if (host->rate > host->sysclk)
509 ctrl |= CLK_HISPD;
510 writel(ctrl, host->base + REG_CLOCK_CONTROL);
511 }
512
513 if (ios->power_mode == MMC_POWER_OFF) {
514 writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON,
515 host->base + REG_POWER_CONTROL);
516 } else {
517 if (ios->vdd < MIN_POWER)
518 power = 0;
519 else
520 power = ios->vdd - MIN_POWER;
521
522 writel(SD_POWER_ON | (u32) power,
523 host->base + REG_POWER_CONTROL);
524 }
525
526 switch (ios->bus_width) {
527 case MMC_BUS_WIDTH_4:
528 writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH);
529 break;
530 case MMC_BUS_WIDTH_8:
531 writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH);
532 break;
533 default:
534 writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH);
535 break;
536 }
537
538 spin_unlock_irqrestore(&host->lock, flags);
539 }
540
541
moxart_get_ro(struct mmc_host * mmc)542 static int moxart_get_ro(struct mmc_host *mmc)
543 {
544 struct moxart_host *host = mmc_priv(mmc);
545
546 return !!(readl(host->base + REG_STATUS) & WRITE_PROT);
547 }
548
549 static const struct mmc_host_ops moxart_ops = {
550 .request = moxart_request,
551 .set_ios = moxart_set_ios,
552 .get_ro = moxart_get_ro,
553 };
554
moxart_probe(struct platform_device * pdev)555 static int moxart_probe(struct platform_device *pdev)
556 {
557 struct device *dev = &pdev->dev;
558 struct device_node *node = dev->of_node;
559 struct resource res_mmc;
560 struct mmc_host *mmc;
561 struct moxart_host *host = NULL;
562 struct dma_slave_config cfg;
563 struct clk *clk;
564 void __iomem *reg_mmc;
565 int irq, ret;
566 u32 i;
567
568 mmc = mmc_alloc_host(sizeof(struct moxart_host), dev);
569 if (!mmc) {
570 dev_err(dev, "mmc_alloc_host failed\n");
571 ret = -ENOMEM;
572 goto out;
573 }
574
575 ret = of_address_to_resource(node, 0, &res_mmc);
576 if (ret) {
577 dev_err(dev, "of_address_to_resource failed\n");
578 goto out;
579 }
580
581 irq = irq_of_parse_and_map(node, 0);
582 if (irq <= 0) {
583 dev_err(dev, "irq_of_parse_and_map failed\n");
584 ret = -EINVAL;
585 goto out;
586 }
587
588 clk = devm_clk_get(dev, NULL);
589 if (IS_ERR(clk)) {
590 ret = PTR_ERR(clk);
591 goto out;
592 }
593
594 reg_mmc = devm_ioremap_resource(dev, &res_mmc);
595 if (IS_ERR(reg_mmc)) {
596 ret = PTR_ERR(reg_mmc);
597 goto out;
598 }
599
600 ret = mmc_of_parse(mmc);
601 if (ret)
602 goto out;
603
604 host = mmc_priv(mmc);
605 host->mmc = mmc;
606 host->base = reg_mmc;
607 host->reg_phys = res_mmc.start;
608 host->timeout = msecs_to_jiffies(1000);
609 host->sysclk = clk_get_rate(clk);
610 host->fifo_width = readl(host->base + REG_FEATURE) << 2;
611 host->dma_chan_tx = dma_request_chan(dev, "tx");
612 host->dma_chan_rx = dma_request_chan(dev, "rx");
613
614 spin_lock_init(&host->lock);
615
616 mmc->ops = &moxart_ops;
617 mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2);
618 mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2);
619 mmc->ocr_avail = 0xffff00; /* Support 2.0v - 3.6v power. */
620
621 if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) {
622 if (PTR_ERR(host->dma_chan_tx) == -EPROBE_DEFER ||
623 PTR_ERR(host->dma_chan_rx) == -EPROBE_DEFER) {
624 ret = -EPROBE_DEFER;
625 goto out;
626 }
627 dev_dbg(dev, "PIO mode transfer enabled\n");
628 host->have_dma = false;
629 } else {
630 dev_dbg(dev, "DMA channels found (%p,%p)\n",
631 host->dma_chan_tx, host->dma_chan_rx);
632 host->have_dma = true;
633
634 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
635 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
636
637 cfg.direction = DMA_MEM_TO_DEV;
638 cfg.src_addr = 0;
639 cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW;
640 dmaengine_slave_config(host->dma_chan_tx, &cfg);
641
642 cfg.direction = DMA_DEV_TO_MEM;
643 cfg.src_addr = host->reg_phys + REG_DATA_WINDOW;
644 cfg.dst_addr = 0;
645 dmaengine_slave_config(host->dma_chan_rx, &cfg);
646 }
647
648 switch ((readl(host->base + REG_BUS_WIDTH) >> 3) & 3) {
649 case 1:
650 mmc->caps |= MMC_CAP_4_BIT_DATA;
651 break;
652 case 2:
653 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
654 break;
655 default:
656 break;
657 }
658
659 writel(0, host->base + REG_INTERRUPT_MASK);
660
661 writel(CMD_SDC_RESET, host->base + REG_COMMAND);
662 for (i = 0; i < MAX_RETRIES; i++) {
663 if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET))
664 break;
665 udelay(5);
666 }
667
668 ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host);
669 if (ret)
670 goto out;
671
672 dev_set_drvdata(dev, mmc);
673 mmc_add_host(mmc);
674
675 dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width);
676
677 return 0;
678
679 out:
680 if (mmc)
681 mmc_free_host(mmc);
682 return ret;
683 }
684
moxart_remove(struct platform_device * pdev)685 static int moxart_remove(struct platform_device *pdev)
686 {
687 struct mmc_host *mmc = dev_get_drvdata(&pdev->dev);
688 struct moxart_host *host = mmc_priv(mmc);
689
690 dev_set_drvdata(&pdev->dev, NULL);
691
692 if (!IS_ERR(host->dma_chan_tx))
693 dma_release_channel(host->dma_chan_tx);
694 if (!IS_ERR(host->dma_chan_rx))
695 dma_release_channel(host->dma_chan_rx);
696 mmc_remove_host(mmc);
697 mmc_free_host(mmc);
698
699 writel(0, host->base + REG_INTERRUPT_MASK);
700 writel(0, host->base + REG_POWER_CONTROL);
701 writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF,
702 host->base + REG_CLOCK_CONTROL);
703
704 return 0;
705 }
706
707 static const struct of_device_id moxart_mmc_match[] = {
708 { .compatible = "moxa,moxart-mmc" },
709 { .compatible = "faraday,ftsdc010" },
710 { }
711 };
712 MODULE_DEVICE_TABLE(of, moxart_mmc_match);
713
714 static struct platform_driver moxart_mmc_driver = {
715 .probe = moxart_probe,
716 .remove = moxart_remove,
717 .driver = {
718 .name = "mmc-moxart",
719 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
720 .of_match_table = moxart_mmc_match,
721 },
722 };
723 module_platform_driver(moxart_mmc_driver);
724
725 MODULE_ALIAS("platform:mmc-moxart");
726 MODULE_DESCRIPTION("MOXA ART MMC driver");
727 MODULE_LICENSE("GPL v2");
728 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>");
729
