1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015-2016 MediaTek Inc.
4 * Author: Yong Wu <yong.wu@mediatek.com>
5 */
6 #include <linux/clk.h>
7 #include <linux/component.h>
8 #include <linux/device.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_platform.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <soc/mediatek/smi.h>
17 #include <dt-bindings/memory/mt2701-larb-port.h>
18
19 /* mt8173 */
20 #define SMI_LARB_MMU_EN 0xf00
21
22 /* mt8167 */
23 #define MT8167_SMI_LARB_MMU_EN 0xfc0
24
25 /* mt2701 */
26 #define REG_SMI_SECUR_CON_BASE 0x5c0
27
28 /* every register control 8 port, register offset 0x4 */
29 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2)
30 #define REG_SMI_SECUR_CON_ADDR(id) \
31 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
32
33 /*
34 * every port have 4 bit to control, bit[port + 3] control virtual or physical,
35 * bit[port + 2 : port + 1] control the domain, bit[port] control the security
36 * or non-security.
37 */
38 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2)))
39 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3)
40 /* mt2701 domain should be set to 3 */
41 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1))
42
43 /* mt2712 */
44 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4))
45 #define F_MMU_EN BIT(0)
46
47 /* SMI COMMON */
48 #define SMI_BUS_SEL 0x220
49 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1)
50 /* All are MMU0 defaultly. Only specialize mmu1 here. */
51 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid))
52
53 enum mtk_smi_gen {
54 MTK_SMI_GEN1,
55 MTK_SMI_GEN2
56 };
57
58 struct mtk_smi_common_plat {
59 enum mtk_smi_gen gen;
60 bool has_gals;
61 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
62 };
63
64 struct mtk_smi_larb_gen {
65 int port_in_larb[MTK_LARB_NR_MAX + 1];
66 void (*config_port)(struct device *dev);
67 unsigned int larb_direct_to_common_mask;
68 bool has_gals;
69 };
70
71 struct mtk_smi {
72 struct device *dev;
73 struct clk *clk_apb, *clk_smi;
74 struct clk *clk_gals0, *clk_gals1;
75 struct clk *clk_async; /*only needed by mt2701*/
76 union {
77 void __iomem *smi_ao_base; /* only for gen1 */
78 void __iomem *base; /* only for gen2 */
79 };
80 const struct mtk_smi_common_plat *plat;
81 };
82
83 struct mtk_smi_larb { /* larb: local arbiter */
84 struct mtk_smi smi;
85 void __iomem *base;
86 struct device *smi_common_dev;
87 const struct mtk_smi_larb_gen *larb_gen;
88 int larbid;
89 u32 *mmu;
90 };
91
mtk_smi_clk_enable(const struct mtk_smi * smi)92 static int mtk_smi_clk_enable(const struct mtk_smi *smi)
93 {
94 int ret;
95
96 ret = clk_prepare_enable(smi->clk_apb);
97 if (ret)
98 return ret;
99
100 ret = clk_prepare_enable(smi->clk_smi);
101 if (ret)
102 goto err_disable_apb;
103
104 ret = clk_prepare_enable(smi->clk_gals0);
105 if (ret)
106 goto err_disable_smi;
107
108 ret = clk_prepare_enable(smi->clk_gals1);
109 if (ret)
110 goto err_disable_gals0;
111
112 return 0;
113
114 err_disable_gals0:
115 clk_disable_unprepare(smi->clk_gals0);
116 err_disable_smi:
117 clk_disable_unprepare(smi->clk_smi);
118 err_disable_apb:
119 clk_disable_unprepare(smi->clk_apb);
120 return ret;
121 }
122
mtk_smi_clk_disable(const struct mtk_smi * smi)123 static void mtk_smi_clk_disable(const struct mtk_smi *smi)
124 {
125 clk_disable_unprepare(smi->clk_gals1);
126 clk_disable_unprepare(smi->clk_gals0);
127 clk_disable_unprepare(smi->clk_smi);
128 clk_disable_unprepare(smi->clk_apb);
129 }
130
mtk_smi_larb_get(struct device * larbdev)131 int mtk_smi_larb_get(struct device *larbdev)
132 {
133 int ret = pm_runtime_get_sync(larbdev);
134
135 return (ret < 0) ? ret : 0;
136 }
137 EXPORT_SYMBOL_GPL(mtk_smi_larb_get);
138
mtk_smi_larb_put(struct device * larbdev)139 void mtk_smi_larb_put(struct device *larbdev)
140 {
141 pm_runtime_put_sync(larbdev);
142 }
143 EXPORT_SYMBOL_GPL(mtk_smi_larb_put);
144
145 static int
mtk_smi_larb_bind(struct device * dev,struct device * master,void * data)146 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
147 {
148 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
149 struct mtk_smi_larb_iommu *larb_mmu = data;
150 unsigned int i;
151
152 for (i = 0; i < MTK_LARB_NR_MAX; i++) {
153 if (dev == larb_mmu[i].dev) {
154 larb->larbid = i;
155 larb->mmu = &larb_mmu[i].mmu;
156 return 0;
157 }
158 }
159 return -ENODEV;
160 }
161
mtk_smi_larb_config_port_gen2_general(struct device * dev)162 static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
163 {
164 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
165 u32 reg;
166 int i;
167
168 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
169 return;
170
171 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
172 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
173 reg |= F_MMU_EN;
174 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
175 }
176 }
177
mtk_smi_larb_config_port_mt8173(struct device * dev)178 static void mtk_smi_larb_config_port_mt8173(struct device *dev)
179 {
180 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
181
182 writel(*larb->mmu, larb->base + SMI_LARB_MMU_EN);
183 }
184
mtk_smi_larb_config_port_mt8167(struct device * dev)185 static void mtk_smi_larb_config_port_mt8167(struct device *dev)
186 {
187 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
188
189 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
190 }
191
mtk_smi_larb_config_port_gen1(struct device * dev)192 static void mtk_smi_larb_config_port_gen1(struct device *dev)
193 {
194 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
195 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
196 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
197 int i, m4u_port_id, larb_port_num;
198 u32 sec_con_val, reg_val;
199
200 m4u_port_id = larb_gen->port_in_larb[larb->larbid];
201 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
202 - larb_gen->port_in_larb[larb->larbid];
203
204 for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
205 if (*larb->mmu & BIT(i)) {
206 /* bit[port + 3] controls the virtual or physical */
207 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
208 } else {
209 /* do not need to enable m4u for this port */
210 continue;
211 }
212 reg_val = readl(common->smi_ao_base
213 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
214 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
215 reg_val |= sec_con_val;
216 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
217 writel(reg_val,
218 common->smi_ao_base
219 + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
220 }
221 }
222
223 static void
mtk_smi_larb_unbind(struct device * dev,struct device * master,void * data)224 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
225 {
226 /* Do nothing as the iommu is always enabled. */
227 }
228
229 static const struct component_ops mtk_smi_larb_component_ops = {
230 .bind = mtk_smi_larb_bind,
231 .unbind = mtk_smi_larb_unbind,
232 };
233
234 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
235 /* mt8173 do not need the port in larb */
236 .config_port = mtk_smi_larb_config_port_mt8173,
237 };
238
239 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
240 /* mt8167 do not need the port in larb */
241 .config_port = mtk_smi_larb_config_port_mt8167,
242 };
243
244 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
245 .port_in_larb = {
246 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
247 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
248 },
249 .config_port = mtk_smi_larb_config_port_gen1,
250 };
251
252 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
253 .config_port = mtk_smi_larb_config_port_gen2_general,
254 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */
255 };
256
257 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
258 .config_port = mtk_smi_larb_config_port_gen2_general,
259 .larb_direct_to_common_mask =
260 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
261 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
262 };
263
264 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
265 .has_gals = true,
266 .config_port = mtk_smi_larb_config_port_gen2_general,
267 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
268 /* IPU0 | IPU1 | CCU */
269 };
270
271 static const struct of_device_id mtk_smi_larb_of_ids[] = {
272 {
273 .compatible = "mediatek,mt8167-smi-larb",
274 .data = &mtk_smi_larb_mt8167
275 },
276 {
277 .compatible = "mediatek,mt8173-smi-larb",
278 .data = &mtk_smi_larb_mt8173
279 },
280 {
281 .compatible = "mediatek,mt2701-smi-larb",
282 .data = &mtk_smi_larb_mt2701
283 },
284 {
285 .compatible = "mediatek,mt2712-smi-larb",
286 .data = &mtk_smi_larb_mt2712
287 },
288 {
289 .compatible = "mediatek,mt6779-smi-larb",
290 .data = &mtk_smi_larb_mt6779
291 },
292 {
293 .compatible = "mediatek,mt8183-smi-larb",
294 .data = &mtk_smi_larb_mt8183
295 },
296 {}
297 };
298
mtk_smi_larb_probe(struct platform_device * pdev)299 static int mtk_smi_larb_probe(struct platform_device *pdev)
300 {
301 struct mtk_smi_larb *larb;
302 struct resource *res;
303 struct device *dev = &pdev->dev;
304 struct device_node *smi_node;
305 struct platform_device *smi_pdev;
306
307 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
308 if (!larb)
309 return -ENOMEM;
310
311 larb->larb_gen = of_device_get_match_data(dev);
312 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
313 larb->base = devm_ioremap_resource(dev, res);
314 if (IS_ERR(larb->base))
315 return PTR_ERR(larb->base);
316
317 larb->smi.clk_apb = devm_clk_get(dev, "apb");
318 if (IS_ERR(larb->smi.clk_apb))
319 return PTR_ERR(larb->smi.clk_apb);
320
321 larb->smi.clk_smi = devm_clk_get(dev, "smi");
322 if (IS_ERR(larb->smi.clk_smi))
323 return PTR_ERR(larb->smi.clk_smi);
324
325 if (larb->larb_gen->has_gals) {
326 /* The larbs may still haven't gals even if the SoC support.*/
327 larb->smi.clk_gals0 = devm_clk_get(dev, "gals");
328 if (PTR_ERR(larb->smi.clk_gals0) == -ENOENT)
329 larb->smi.clk_gals0 = NULL;
330 else if (IS_ERR(larb->smi.clk_gals0))
331 return PTR_ERR(larb->smi.clk_gals0);
332 }
333 larb->smi.dev = dev;
334
335 smi_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
336 if (!smi_node)
337 return -EINVAL;
338
339 smi_pdev = of_find_device_by_node(smi_node);
340 of_node_put(smi_node);
341 if (smi_pdev) {
342 if (!platform_get_drvdata(smi_pdev))
343 return -EPROBE_DEFER;
344 larb->smi_common_dev = &smi_pdev->dev;
345 } else {
346 dev_err(dev, "Failed to get the smi_common device\n");
347 return -EINVAL;
348 }
349
350 pm_runtime_enable(dev);
351 platform_set_drvdata(pdev, larb);
352 return component_add(dev, &mtk_smi_larb_component_ops);
353 }
354
mtk_smi_larb_remove(struct platform_device * pdev)355 static int mtk_smi_larb_remove(struct platform_device *pdev)
356 {
357 pm_runtime_disable(&pdev->dev);
358 component_del(&pdev->dev, &mtk_smi_larb_component_ops);
359 return 0;
360 }
361
mtk_smi_larb_resume(struct device * dev)362 static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
363 {
364 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
365 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
366 int ret;
367
368 /* Power on smi-common. */
369 ret = pm_runtime_get_sync(larb->smi_common_dev);
370 if (ret < 0) {
371 dev_err(dev, "Failed to pm get for smi-common(%d).\n", ret);
372 return ret;
373 }
374
375 ret = mtk_smi_clk_enable(&larb->smi);
376 if (ret < 0) {
377 dev_err(dev, "Failed to enable clock(%d).\n", ret);
378 pm_runtime_put_sync(larb->smi_common_dev);
379 return ret;
380 }
381
382 /* Configure the basic setting for this larb */
383 larb_gen->config_port(dev);
384
385 return 0;
386 }
387
mtk_smi_larb_suspend(struct device * dev)388 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
389 {
390 struct mtk_smi_larb *larb = dev_get_drvdata(dev);
391
392 mtk_smi_clk_disable(&larb->smi);
393 pm_runtime_put_sync(larb->smi_common_dev);
394 return 0;
395 }
396
397 static const struct dev_pm_ops smi_larb_pm_ops = {
398 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
399 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
400 pm_runtime_force_resume)
401 };
402
403 static struct platform_driver mtk_smi_larb_driver = {
404 .probe = mtk_smi_larb_probe,
405 .remove = mtk_smi_larb_remove,
406 .driver = {
407 .name = "mtk-smi-larb",
408 .of_match_table = mtk_smi_larb_of_ids,
409 .pm = &smi_larb_pm_ops,
410 }
411 };
412
413 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
414 .gen = MTK_SMI_GEN1,
415 };
416
417 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
418 .gen = MTK_SMI_GEN2,
419 };
420
421 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
422 .gen = MTK_SMI_GEN2,
423 .has_gals = true,
424 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
425 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
426 };
427
428 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
429 .gen = MTK_SMI_GEN2,
430 .has_gals = true,
431 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
432 F_MMU1_LARB(7),
433 };
434
435 static const struct of_device_id mtk_smi_common_of_ids[] = {
436 {
437 .compatible = "mediatek,mt8173-smi-common",
438 .data = &mtk_smi_common_gen2,
439 },
440 {
441 .compatible = "mediatek,mt8167-smi-common",
442 .data = &mtk_smi_common_gen2,
443 },
444 {
445 .compatible = "mediatek,mt2701-smi-common",
446 .data = &mtk_smi_common_gen1,
447 },
448 {
449 .compatible = "mediatek,mt2712-smi-common",
450 .data = &mtk_smi_common_gen2,
451 },
452 {
453 .compatible = "mediatek,mt6779-smi-common",
454 .data = &mtk_smi_common_mt6779,
455 },
456 {
457 .compatible = "mediatek,mt8183-smi-common",
458 .data = &mtk_smi_common_mt8183,
459 },
460 {}
461 };
462
mtk_smi_common_probe(struct platform_device * pdev)463 static int mtk_smi_common_probe(struct platform_device *pdev)
464 {
465 struct device *dev = &pdev->dev;
466 struct mtk_smi *common;
467 struct resource *res;
468 int ret;
469
470 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
471 if (!common)
472 return -ENOMEM;
473 common->dev = dev;
474 common->plat = of_device_get_match_data(dev);
475
476 common->clk_apb = devm_clk_get(dev, "apb");
477 if (IS_ERR(common->clk_apb))
478 return PTR_ERR(common->clk_apb);
479
480 common->clk_smi = devm_clk_get(dev, "smi");
481 if (IS_ERR(common->clk_smi))
482 return PTR_ERR(common->clk_smi);
483
484 if (common->plat->has_gals) {
485 common->clk_gals0 = devm_clk_get(dev, "gals0");
486 if (IS_ERR(common->clk_gals0))
487 return PTR_ERR(common->clk_gals0);
488
489 common->clk_gals1 = devm_clk_get(dev, "gals1");
490 if (IS_ERR(common->clk_gals1))
491 return PTR_ERR(common->clk_gals1);
492 }
493
494 /*
495 * for mtk smi gen 1, we need to get the ao(always on) base to config
496 * m4u port, and we need to enable the aync clock for transform the smi
497 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
498 * base.
499 */
500 if (common->plat->gen == MTK_SMI_GEN1) {
501 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
502 common->smi_ao_base = devm_ioremap_resource(dev, res);
503 if (IS_ERR(common->smi_ao_base))
504 return PTR_ERR(common->smi_ao_base);
505
506 common->clk_async = devm_clk_get(dev, "async");
507 if (IS_ERR(common->clk_async))
508 return PTR_ERR(common->clk_async);
509
510 ret = clk_prepare_enable(common->clk_async);
511 if (ret)
512 return ret;
513 } else {
514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
515 common->base = devm_ioremap_resource(dev, res);
516 if (IS_ERR(common->base))
517 return PTR_ERR(common->base);
518 }
519 pm_runtime_enable(dev);
520 platform_set_drvdata(pdev, common);
521 return 0;
522 }
523
mtk_smi_common_remove(struct platform_device * pdev)524 static int mtk_smi_common_remove(struct platform_device *pdev)
525 {
526 pm_runtime_disable(&pdev->dev);
527 return 0;
528 }
529
mtk_smi_common_resume(struct device * dev)530 static int __maybe_unused mtk_smi_common_resume(struct device *dev)
531 {
532 struct mtk_smi *common = dev_get_drvdata(dev);
533 u32 bus_sel = common->plat->bus_sel;
534 int ret;
535
536 ret = mtk_smi_clk_enable(common);
537 if (ret) {
538 dev_err(common->dev, "Failed to enable clock(%d).\n", ret);
539 return ret;
540 }
541
542 if (common->plat->gen == MTK_SMI_GEN2 && bus_sel)
543 writel(bus_sel, common->base + SMI_BUS_SEL);
544 return 0;
545 }
546
mtk_smi_common_suspend(struct device * dev)547 static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
548 {
549 struct mtk_smi *common = dev_get_drvdata(dev);
550
551 mtk_smi_clk_disable(common);
552 return 0;
553 }
554
555 static const struct dev_pm_ops smi_common_pm_ops = {
556 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
557 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
558 pm_runtime_force_resume)
559 };
560
561 static struct platform_driver mtk_smi_common_driver = {
562 .probe = mtk_smi_common_probe,
563 .remove = mtk_smi_common_remove,
564 .driver = {
565 .name = "mtk-smi-common",
566 .of_match_table = mtk_smi_common_of_ids,
567 .pm = &smi_common_pm_ops,
568 }
569 };
570
mtk_smi_init(void)571 static int __init mtk_smi_init(void)
572 {
573 int ret;
574
575 ret = platform_driver_register(&mtk_smi_common_driver);
576 if (ret != 0) {
577 pr_err("Failed to register SMI driver\n");
578 return ret;
579 }
580
581 ret = platform_driver_register(&mtk_smi_larb_driver);
582 if (ret != 0) {
583 pr_err("Failed to register SMI-LARB driver\n");
584 goto err_unreg_smi;
585 }
586 return ret;
587
588 err_unreg_smi:
589 platform_driver_unregister(&mtk_smi_common_driver);
590 return ret;
591 }
592
593 module_init(mtk_smi_init);
594
