1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * R-Car Gen3 Digital Radio Interface (DRIF) driver
4 *
5 * Copyright (C) 2017 Renesas Electronics Corporation
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13 /*
14 * The R-Car DRIF is a receive only MSIOF like controller with an
15 * external master device driving the SCK. It receives data into a FIFO,
16 * then this driver uses the SYS-DMAC engine to move the data from
17 * the device to memory.
18 *
19 * Each DRIF channel DRIFx (as per datasheet) contains two internal
20 * channels DRIFx0 & DRIFx1 within itself with each having its own resources
21 * like module clk, register set, irq and dma. These internal channels share
22 * common CLK & SYNC from master. The two data pins D0 & D1 shall be
23 * considered to represent the two internal channels. This internal split
24 * is not visible to the master device.
25 *
26 * Depending on the master device, a DRIF channel can use
27 * (1) both internal channels (D0 & D1) to receive data in parallel (or)
28 * (2) one internal channel (D0 or D1) to receive data
29 *
30 * The primary design goal of this controller is to act as a Digital Radio
31 * Interface that receives digital samples from a tuner device. Hence the
32 * driver exposes the device as a V4L2 SDR device. In order to qualify as
33 * a V4L2 SDR device, it should possess a tuner interface as mandated by the
34 * framework. This driver expects a tuner driver (sub-device) to bind
35 * asynchronously with this device and the combined drivers shall expose
36 * a V4L2 compliant SDR device. The DRIF driver is independent of the
37 * tuner vendor.
38 *
39 * The DRIF h/w can support I2S mode and Frame start synchronization pulse mode.
40 * This driver is tested for I2S mode only because of the availability of
41 * suitable master devices. Hence, not all configurable options of DRIF h/w
42 * like lsb/msb first, syncdl, dtdl etc. are exposed via DT and I2S defaults
43 * are used. These can be exposed later if needed after testing.
44 */
45 #include <linux/bitops.h>
46 #include <linux/clk.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/dmaengine.h>
49 #include <linux/ioctl.h>
50 #include <linux/iopoll.h>
51 #include <linux/module.h>
52 #include <linux/of_graph.h>
53 #include <linux/of_device.h>
54 #include <linux/platform_device.h>
55 #include <linux/sched.h>
56 #include <media/v4l2-async.h>
57 #include <media/v4l2-ctrls.h>
58 #include <media/v4l2-device.h>
59 #include <media/v4l2-event.h>
60 #include <media/v4l2-fh.h>
61 #include <media/v4l2-ioctl.h>
62 #include <media/videobuf2-v4l2.h>
63 #include <media/videobuf2-vmalloc.h>
64
65 /* DRIF register offsets */
66 #define RCAR_DRIF_SITMDR1 0x00
67 #define RCAR_DRIF_SITMDR2 0x04
68 #define RCAR_DRIF_SITMDR3 0x08
69 #define RCAR_DRIF_SIRMDR1 0x10
70 #define RCAR_DRIF_SIRMDR2 0x14
71 #define RCAR_DRIF_SIRMDR3 0x18
72 #define RCAR_DRIF_SICTR 0x28
73 #define RCAR_DRIF_SIFCTR 0x30
74 #define RCAR_DRIF_SISTR 0x40
75 #define RCAR_DRIF_SIIER 0x44
76 #define RCAR_DRIF_SIRFDR 0x60
77
78 #define RCAR_DRIF_RFOVF BIT(3) /* Receive FIFO overflow */
79 #define RCAR_DRIF_RFUDF BIT(4) /* Receive FIFO underflow */
80 #define RCAR_DRIF_RFSERR BIT(5) /* Receive frame sync error */
81 #define RCAR_DRIF_REOF BIT(7) /* Frame reception end */
82 #define RCAR_DRIF_RDREQ BIT(12) /* Receive data xfer req */
83 #define RCAR_DRIF_RFFUL BIT(13) /* Receive FIFO full */
84
85 /* SIRMDR1 */
86 #define RCAR_DRIF_SIRMDR1_SYNCMD_FRAME (0 << 28)
87 #define RCAR_DRIF_SIRMDR1_SYNCMD_LR (3 << 28)
88
89 #define RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH (0 << 25)
90 #define RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW (1 << 25)
91
92 #define RCAR_DRIF_SIRMDR1_MSB_FIRST (0 << 24)
93 #define RCAR_DRIF_SIRMDR1_LSB_FIRST (1 << 24)
94
95 #define RCAR_DRIF_SIRMDR1_DTDL_0 (0 << 20)
96 #define RCAR_DRIF_SIRMDR1_DTDL_1 (1 << 20)
97 #define RCAR_DRIF_SIRMDR1_DTDL_2 (2 << 20)
98 #define RCAR_DRIF_SIRMDR1_DTDL_0PT5 (5 << 20)
99 #define RCAR_DRIF_SIRMDR1_DTDL_1PT5 (6 << 20)
100
101 #define RCAR_DRIF_SIRMDR1_SYNCDL_0 (0 << 20)
102 #define RCAR_DRIF_SIRMDR1_SYNCDL_1 (1 << 20)
103 #define RCAR_DRIF_SIRMDR1_SYNCDL_2 (2 << 20)
104 #define RCAR_DRIF_SIRMDR1_SYNCDL_3 (3 << 20)
105 #define RCAR_DRIF_SIRMDR1_SYNCDL_0PT5 (5 << 20)
106 #define RCAR_DRIF_SIRMDR1_SYNCDL_1PT5 (6 << 20)
107
108 #define RCAR_DRIF_MDR_GRPCNT(n) (((n) - 1) << 30)
109 #define RCAR_DRIF_MDR_BITLEN(n) (((n) - 1) << 24)
110 #define RCAR_DRIF_MDR_WDCNT(n) (((n) - 1) << 16)
111
112 /* Hidden Transmit register that controls CLK & SYNC */
113 #define RCAR_DRIF_SITMDR1_PCON BIT(30)
114
115 #define RCAR_DRIF_SICTR_RX_RISING_EDGE BIT(26)
116 #define RCAR_DRIF_SICTR_RX_EN BIT(8)
117 #define RCAR_DRIF_SICTR_RESET BIT(0)
118
119 /* Constants */
120 #define RCAR_DRIF_NUM_HWBUFS 32
121 #define RCAR_DRIF_MAX_DEVS 4
122 #define RCAR_DRIF_DEFAULT_NUM_HWBUFS 16
123 #define RCAR_DRIF_DEFAULT_HWBUF_SIZE (4 * PAGE_SIZE)
124 #define RCAR_DRIF_MAX_CHANNEL 2
125 #define RCAR_SDR_BUFFER_SIZE SZ_64K
126
127 /* Internal buffer status flags */
128 #define RCAR_DRIF_BUF_DONE BIT(0) /* DMA completed */
129 #define RCAR_DRIF_BUF_OVERFLOW BIT(1) /* Overflow detected */
130
131 #define to_rcar_drif_buf_pair(sdr, ch_num, idx) \
132 (&((sdr)->ch[!(ch_num)]->buf[(idx)]))
133
134 #define for_each_rcar_drif_channel(ch, ch_mask) \
135 for_each_set_bit(ch, ch_mask, RCAR_DRIF_MAX_CHANNEL)
136
137 /* Debug */
138 #define rdrif_dbg(sdr, fmt, arg...) \
139 dev_dbg(sdr->v4l2_dev.dev, fmt, ## arg)
140
141 #define rdrif_err(sdr, fmt, arg...) \
142 dev_err(sdr->v4l2_dev.dev, fmt, ## arg)
143
144 /* Stream formats */
145 struct rcar_drif_format {
146 u32 pixelformat;
147 u32 buffersize;
148 u32 bitlen;
149 u32 wdcnt;
150 u32 num_ch;
151 };
152
153 /* Format descriptions for capture */
154 static const struct rcar_drif_format formats[] = {
155 {
156 .pixelformat = V4L2_SDR_FMT_PCU16BE,
157 .buffersize = RCAR_SDR_BUFFER_SIZE,
158 .bitlen = 16,
159 .wdcnt = 1,
160 .num_ch = 2,
161 },
162 {
163 .pixelformat = V4L2_SDR_FMT_PCU18BE,
164 .buffersize = RCAR_SDR_BUFFER_SIZE,
165 .bitlen = 18,
166 .wdcnt = 1,
167 .num_ch = 2,
168 },
169 {
170 .pixelformat = V4L2_SDR_FMT_PCU20BE,
171 .buffersize = RCAR_SDR_BUFFER_SIZE,
172 .bitlen = 20,
173 .wdcnt = 1,
174 .num_ch = 2,
175 },
176 };
177
178 /* Buffer for a received frame from one or both internal channels */
179 struct rcar_drif_frame_buf {
180 /* Common v4l buffer stuff -- must be first */
181 struct vb2_v4l2_buffer vb;
182 struct list_head list;
183 };
184
185 /* OF graph endpoint's V4L2 async data */
186 struct rcar_drif_graph_ep {
187 struct v4l2_subdev *subdev; /* Async matched subdev */
188 };
189
190 /* DMA buffer */
191 struct rcar_drif_hwbuf {
192 void *addr; /* CPU-side address */
193 unsigned int status; /* Buffer status flags */
194 };
195
196 /* Internal channel */
197 struct rcar_drif {
198 struct rcar_drif_sdr *sdr; /* Group device */
199 struct platform_device *pdev; /* Channel's pdev */
200 void __iomem *base; /* Base register address */
201 resource_size_t start; /* I/O resource offset */
202 struct dma_chan *dmach; /* Reserved DMA channel */
203 struct clk *clk; /* Module clock */
204 struct rcar_drif_hwbuf buf[RCAR_DRIF_NUM_HWBUFS]; /* H/W bufs */
205 dma_addr_t dma_handle; /* Handle for all bufs */
206 unsigned int num; /* Channel number */
207 bool acting_sdr; /* Channel acting as SDR device */
208 };
209
210 /* DRIF V4L2 SDR */
211 struct rcar_drif_sdr {
212 struct device *dev; /* Platform device */
213 struct video_device *vdev; /* V4L2 SDR device */
214 struct v4l2_device v4l2_dev; /* V4L2 device */
215
216 /* Videobuf2 queue and queued buffers list */
217 struct vb2_queue vb_queue;
218 struct list_head queued_bufs;
219 spinlock_t queued_bufs_lock; /* Protects queued_bufs */
220 spinlock_t dma_lock; /* To serialize DMA cb of channels */
221
222 struct mutex v4l2_mutex; /* To serialize ioctls */
223 struct mutex vb_queue_mutex; /* To serialize streaming ioctls */
224 struct v4l2_ctrl_handler ctrl_hdl; /* SDR control handler */
225 struct v4l2_async_notifier notifier; /* For subdev (tuner) */
226 struct rcar_drif_graph_ep ep; /* Endpoint V4L2 async data */
227
228 /* Current V4L2 SDR format ptr */
229 const struct rcar_drif_format *fmt;
230
231 /* Device tree SYNC properties */
232 u32 mdr1;
233
234 /* Internals */
235 struct rcar_drif *ch[RCAR_DRIF_MAX_CHANNEL]; /* DRIFx0,1 */
236 unsigned long hw_ch_mask; /* Enabled channels per DT */
237 unsigned long cur_ch_mask; /* Used channels for an SDR FMT */
238 u32 num_hw_ch; /* Num of DT enabled channels */
239 u32 num_cur_ch; /* Num of used channels */
240 u32 hwbuf_size; /* Each DMA buffer size */
241 u32 produced; /* Buffers produced by sdr dev */
242 };
243
244 /* Register access functions */
rcar_drif_write(struct rcar_drif * ch,u32 offset,u32 data)245 static void rcar_drif_write(struct rcar_drif *ch, u32 offset, u32 data)
246 {
247 writel(data, ch->base + offset);
248 }
249
rcar_drif_read(struct rcar_drif * ch,u32 offset)250 static u32 rcar_drif_read(struct rcar_drif *ch, u32 offset)
251 {
252 return readl(ch->base + offset);
253 }
254
255 /* Release DMA channels */
rcar_drif_release_dmachannels(struct rcar_drif_sdr * sdr)256 static void rcar_drif_release_dmachannels(struct rcar_drif_sdr *sdr)
257 {
258 unsigned int i;
259
260 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
261 if (sdr->ch[i]->dmach) {
262 dma_release_channel(sdr->ch[i]->dmach);
263 sdr->ch[i]->dmach = NULL;
264 }
265 }
266
267 /* Allocate DMA channels */
rcar_drif_alloc_dmachannels(struct rcar_drif_sdr * sdr)268 static int rcar_drif_alloc_dmachannels(struct rcar_drif_sdr *sdr)
269 {
270 struct dma_slave_config dma_cfg;
271 unsigned int i;
272 int ret;
273
274 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
275 struct rcar_drif *ch = sdr->ch[i];
276
277 ch->dmach = dma_request_chan(&ch->pdev->dev, "rx");
278 if (IS_ERR(ch->dmach)) {
279 ret = PTR_ERR(ch->dmach);
280 if (ret != -EPROBE_DEFER)
281 rdrif_err(sdr,
282 "ch%u: dma channel req failed: %pe\n",
283 i, ch->dmach);
284 ch->dmach = NULL;
285 goto dmach_error;
286 }
287
288 /* Configure slave */
289 memset(&dma_cfg, 0, sizeof(dma_cfg));
290 dma_cfg.src_addr = (phys_addr_t)(ch->start + RCAR_DRIF_SIRFDR);
291 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
292 ret = dmaengine_slave_config(ch->dmach, &dma_cfg);
293 if (ret) {
294 rdrif_err(sdr, "ch%u: dma slave config failed\n", i);
295 goto dmach_error;
296 }
297 }
298 return 0;
299
300 dmach_error:
301 rcar_drif_release_dmachannels(sdr);
302 return ret;
303 }
304
305 /* Release queued vb2 buffers */
rcar_drif_release_queued_bufs(struct rcar_drif_sdr * sdr,enum vb2_buffer_state state)306 static void rcar_drif_release_queued_bufs(struct rcar_drif_sdr *sdr,
307 enum vb2_buffer_state state)
308 {
309 struct rcar_drif_frame_buf *fbuf, *tmp;
310 unsigned long flags;
311
312 spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
313 list_for_each_entry_safe(fbuf, tmp, &sdr->queued_bufs, list) {
314 list_del(&fbuf->list);
315 vb2_buffer_done(&fbuf->vb.vb2_buf, state);
316 }
317 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
318 }
319
320 /* Set MDR defaults */
rcar_drif_set_mdr1(struct rcar_drif_sdr * sdr)321 static inline void rcar_drif_set_mdr1(struct rcar_drif_sdr *sdr)
322 {
323 unsigned int i;
324
325 /* Set defaults for enabled internal channels */
326 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
327 /* Refer MSIOF section in manual for this register setting */
328 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SITMDR1,
329 RCAR_DRIF_SITMDR1_PCON);
330
331 /* Setup MDR1 value */
332 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR1, sdr->mdr1);
333
334 rdrif_dbg(sdr, "ch%u: mdr1 = 0x%08x",
335 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR1));
336 }
337 }
338
339 /* Set DRIF receive format */
rcar_drif_set_format(struct rcar_drif_sdr * sdr)340 static int rcar_drif_set_format(struct rcar_drif_sdr *sdr)
341 {
342 unsigned int i;
343
344 rdrif_dbg(sdr, "setfmt: bitlen %u wdcnt %u num_ch %u\n",
345 sdr->fmt->bitlen, sdr->fmt->wdcnt, sdr->fmt->num_ch);
346
347 /* Sanity check */
348 if (sdr->fmt->num_ch > sdr->num_cur_ch) {
349 rdrif_err(sdr, "fmt num_ch %u cur_ch %u mismatch\n",
350 sdr->fmt->num_ch, sdr->num_cur_ch);
351 return -EINVAL;
352 }
353
354 /* Setup group, bitlen & wdcnt */
355 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
356 u32 mdr;
357
358 /* Two groups */
359 mdr = RCAR_DRIF_MDR_GRPCNT(2) |
360 RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
361 RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt);
362 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR2, mdr);
363
364 mdr = RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
365 RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt);
366 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR3, mdr);
367
368 rdrif_dbg(sdr, "ch%u: new mdr[2,3] = 0x%08x, 0x%08x\n",
369 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR2),
370 rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR3));
371 }
372 return 0;
373 }
374
375 /* Release DMA buffers */
rcar_drif_release_buf(struct rcar_drif_sdr * sdr)376 static void rcar_drif_release_buf(struct rcar_drif_sdr *sdr)
377 {
378 unsigned int i;
379
380 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
381 struct rcar_drif *ch = sdr->ch[i];
382
383 /* First entry contains the dma buf ptr */
384 if (ch->buf[0].addr) {
385 dma_free_coherent(&ch->pdev->dev,
386 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
387 ch->buf[0].addr, ch->dma_handle);
388 ch->buf[0].addr = NULL;
389 }
390 }
391 }
392
393 /* Request DMA buffers */
rcar_drif_request_buf(struct rcar_drif_sdr * sdr)394 static int rcar_drif_request_buf(struct rcar_drif_sdr *sdr)
395 {
396 int ret = -ENOMEM;
397 unsigned int i, j;
398 void *addr;
399
400 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
401 struct rcar_drif *ch = sdr->ch[i];
402
403 /* Allocate DMA buffers */
404 addr = dma_alloc_coherent(&ch->pdev->dev,
405 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
406 &ch->dma_handle, GFP_KERNEL);
407 if (!addr) {
408 rdrif_err(sdr,
409 "ch%u: dma alloc failed. num hwbufs %u size %u\n",
410 i, RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size);
411 goto error;
412 }
413
414 /* Split the chunk and populate bufctxt */
415 for (j = 0; j < RCAR_DRIF_NUM_HWBUFS; j++) {
416 ch->buf[j].addr = addr + (j * sdr->hwbuf_size);
417 ch->buf[j].status = 0;
418 }
419 }
420 return 0;
421 error:
422 return ret;
423 }
424
425 /* Setup vb_queue minimum buffer requirements */
rcar_drif_queue_setup(struct vb2_queue * vq,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_devs[])426 static int rcar_drif_queue_setup(struct vb2_queue *vq,
427 unsigned int *num_buffers, unsigned int *num_planes,
428 unsigned int sizes[], struct device *alloc_devs[])
429 {
430 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
431
432 /* Need at least 16 buffers */
433 if (vq->num_buffers + *num_buffers < 16)
434 *num_buffers = 16 - vq->num_buffers;
435
436 *num_planes = 1;
437 sizes[0] = PAGE_ALIGN(sdr->fmt->buffersize);
438 rdrif_dbg(sdr, "num_bufs %d sizes[0] %d\n", *num_buffers, sizes[0]);
439
440 return 0;
441 }
442
443 /* Enqueue buffer */
rcar_drif_buf_queue(struct vb2_buffer * vb)444 static void rcar_drif_buf_queue(struct vb2_buffer *vb)
445 {
446 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
447 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vb->vb2_queue);
448 struct rcar_drif_frame_buf *fbuf =
449 container_of(vbuf, struct rcar_drif_frame_buf, vb);
450 unsigned long flags;
451
452 rdrif_dbg(sdr, "buf_queue idx %u\n", vb->index);
453 spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
454 list_add_tail(&fbuf->list, &sdr->queued_bufs);
455 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
456 }
457
458 /* Get a frame buf from list */
459 static struct rcar_drif_frame_buf *
rcar_drif_get_fbuf(struct rcar_drif_sdr * sdr)460 rcar_drif_get_fbuf(struct rcar_drif_sdr *sdr)
461 {
462 struct rcar_drif_frame_buf *fbuf;
463 unsigned long flags;
464
465 spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
466 fbuf = list_first_entry_or_null(&sdr->queued_bufs, struct
467 rcar_drif_frame_buf, list);
468 if (!fbuf) {
469 /*
470 * App is late in enqueing buffers. Samples lost & there will
471 * be a gap in sequence number when app recovers
472 */
473 rdrif_dbg(sdr, "\napp late: prod %u\n", sdr->produced);
474 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
475 return NULL;
476 }
477 list_del(&fbuf->list);
478 spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
479
480 return fbuf;
481 }
482
483 /* Helpers to set/clear buf pair status */
rcar_drif_bufs_done(struct rcar_drif_hwbuf ** buf)484 static inline bool rcar_drif_bufs_done(struct rcar_drif_hwbuf **buf)
485 {
486 return (buf[0]->status & buf[1]->status & RCAR_DRIF_BUF_DONE);
487 }
488
rcar_drif_bufs_overflow(struct rcar_drif_hwbuf ** buf)489 static inline bool rcar_drif_bufs_overflow(struct rcar_drif_hwbuf **buf)
490 {
491 return ((buf[0]->status | buf[1]->status) & RCAR_DRIF_BUF_OVERFLOW);
492 }
493
rcar_drif_bufs_clear(struct rcar_drif_hwbuf ** buf,unsigned int bit)494 static inline void rcar_drif_bufs_clear(struct rcar_drif_hwbuf **buf,
495 unsigned int bit)
496 {
497 unsigned int i;
498
499 for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++)
500 buf[i]->status &= ~bit;
501 }
502
503 /* Channel DMA complete */
rcar_drif_channel_complete(struct rcar_drif * ch,u32 idx)504 static void rcar_drif_channel_complete(struct rcar_drif *ch, u32 idx)
505 {
506 u32 str;
507
508 ch->buf[idx].status |= RCAR_DRIF_BUF_DONE;
509
510 /* Check for DRIF errors */
511 str = rcar_drif_read(ch, RCAR_DRIF_SISTR);
512 if (unlikely(str & RCAR_DRIF_RFOVF)) {
513 /* Writing the same clears it */
514 rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
515
516 /* Overflow: some samples are lost */
517 ch->buf[idx].status |= RCAR_DRIF_BUF_OVERFLOW;
518 }
519 }
520
521 /* DMA callback for each stage */
rcar_drif_dma_complete(void * dma_async_param)522 static void rcar_drif_dma_complete(void *dma_async_param)
523 {
524 struct rcar_drif *ch = dma_async_param;
525 struct rcar_drif_sdr *sdr = ch->sdr;
526 struct rcar_drif_hwbuf *buf[RCAR_DRIF_MAX_CHANNEL];
527 struct rcar_drif_frame_buf *fbuf;
528 bool overflow = false;
529 u32 idx, produced;
530 unsigned int i;
531
532 spin_lock(&sdr->dma_lock);
533
534 /* DMA can be terminated while the callback was waiting on lock */
535 if (!vb2_is_streaming(&sdr->vb_queue)) {
536 spin_unlock(&sdr->dma_lock);
537 return;
538 }
539
540 idx = sdr->produced % RCAR_DRIF_NUM_HWBUFS;
541 rcar_drif_channel_complete(ch, idx);
542
543 if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL) {
544 buf[0] = ch->num ? to_rcar_drif_buf_pair(sdr, ch->num, idx) :
545 &ch->buf[idx];
546 buf[1] = ch->num ? &ch->buf[idx] :
547 to_rcar_drif_buf_pair(sdr, ch->num, idx);
548
549 /* Check if both DMA buffers are done */
550 if (!rcar_drif_bufs_done(buf)) {
551 spin_unlock(&sdr->dma_lock);
552 return;
553 }
554
555 /* Clear buf done status */
556 rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_DONE);
557
558 if (rcar_drif_bufs_overflow(buf)) {
559 overflow = true;
560 /* Clear the flag in status */
561 rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_OVERFLOW);
562 }
563 } else {
564 buf[0] = &ch->buf[idx];
565 if (buf[0]->status & RCAR_DRIF_BUF_OVERFLOW) {
566 overflow = true;
567 /* Clear the flag in status */
568 buf[0]->status &= ~RCAR_DRIF_BUF_OVERFLOW;
569 }
570 }
571
572 /* Buffer produced for consumption */
573 produced = sdr->produced++;
574 spin_unlock(&sdr->dma_lock);
575
576 rdrif_dbg(sdr, "ch%u: prod %u\n", ch->num, produced);
577
578 /* Get fbuf */
579 fbuf = rcar_drif_get_fbuf(sdr);
580 if (!fbuf)
581 return;
582
583 for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++)
584 memcpy(vb2_plane_vaddr(&fbuf->vb.vb2_buf, 0) +
585 i * sdr->hwbuf_size, buf[i]->addr, sdr->hwbuf_size);
586
587 fbuf->vb.field = V4L2_FIELD_NONE;
588 fbuf->vb.sequence = produced;
589 fbuf->vb.vb2_buf.timestamp = ktime_get_ns();
590 vb2_set_plane_payload(&fbuf->vb.vb2_buf, 0, sdr->fmt->buffersize);
591
592 /* Set error state on overflow */
593 vb2_buffer_done(&fbuf->vb.vb2_buf,
594 overflow ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
595 }
596
rcar_drif_qbuf(struct rcar_drif * ch)597 static int rcar_drif_qbuf(struct rcar_drif *ch)
598 {
599 struct rcar_drif_sdr *sdr = ch->sdr;
600 dma_addr_t addr = ch->dma_handle;
601 struct dma_async_tx_descriptor *rxd;
602 dma_cookie_t cookie;
603 int ret = -EIO;
604
605 /* Setup cyclic DMA with given buffers */
606 rxd = dmaengine_prep_dma_cyclic(ch->dmach, addr,
607 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
608 sdr->hwbuf_size, DMA_DEV_TO_MEM,
609 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
610 if (!rxd) {
611 rdrif_err(sdr, "ch%u: prep dma cyclic failed\n", ch->num);
612 return ret;
613 }
614
615 /* Submit descriptor */
616 rxd->callback = rcar_drif_dma_complete;
617 rxd->callback_param = ch;
618 cookie = dmaengine_submit(rxd);
619 if (dma_submit_error(cookie)) {
620 rdrif_err(sdr, "ch%u: dma submit failed\n", ch->num);
621 return ret;
622 }
623
624 dma_async_issue_pending(ch->dmach);
625 return 0;
626 }
627
628 /* Enable reception */
rcar_drif_enable_rx(struct rcar_drif_sdr * sdr)629 static int rcar_drif_enable_rx(struct rcar_drif_sdr *sdr)
630 {
631 unsigned int i;
632 u32 ctr;
633 int ret = -EINVAL;
634
635 /*
636 * When both internal channels are enabled, they can be synchronized
637 * only by the master
638 */
639
640 /* Enable receive */
641 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
642 ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
643 ctr |= (RCAR_DRIF_SICTR_RX_RISING_EDGE |
644 RCAR_DRIF_SICTR_RX_EN);
645 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
646 }
647
648 /* Check receive enabled */
649 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
650 ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
651 ctr, ctr & RCAR_DRIF_SICTR_RX_EN, 7, 100000);
652 if (ret) {
653 rdrif_err(sdr, "ch%u: rx en failed. ctr 0x%08x\n", i,
654 rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
655 break;
656 }
657 }
658 return ret;
659 }
660
661 /* Disable reception */
rcar_drif_disable_rx(struct rcar_drif_sdr * sdr)662 static void rcar_drif_disable_rx(struct rcar_drif_sdr *sdr)
663 {
664 unsigned int i;
665 u32 ctr;
666 int ret;
667
668 /* Disable receive */
669 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
670 ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
671 ctr &= ~RCAR_DRIF_SICTR_RX_EN;
672 rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
673 }
674
675 /* Check receive disabled */
676 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
677 ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
678 ctr, !(ctr & RCAR_DRIF_SICTR_RX_EN), 7, 100000);
679 if (ret)
680 dev_warn(&sdr->vdev->dev,
681 "ch%u: failed to disable rx. ctr 0x%08x\n",
682 i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
683 }
684 }
685
686 /* Stop channel */
rcar_drif_stop_channel(struct rcar_drif * ch)687 static void rcar_drif_stop_channel(struct rcar_drif *ch)
688 {
689 /* Disable DMA receive interrupt */
690 rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00000000);
691
692 /* Terminate all DMA transfers */
693 dmaengine_terminate_sync(ch->dmach);
694 }
695
696 /* Stop receive operation */
rcar_drif_stop(struct rcar_drif_sdr * sdr)697 static void rcar_drif_stop(struct rcar_drif_sdr *sdr)
698 {
699 unsigned int i;
700
701 /* Disable Rx */
702 rcar_drif_disable_rx(sdr);
703
704 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
705 rcar_drif_stop_channel(sdr->ch[i]);
706 }
707
708 /* Start channel */
rcar_drif_start_channel(struct rcar_drif * ch)709 static int rcar_drif_start_channel(struct rcar_drif *ch)
710 {
711 struct rcar_drif_sdr *sdr = ch->sdr;
712 u32 ctr, str;
713 int ret;
714
715 /* Reset receive */
716 rcar_drif_write(ch, RCAR_DRIF_SICTR, RCAR_DRIF_SICTR_RESET);
717 ret = readl_poll_timeout(ch->base + RCAR_DRIF_SICTR, ctr,
718 !(ctr & RCAR_DRIF_SICTR_RESET), 7, 100000);
719 if (ret) {
720 rdrif_err(sdr, "ch%u: failed to reset rx. ctr 0x%08x\n",
721 ch->num, rcar_drif_read(ch, RCAR_DRIF_SICTR));
722 return ret;
723 }
724
725 /* Queue buffers for DMA */
726 ret = rcar_drif_qbuf(ch);
727 if (ret)
728 return ret;
729
730 /* Clear status register flags */
731 str = RCAR_DRIF_RFFUL | RCAR_DRIF_REOF | RCAR_DRIF_RFSERR |
732 RCAR_DRIF_RFUDF | RCAR_DRIF_RFOVF;
733 rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
734
735 /* Enable DMA receive interrupt */
736 rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00009000);
737
738 return ret;
739 }
740
741 /* Start receive operation */
rcar_drif_start(struct rcar_drif_sdr * sdr)742 static int rcar_drif_start(struct rcar_drif_sdr *sdr)
743 {
744 unsigned long enabled = 0;
745 unsigned int i;
746 int ret;
747
748 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
749 ret = rcar_drif_start_channel(sdr->ch[i]);
750 if (ret)
751 goto start_error;
752 enabled |= BIT(i);
753 }
754
755 ret = rcar_drif_enable_rx(sdr);
756 if (ret)
757 goto enable_error;
758
759 sdr->produced = 0;
760 return ret;
761
762 enable_error:
763 rcar_drif_disable_rx(sdr);
764 start_error:
765 for_each_rcar_drif_channel(i, &enabled)
766 rcar_drif_stop_channel(sdr->ch[i]);
767
768 return ret;
769 }
770
771 /* Start streaming */
rcar_drif_start_streaming(struct vb2_queue * vq,unsigned int count)772 static int rcar_drif_start_streaming(struct vb2_queue *vq, unsigned int count)
773 {
774 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
775 unsigned long enabled = 0;
776 unsigned int i;
777 int ret;
778
779 mutex_lock(&sdr->v4l2_mutex);
780
781 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
782 ret = clk_prepare_enable(sdr->ch[i]->clk);
783 if (ret)
784 goto error;
785 enabled |= BIT(i);
786 }
787
788 /* Set default MDRx settings */
789 rcar_drif_set_mdr1(sdr);
790
791 /* Set new format */
792 ret = rcar_drif_set_format(sdr);
793 if (ret)
794 goto error;
795
796 if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL)
797 sdr->hwbuf_size = sdr->fmt->buffersize / RCAR_DRIF_MAX_CHANNEL;
798 else
799 sdr->hwbuf_size = sdr->fmt->buffersize;
800
801 rdrif_dbg(sdr, "num hwbufs %u, hwbuf_size %u\n",
802 RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size);
803
804 /* Alloc DMA channel */
805 ret = rcar_drif_alloc_dmachannels(sdr);
806 if (ret)
807 goto error;
808
809 /* Request buffers */
810 ret = rcar_drif_request_buf(sdr);
811 if (ret)
812 goto error;
813
814 /* Start Rx */
815 ret = rcar_drif_start(sdr);
816 if (ret)
817 goto error;
818
819 mutex_unlock(&sdr->v4l2_mutex);
820
821 return ret;
822
823 error:
824 rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_QUEUED);
825 rcar_drif_release_buf(sdr);
826 rcar_drif_release_dmachannels(sdr);
827 for_each_rcar_drif_channel(i, &enabled)
828 clk_disable_unprepare(sdr->ch[i]->clk);
829
830 mutex_unlock(&sdr->v4l2_mutex);
831
832 return ret;
833 }
834
835 /* Stop streaming */
rcar_drif_stop_streaming(struct vb2_queue * vq)836 static void rcar_drif_stop_streaming(struct vb2_queue *vq)
837 {
838 struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
839 unsigned int i;
840
841 mutex_lock(&sdr->v4l2_mutex);
842
843 /* Stop hardware streaming */
844 rcar_drif_stop(sdr);
845
846 /* Return all queued buffers to vb2 */
847 rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_ERROR);
848
849 /* Release buf */
850 rcar_drif_release_buf(sdr);
851
852 /* Release DMA channel resources */
853 rcar_drif_release_dmachannels(sdr);
854
855 for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
856 clk_disable_unprepare(sdr->ch[i]->clk);
857
858 mutex_unlock(&sdr->v4l2_mutex);
859 }
860
861 /* Vb2 ops */
862 static const struct vb2_ops rcar_drif_vb2_ops = {
863 .queue_setup = rcar_drif_queue_setup,
864 .buf_queue = rcar_drif_buf_queue,
865 .start_streaming = rcar_drif_start_streaming,
866 .stop_streaming = rcar_drif_stop_streaming,
867 .wait_prepare = vb2_ops_wait_prepare,
868 .wait_finish = vb2_ops_wait_finish,
869 };
870
rcar_drif_querycap(struct file * file,void * fh,struct v4l2_capability * cap)871 static int rcar_drif_querycap(struct file *file, void *fh,
872 struct v4l2_capability *cap)
873 {
874 struct rcar_drif_sdr *sdr = video_drvdata(file);
875
876 strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
877 strscpy(cap->card, sdr->vdev->name, sizeof(cap->card));
878 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
879 sdr->vdev->name);
880
881 return 0;
882 }
883
rcar_drif_set_default_format(struct rcar_drif_sdr * sdr)884 static int rcar_drif_set_default_format(struct rcar_drif_sdr *sdr)
885 {
886 unsigned int i;
887
888 for (i = 0; i < ARRAY_SIZE(formats); i++) {
889 /* Matching fmt based on required channels is set as default */
890 if (sdr->num_hw_ch == formats[i].num_ch) {
891 sdr->fmt = &formats[i];
892 sdr->cur_ch_mask = sdr->hw_ch_mask;
893 sdr->num_cur_ch = sdr->num_hw_ch;
894 dev_dbg(sdr->dev, "default fmt[%u]: mask %lu num %u\n",
895 i, sdr->cur_ch_mask, sdr->num_cur_ch);
896 return 0;
897 }
898 }
899 return -EINVAL;
900 }
901
rcar_drif_enum_fmt_sdr_cap(struct file * file,void * priv,struct v4l2_fmtdesc * f)902 static int rcar_drif_enum_fmt_sdr_cap(struct file *file, void *priv,
903 struct v4l2_fmtdesc *f)
904 {
905 if (f->index >= ARRAY_SIZE(formats))
906 return -EINVAL;
907
908 f->pixelformat = formats[f->index].pixelformat;
909
910 return 0;
911 }
912
rcar_drif_g_fmt_sdr_cap(struct file * file,void * priv,struct v4l2_format * f)913 static int rcar_drif_g_fmt_sdr_cap(struct file *file, void *priv,
914 struct v4l2_format *f)
915 {
916 struct rcar_drif_sdr *sdr = video_drvdata(file);
917
918 memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
919 f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
920 f->fmt.sdr.buffersize = sdr->fmt->buffersize;
921
922 return 0;
923 }
924
rcar_drif_s_fmt_sdr_cap(struct file * file,void * priv,struct v4l2_format * f)925 static int rcar_drif_s_fmt_sdr_cap(struct file *file, void *priv,
926 struct v4l2_format *f)
927 {
928 struct rcar_drif_sdr *sdr = video_drvdata(file);
929 struct vb2_queue *q = &sdr->vb_queue;
930 unsigned int i;
931
932 if (vb2_is_busy(q))
933 return -EBUSY;
934
935 for (i = 0; i < ARRAY_SIZE(formats); i++) {
936 if (formats[i].pixelformat == f->fmt.sdr.pixelformat)
937 break;
938 }
939
940 if (i == ARRAY_SIZE(formats))
941 i = 0; /* Set the 1st format as default on no match */
942
943 sdr->fmt = &formats[i];
944 f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
945 f->fmt.sdr.buffersize = formats[i].buffersize;
946 memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
947
948 /*
949 * If a format demands one channel only out of two
950 * enabled channels, pick the 0th channel.
951 */
952 if (formats[i].num_ch < sdr->num_hw_ch) {
953 sdr->cur_ch_mask = BIT(0);
954 sdr->num_cur_ch = formats[i].num_ch;
955 } else {
956 sdr->cur_ch_mask = sdr->hw_ch_mask;
957 sdr->num_cur_ch = sdr->num_hw_ch;
958 }
959
960 rdrif_dbg(sdr, "cur: idx %u mask %lu num %u\n",
961 i, sdr->cur_ch_mask, sdr->num_cur_ch);
962
963 return 0;
964 }
965
rcar_drif_try_fmt_sdr_cap(struct file * file,void * priv,struct v4l2_format * f)966 static int rcar_drif_try_fmt_sdr_cap(struct file *file, void *priv,
967 struct v4l2_format *f)
968 {
969 unsigned int i;
970
971 for (i = 0; i < ARRAY_SIZE(formats); i++) {
972 if (formats[i].pixelformat == f->fmt.sdr.pixelformat) {
973 f->fmt.sdr.buffersize = formats[i].buffersize;
974 return 0;
975 }
976 }
977
978 f->fmt.sdr.pixelformat = formats[0].pixelformat;
979 f->fmt.sdr.buffersize = formats[0].buffersize;
980 memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
981
982 return 0;
983 }
984
985 /* Tuner subdev ioctls */
rcar_drif_enum_freq_bands(struct file * file,void * priv,struct v4l2_frequency_band * band)986 static int rcar_drif_enum_freq_bands(struct file *file, void *priv,
987 struct v4l2_frequency_band *band)
988 {
989 struct rcar_drif_sdr *sdr = video_drvdata(file);
990
991 return v4l2_subdev_call(sdr->ep.subdev, tuner, enum_freq_bands, band);
992 }
993
rcar_drif_g_frequency(struct file * file,void * priv,struct v4l2_frequency * f)994 static int rcar_drif_g_frequency(struct file *file, void *priv,
995 struct v4l2_frequency *f)
996 {
997 struct rcar_drif_sdr *sdr = video_drvdata(file);
998
999 return v4l2_subdev_call(sdr->ep.subdev, tuner, g_frequency, f);
1000 }
1001
rcar_drif_s_frequency(struct file * file,void * priv,const struct v4l2_frequency * f)1002 static int rcar_drif_s_frequency(struct file *file, void *priv,
1003 const struct v4l2_frequency *f)
1004 {
1005 struct rcar_drif_sdr *sdr = video_drvdata(file);
1006
1007 return v4l2_subdev_call(sdr->ep.subdev, tuner, s_frequency, f);
1008 }
1009
rcar_drif_g_tuner(struct file * file,void * priv,struct v4l2_tuner * vt)1010 static int rcar_drif_g_tuner(struct file *file, void *priv,
1011 struct v4l2_tuner *vt)
1012 {
1013 struct rcar_drif_sdr *sdr = video_drvdata(file);
1014
1015 return v4l2_subdev_call(sdr->ep.subdev, tuner, g_tuner, vt);
1016 }
1017
rcar_drif_s_tuner(struct file * file,void * priv,const struct v4l2_tuner * vt)1018 static int rcar_drif_s_tuner(struct file *file, void *priv,
1019 const struct v4l2_tuner *vt)
1020 {
1021 struct rcar_drif_sdr *sdr = video_drvdata(file);
1022
1023 return v4l2_subdev_call(sdr->ep.subdev, tuner, s_tuner, vt);
1024 }
1025
1026 static const struct v4l2_ioctl_ops rcar_drif_ioctl_ops = {
1027 .vidioc_querycap = rcar_drif_querycap,
1028
1029 .vidioc_enum_fmt_sdr_cap = rcar_drif_enum_fmt_sdr_cap,
1030 .vidioc_g_fmt_sdr_cap = rcar_drif_g_fmt_sdr_cap,
1031 .vidioc_s_fmt_sdr_cap = rcar_drif_s_fmt_sdr_cap,
1032 .vidioc_try_fmt_sdr_cap = rcar_drif_try_fmt_sdr_cap,
1033
1034 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1035 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1036 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1037 .vidioc_querybuf = vb2_ioctl_querybuf,
1038 .vidioc_qbuf = vb2_ioctl_qbuf,
1039 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1040
1041 .vidioc_streamon = vb2_ioctl_streamon,
1042 .vidioc_streamoff = vb2_ioctl_streamoff,
1043
1044 .vidioc_s_frequency = rcar_drif_s_frequency,
1045 .vidioc_g_frequency = rcar_drif_g_frequency,
1046 .vidioc_s_tuner = rcar_drif_s_tuner,
1047 .vidioc_g_tuner = rcar_drif_g_tuner,
1048 .vidioc_enum_freq_bands = rcar_drif_enum_freq_bands,
1049 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1050 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1051 .vidioc_log_status = v4l2_ctrl_log_status,
1052 };
1053
1054 static const struct v4l2_file_operations rcar_drif_fops = {
1055 .owner = THIS_MODULE,
1056 .open = v4l2_fh_open,
1057 .release = vb2_fop_release,
1058 .read = vb2_fop_read,
1059 .poll = vb2_fop_poll,
1060 .mmap = vb2_fop_mmap,
1061 .unlocked_ioctl = video_ioctl2,
1062 };
1063
rcar_drif_sdr_register(struct rcar_drif_sdr * sdr)1064 static int rcar_drif_sdr_register(struct rcar_drif_sdr *sdr)
1065 {
1066 int ret;
1067
1068 /* Init video_device structure */
1069 sdr->vdev = video_device_alloc();
1070 if (!sdr->vdev)
1071 return -ENOMEM;
1072
1073 snprintf(sdr->vdev->name, sizeof(sdr->vdev->name), "R-Car DRIF");
1074 sdr->vdev->fops = &rcar_drif_fops;
1075 sdr->vdev->ioctl_ops = &rcar_drif_ioctl_ops;
1076 sdr->vdev->release = video_device_release;
1077 sdr->vdev->lock = &sdr->v4l2_mutex;
1078 sdr->vdev->queue = &sdr->vb_queue;
1079 sdr->vdev->queue->lock = &sdr->vb_queue_mutex;
1080 sdr->vdev->ctrl_handler = &sdr->ctrl_hdl;
1081 sdr->vdev->v4l2_dev = &sdr->v4l2_dev;
1082 sdr->vdev->device_caps = V4L2_CAP_SDR_CAPTURE | V4L2_CAP_TUNER |
1083 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
1084 video_set_drvdata(sdr->vdev, sdr);
1085
1086 /* Register V4L2 SDR device */
1087 ret = video_register_device(sdr->vdev, VFL_TYPE_SDR, -1);
1088 if (ret) {
1089 video_device_release(sdr->vdev);
1090 sdr->vdev = NULL;
1091 dev_err(sdr->dev, "failed video_register_device (%d)\n", ret);
1092 }
1093
1094 return ret;
1095 }
1096
rcar_drif_sdr_unregister(struct rcar_drif_sdr * sdr)1097 static void rcar_drif_sdr_unregister(struct rcar_drif_sdr *sdr)
1098 {
1099 video_unregister_device(sdr->vdev);
1100 sdr->vdev = NULL;
1101 }
1102
1103 /* Sub-device bound callback */
rcar_drif_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1104 static int rcar_drif_notify_bound(struct v4l2_async_notifier *notifier,
1105 struct v4l2_subdev *subdev,
1106 struct v4l2_async_subdev *asd)
1107 {
1108 struct rcar_drif_sdr *sdr =
1109 container_of(notifier, struct rcar_drif_sdr, notifier);
1110
1111 v4l2_set_subdev_hostdata(subdev, sdr);
1112 sdr->ep.subdev = subdev;
1113 rdrif_dbg(sdr, "bound asd %s\n", subdev->name);
1114
1115 return 0;
1116 }
1117
1118 /* Sub-device unbind callback */
rcar_drif_notify_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1119 static void rcar_drif_notify_unbind(struct v4l2_async_notifier *notifier,
1120 struct v4l2_subdev *subdev,
1121 struct v4l2_async_subdev *asd)
1122 {
1123 struct rcar_drif_sdr *sdr =
1124 container_of(notifier, struct rcar_drif_sdr, notifier);
1125
1126 if (sdr->ep.subdev != subdev) {
1127 rdrif_err(sdr, "subdev %s is not bound\n", subdev->name);
1128 return;
1129 }
1130
1131 /* Free ctrl handler if initialized */
1132 v4l2_ctrl_handler_free(&sdr->ctrl_hdl);
1133 sdr->v4l2_dev.ctrl_handler = NULL;
1134 sdr->ep.subdev = NULL;
1135
1136 rcar_drif_sdr_unregister(sdr);
1137 rdrif_dbg(sdr, "unbind asd %s\n", subdev->name);
1138 }
1139
1140 /* Sub-device registered notification callback */
rcar_drif_notify_complete(struct v4l2_async_notifier * notifier)1141 static int rcar_drif_notify_complete(struct v4l2_async_notifier *notifier)
1142 {
1143 struct rcar_drif_sdr *sdr =
1144 container_of(notifier, struct rcar_drif_sdr, notifier);
1145 int ret;
1146
1147 /*
1148 * The subdev tested at this point uses 4 controls. Using 10 as a worst
1149 * case scenario hint. When less controls are needed there will be some
1150 * unused memory and when more controls are needed the framework uses
1151 * hash to manage controls within this number.
1152 */
1153 ret = v4l2_ctrl_handler_init(&sdr->ctrl_hdl, 10);
1154 if (ret)
1155 return -ENOMEM;
1156
1157 sdr->v4l2_dev.ctrl_handler = &sdr->ctrl_hdl;
1158 ret = v4l2_device_register_subdev_nodes(&sdr->v4l2_dev);
1159 if (ret) {
1160 rdrif_err(sdr, "failed: register subdev nodes ret %d\n", ret);
1161 goto error;
1162 }
1163
1164 ret = v4l2_ctrl_add_handler(&sdr->ctrl_hdl,
1165 sdr->ep.subdev->ctrl_handler, NULL, true);
1166 if (ret) {
1167 rdrif_err(sdr, "failed: ctrl add hdlr ret %d\n", ret);
1168 goto error;
1169 }
1170
1171 ret = rcar_drif_sdr_register(sdr);
1172 if (ret)
1173 goto error;
1174
1175 return ret;
1176
1177 error:
1178 v4l2_ctrl_handler_free(&sdr->ctrl_hdl);
1179
1180 return ret;
1181 }
1182
1183 static const struct v4l2_async_notifier_operations rcar_drif_notify_ops = {
1184 .bound = rcar_drif_notify_bound,
1185 .unbind = rcar_drif_notify_unbind,
1186 .complete = rcar_drif_notify_complete,
1187 };
1188
1189 /* Read endpoint properties */
rcar_drif_get_ep_properties(struct rcar_drif_sdr * sdr,struct fwnode_handle * fwnode)1190 static void rcar_drif_get_ep_properties(struct rcar_drif_sdr *sdr,
1191 struct fwnode_handle *fwnode)
1192 {
1193 u32 val;
1194
1195 /* Set the I2S defaults for SIRMDR1*/
1196 sdr->mdr1 = RCAR_DRIF_SIRMDR1_SYNCMD_LR | RCAR_DRIF_SIRMDR1_MSB_FIRST |
1197 RCAR_DRIF_SIRMDR1_DTDL_1 | RCAR_DRIF_SIRMDR1_SYNCDL_0;
1198
1199 /* Parse sync polarity from endpoint */
1200 if (!fwnode_property_read_u32(fwnode, "sync-active", &val))
1201 sdr->mdr1 |= val ? RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH :
1202 RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW;
1203 else
1204 sdr->mdr1 |= RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH; /* default */
1205
1206 dev_dbg(sdr->dev, "mdr1 0x%08x\n", sdr->mdr1);
1207 }
1208
1209 /* Parse sub-devs (tuner) to find a matching device */
rcar_drif_parse_subdevs(struct rcar_drif_sdr * sdr)1210 static int rcar_drif_parse_subdevs(struct rcar_drif_sdr *sdr)
1211 {
1212 struct v4l2_async_notifier *notifier = &sdr->notifier;
1213 struct fwnode_handle *fwnode, *ep;
1214 struct v4l2_async_subdev *asd;
1215
1216 v4l2_async_notifier_init(notifier);
1217
1218 ep = fwnode_graph_get_next_endpoint(of_fwnode_handle(sdr->dev->of_node),
1219 NULL);
1220 if (!ep)
1221 return 0;
1222
1223 /* Get the endpoint properties */
1224 rcar_drif_get_ep_properties(sdr, ep);
1225
1226 fwnode = fwnode_graph_get_remote_port_parent(ep);
1227 fwnode_handle_put(ep);
1228 if (!fwnode) {
1229 dev_warn(sdr->dev, "bad remote port parent\n");
1230 return -EINVAL;
1231 }
1232
1233 asd = v4l2_async_notifier_add_fwnode_subdev(notifier, fwnode,
1234 sizeof(*asd));
1235 fwnode_handle_put(fwnode);
1236 if (IS_ERR(asd))
1237 return PTR_ERR(asd);
1238
1239 return 0;
1240 }
1241
1242 /* Check if the given device is the primary bond */
rcar_drif_primary_bond(struct platform_device * pdev)1243 static bool rcar_drif_primary_bond(struct platform_device *pdev)
1244 {
1245 return of_property_read_bool(pdev->dev.of_node, "renesas,primary-bond");
1246 }
1247
1248 /* Check if both devices of the bond are enabled */
rcar_drif_bond_enabled(struct platform_device * p)1249 static struct device_node *rcar_drif_bond_enabled(struct platform_device *p)
1250 {
1251 struct device_node *np;
1252
1253 np = of_parse_phandle(p->dev.of_node, "renesas,bonding", 0);
1254 if (np && of_device_is_available(np))
1255 return np;
1256
1257 return NULL;
1258 }
1259
1260 /* Check if the bonded device is probed */
rcar_drif_bond_available(struct rcar_drif_sdr * sdr,struct device_node * np)1261 static int rcar_drif_bond_available(struct rcar_drif_sdr *sdr,
1262 struct device_node *np)
1263 {
1264 struct platform_device *pdev;
1265 struct rcar_drif *ch;
1266 int ret = 0;
1267
1268 pdev = of_find_device_by_node(np);
1269 if (!pdev) {
1270 dev_err(sdr->dev, "failed to get bonded device from node\n");
1271 return -ENODEV;
1272 }
1273
1274 device_lock(&pdev->dev);
1275 ch = platform_get_drvdata(pdev);
1276 if (ch) {
1277 /* Update sdr data in the bonded device */
1278 ch->sdr = sdr;
1279
1280 /* Update sdr with bonded device data */
1281 sdr->ch[ch->num] = ch;
1282 sdr->hw_ch_mask |= BIT(ch->num);
1283 } else {
1284 /* Defer */
1285 dev_info(sdr->dev, "defer probe\n");
1286 ret = -EPROBE_DEFER;
1287 }
1288 device_unlock(&pdev->dev);
1289
1290 put_device(&pdev->dev);
1291
1292 return ret;
1293 }
1294
1295 /* V4L2 SDR device probe */
rcar_drif_sdr_probe(struct rcar_drif_sdr * sdr)1296 static int rcar_drif_sdr_probe(struct rcar_drif_sdr *sdr)
1297 {
1298 int ret;
1299
1300 /* Validate any supported format for enabled channels */
1301 ret = rcar_drif_set_default_format(sdr);
1302 if (ret) {
1303 dev_err(sdr->dev, "failed to set default format\n");
1304 return ret;
1305 }
1306
1307 /* Set defaults */
1308 sdr->hwbuf_size = RCAR_DRIF_DEFAULT_HWBUF_SIZE;
1309
1310 mutex_init(&sdr->v4l2_mutex);
1311 mutex_init(&sdr->vb_queue_mutex);
1312 spin_lock_init(&sdr->queued_bufs_lock);
1313 spin_lock_init(&sdr->dma_lock);
1314 INIT_LIST_HEAD(&sdr->queued_bufs);
1315
1316 /* Init videobuf2 queue structure */
1317 sdr->vb_queue.type = V4L2_BUF_TYPE_SDR_CAPTURE;
1318 sdr->vb_queue.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF;
1319 sdr->vb_queue.drv_priv = sdr;
1320 sdr->vb_queue.buf_struct_size = sizeof(struct rcar_drif_frame_buf);
1321 sdr->vb_queue.ops = &rcar_drif_vb2_ops;
1322 sdr->vb_queue.mem_ops = &vb2_vmalloc_memops;
1323 sdr->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1324
1325 /* Init videobuf2 queue */
1326 ret = vb2_queue_init(&sdr->vb_queue);
1327 if (ret) {
1328 dev_err(sdr->dev, "failed: vb2_queue_init ret %d\n", ret);
1329 return ret;
1330 }
1331
1332 /* Register the v4l2_device */
1333 ret = v4l2_device_register(sdr->dev, &sdr->v4l2_dev);
1334 if (ret) {
1335 dev_err(sdr->dev, "failed: v4l2_device_register ret %d\n", ret);
1336 return ret;
1337 }
1338
1339 /*
1340 * Parse subdevs after v4l2_device_register because if the subdev
1341 * is already probed, bound and complete will be called immediately
1342 */
1343 ret = rcar_drif_parse_subdevs(sdr);
1344 if (ret)
1345 goto error;
1346
1347 sdr->notifier.ops = &rcar_drif_notify_ops;
1348
1349 /* Register notifier */
1350 ret = v4l2_async_notifier_register(&sdr->v4l2_dev, &sdr->notifier);
1351 if (ret < 0) {
1352 dev_err(sdr->dev, "failed: notifier register ret %d\n", ret);
1353 goto cleanup;
1354 }
1355
1356 return ret;
1357
1358 cleanup:
1359 v4l2_async_notifier_cleanup(&sdr->notifier);
1360 error:
1361 v4l2_device_unregister(&sdr->v4l2_dev);
1362
1363 return ret;
1364 }
1365
1366 /* V4L2 SDR device remove */
rcar_drif_sdr_remove(struct rcar_drif_sdr * sdr)1367 static void rcar_drif_sdr_remove(struct rcar_drif_sdr *sdr)
1368 {
1369 v4l2_async_notifier_unregister(&sdr->notifier);
1370 v4l2_async_notifier_cleanup(&sdr->notifier);
1371 v4l2_device_unregister(&sdr->v4l2_dev);
1372 }
1373
1374 /* DRIF channel probe */
rcar_drif_probe(struct platform_device * pdev)1375 static int rcar_drif_probe(struct platform_device *pdev)
1376 {
1377 struct rcar_drif_sdr *sdr;
1378 struct device_node *np;
1379 struct rcar_drif *ch;
1380 struct resource *res;
1381 int ret;
1382
1383 /* Reserve memory for enabled channel */
1384 ch = devm_kzalloc(&pdev->dev, sizeof(*ch), GFP_KERNEL);
1385 if (!ch)
1386 return -ENOMEM;
1387
1388 ch->pdev = pdev;
1389
1390 /* Module clock */
1391 ch->clk = devm_clk_get(&pdev->dev, "fck");
1392 if (IS_ERR(ch->clk)) {
1393 ret = PTR_ERR(ch->clk);
1394 dev_err(&pdev->dev, "clk get failed (%d)\n", ret);
1395 return ret;
1396 }
1397
1398 /* Register map */
1399 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1400 ch->base = devm_ioremap_resource(&pdev->dev, res);
1401 if (IS_ERR(ch->base))
1402 return PTR_ERR(ch->base);
1403
1404 ch->start = res->start;
1405 platform_set_drvdata(pdev, ch);
1406
1407 /* Check if both channels of the bond are enabled */
1408 np = rcar_drif_bond_enabled(pdev);
1409 if (np) {
1410 /* Check if current channel acting as primary-bond */
1411 if (!rcar_drif_primary_bond(pdev)) {
1412 ch->num = 1; /* Primary bond is channel 0 always */
1413 of_node_put(np);
1414 return 0;
1415 }
1416 }
1417
1418 /* Reserve memory for SDR structure */
1419 sdr = devm_kzalloc(&pdev->dev, sizeof(*sdr), GFP_KERNEL);
1420 if (!sdr) {
1421 of_node_put(np);
1422 return -ENOMEM;
1423 }
1424 ch->sdr = sdr;
1425 sdr->dev = &pdev->dev;
1426
1427 /* Establish links between SDR and channel(s) */
1428 sdr->ch[ch->num] = ch;
1429 sdr->hw_ch_mask = BIT(ch->num);
1430 if (np) {
1431 /* Check if bonded device is ready */
1432 ret = rcar_drif_bond_available(sdr, np);
1433 of_node_put(np);
1434 if (ret)
1435 return ret;
1436 }
1437 sdr->num_hw_ch = hweight_long(sdr->hw_ch_mask);
1438
1439 return rcar_drif_sdr_probe(sdr);
1440 }
1441
1442 /* DRIF channel remove */
rcar_drif_remove(struct platform_device * pdev)1443 static int rcar_drif_remove(struct platform_device *pdev)
1444 {
1445 struct rcar_drif *ch = platform_get_drvdata(pdev);
1446 struct rcar_drif_sdr *sdr = ch->sdr;
1447
1448 /* Channel 0 will be the SDR instance */
1449 if (ch->num)
1450 return 0;
1451
1452 /* SDR instance */
1453 rcar_drif_sdr_remove(sdr);
1454
1455 return 0;
1456 }
1457
1458 /* FIXME: Implement suspend/resume support */
rcar_drif_suspend(struct device * dev)1459 static int __maybe_unused rcar_drif_suspend(struct device *dev)
1460 {
1461 return 0;
1462 }
1463
rcar_drif_resume(struct device * dev)1464 static int __maybe_unused rcar_drif_resume(struct device *dev)
1465 {
1466 return 0;
1467 }
1468
1469 static SIMPLE_DEV_PM_OPS(rcar_drif_pm_ops, rcar_drif_suspend,
1470 rcar_drif_resume);
1471
1472 static const struct of_device_id rcar_drif_of_table[] = {
1473 { .compatible = "renesas,rcar-gen3-drif" },
1474 { }
1475 };
1476 MODULE_DEVICE_TABLE(of, rcar_drif_of_table);
1477
1478 #define RCAR_DRIF_DRV_NAME "rcar_drif"
1479 static struct platform_driver rcar_drif_driver = {
1480 .driver = {
1481 .name = RCAR_DRIF_DRV_NAME,
1482 .of_match_table = of_match_ptr(rcar_drif_of_table),
1483 .pm = &rcar_drif_pm_ops,
1484 },
1485 .probe = rcar_drif_probe,
1486 .remove = rcar_drif_remove,
1487 };
1488
1489 module_platform_driver(rcar_drif_driver);
1490
1491 MODULE_DESCRIPTION("Renesas R-Car Gen3 DRIF driver");
1492 MODULE_ALIAS("platform:" RCAR_DRIF_DRV_NAME);
1493 MODULE_LICENSE("GPL");
1494 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
1495
