1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * ispccp2.c
4 *
5 * TI OMAP3 ISP - CCP2 module
6 *
7 * Copyright (C) 2010 Nokia Corporation
8 * Copyright (C) 2010 Texas Instruments, Inc.
9 *
10 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 * Sakari Ailus <sakari.ailus@iki.fi>
12 */
13
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/uaccess.h>
20 #include <linux/regulator/consumer.h>
21
22 #include "isp.h"
23 #include "ispreg.h"
24 #include "ispccp2.h"
25
26 /* Number of LCX channels */
27 #define CCP2_LCx_CHANS_NUM 3
28 /* Max/Min size for CCP2 video port */
29 #define ISPCCP2_DAT_START_MIN 0
30 #define ISPCCP2_DAT_START_MAX 4095
31 #define ISPCCP2_DAT_SIZE_MIN 0
32 #define ISPCCP2_DAT_SIZE_MAX 4095
33 #define ISPCCP2_VPCLK_FRACDIV 65536
34 #define ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP 0x12
35 #define ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP 0x16
36 /* Max/Min size for CCP2 memory channel */
37 #define ISPCCP2_LCM_HSIZE_COUNT_MIN 16
38 #define ISPCCP2_LCM_HSIZE_COUNT_MAX 8191
39 #define ISPCCP2_LCM_HSIZE_SKIP_MIN 0
40 #define ISPCCP2_LCM_HSIZE_SKIP_MAX 8191
41 #define ISPCCP2_LCM_VSIZE_MIN 1
42 #define ISPCCP2_LCM_VSIZE_MAX 8191
43 #define ISPCCP2_LCM_HWORDS_MIN 1
44 #define ISPCCP2_LCM_HWORDS_MAX 4095
45 #define ISPCCP2_LCM_CTRL_BURST_SIZE_32X 5
46 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_FULL 0
47 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 2
48 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 2
49 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 3
50 #define ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 3
51 #define ISPCCP2_LCM_CTRL_DST_PORT_VP 0
52 #define ISPCCP2_LCM_CTRL_DST_PORT_MEM 1
53
54 /* Set only the required bits */
55 #define BIT_SET(var, shift, mask, val) \
56 do { \
57 var = ((var) & ~((mask) << (shift))) \
58 | ((val) << (shift)); \
59 } while (0)
60
61 /*
62 * ccp2_print_status - Print current CCP2 module register values.
63 */
64 #define CCP2_PRINT_REGISTER(isp, name)\
65 dev_dbg(isp->dev, "###CCP2 " #name "=0x%08x\n", \
66 isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_##name))
67
ccp2_print_status(struct isp_ccp2_device * ccp2)68 static void ccp2_print_status(struct isp_ccp2_device *ccp2)
69 {
70 struct isp_device *isp = to_isp_device(ccp2);
71
72 dev_dbg(isp->dev, "-------------CCP2 Register dump-------------\n");
73
74 CCP2_PRINT_REGISTER(isp, SYSCONFIG);
75 CCP2_PRINT_REGISTER(isp, SYSSTATUS);
76 CCP2_PRINT_REGISTER(isp, LC01_IRQENABLE);
77 CCP2_PRINT_REGISTER(isp, LC01_IRQSTATUS);
78 CCP2_PRINT_REGISTER(isp, LC23_IRQENABLE);
79 CCP2_PRINT_REGISTER(isp, LC23_IRQSTATUS);
80 CCP2_PRINT_REGISTER(isp, LCM_IRQENABLE);
81 CCP2_PRINT_REGISTER(isp, LCM_IRQSTATUS);
82 CCP2_PRINT_REGISTER(isp, CTRL);
83 CCP2_PRINT_REGISTER(isp, LCx_CTRL(0));
84 CCP2_PRINT_REGISTER(isp, LCx_CODE(0));
85 CCP2_PRINT_REGISTER(isp, LCx_STAT_START(0));
86 CCP2_PRINT_REGISTER(isp, LCx_STAT_SIZE(0));
87 CCP2_PRINT_REGISTER(isp, LCx_SOF_ADDR(0));
88 CCP2_PRINT_REGISTER(isp, LCx_EOF_ADDR(0));
89 CCP2_PRINT_REGISTER(isp, LCx_DAT_START(0));
90 CCP2_PRINT_REGISTER(isp, LCx_DAT_SIZE(0));
91 CCP2_PRINT_REGISTER(isp, LCx_DAT_PING_ADDR(0));
92 CCP2_PRINT_REGISTER(isp, LCx_DAT_PONG_ADDR(0));
93 CCP2_PRINT_REGISTER(isp, LCx_DAT_OFST(0));
94 CCP2_PRINT_REGISTER(isp, LCM_CTRL);
95 CCP2_PRINT_REGISTER(isp, LCM_VSIZE);
96 CCP2_PRINT_REGISTER(isp, LCM_HSIZE);
97 CCP2_PRINT_REGISTER(isp, LCM_PREFETCH);
98 CCP2_PRINT_REGISTER(isp, LCM_SRC_ADDR);
99 CCP2_PRINT_REGISTER(isp, LCM_SRC_OFST);
100 CCP2_PRINT_REGISTER(isp, LCM_DST_ADDR);
101 CCP2_PRINT_REGISTER(isp, LCM_DST_OFST);
102
103 dev_dbg(isp->dev, "--------------------------------------------\n");
104 }
105
106 /*
107 * ccp2_reset - Reset the CCP2
108 * @ccp2: pointer to ISP CCP2 device
109 */
ccp2_reset(struct isp_ccp2_device * ccp2)110 static void ccp2_reset(struct isp_ccp2_device *ccp2)
111 {
112 struct isp_device *isp = to_isp_device(ccp2);
113 int i = 0;
114
115 /* Reset the CSI1/CCP2B and wait for reset to complete */
116 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG,
117 ISPCCP2_SYSCONFIG_SOFT_RESET);
118 while (!(isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSSTATUS) &
119 ISPCCP2_SYSSTATUS_RESET_DONE)) {
120 udelay(10);
121 if (i++ > 10) { /* try read 10 times */
122 dev_warn(isp->dev,
123 "omap3_isp: timeout waiting for ccp2 reset\n");
124 break;
125 }
126 }
127 }
128
129 /*
130 * ccp2_pwr_cfg - Configure the power mode settings
131 * @ccp2: pointer to ISP CCP2 device
132 */
ccp2_pwr_cfg(struct isp_ccp2_device * ccp2)133 static void ccp2_pwr_cfg(struct isp_ccp2_device *ccp2)
134 {
135 struct isp_device *isp = to_isp_device(ccp2);
136
137 isp_reg_writel(isp, ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART |
138 ((isp->revision == ISP_REVISION_15_0 && isp->autoidle) ?
139 ISPCCP2_SYSCONFIG_AUTO_IDLE : 0),
140 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_SYSCONFIG);
141 }
142
143 /*
144 * ccp2_if_enable - Enable CCP2 interface.
145 * @ccp2: pointer to ISP CCP2 device
146 * @enable: enable/disable flag
147 */
ccp2_if_enable(struct isp_ccp2_device * ccp2,u8 enable)148 static int ccp2_if_enable(struct isp_ccp2_device *ccp2, u8 enable)
149 {
150 struct isp_device *isp = to_isp_device(ccp2);
151 int ret;
152 int i;
153
154 if (enable && ccp2->vdds_csib) {
155 ret = regulator_enable(ccp2->vdds_csib);
156 if (ret < 0)
157 return ret;
158 }
159
160 /* Enable/Disable all the LCx channels */
161 for (i = 0; i < CCP2_LCx_CHANS_NUM; i++)
162 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(i),
163 ISPCCP2_LCx_CTRL_CHAN_EN,
164 enable ? ISPCCP2_LCx_CTRL_CHAN_EN : 0);
165
166 /* Enable/Disable ccp2 interface in ccp2 mode */
167 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
168 ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN,
169 enable ? (ISPCCP2_CTRL_MODE | ISPCCP2_CTRL_IF_EN) : 0);
170
171 if (!enable && ccp2->vdds_csib)
172 regulator_disable(ccp2->vdds_csib);
173
174 return 0;
175 }
176
177 /*
178 * ccp2_mem_enable - Enable CCP2 memory interface.
179 * @ccp2: pointer to ISP CCP2 device
180 * @enable: enable/disable flag
181 */
ccp2_mem_enable(struct isp_ccp2_device * ccp2,u8 enable)182 static void ccp2_mem_enable(struct isp_ccp2_device *ccp2, u8 enable)
183 {
184 struct isp_device *isp = to_isp_device(ccp2);
185
186 if (enable)
187 ccp2_if_enable(ccp2, 0);
188
189 /* Enable/Disable ccp2 interface in ccp2 mode */
190 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
191 ISPCCP2_CTRL_MODE, enable ? ISPCCP2_CTRL_MODE : 0);
192
193 isp_reg_clr_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL,
194 ISPCCP2_LCM_CTRL_CHAN_EN,
195 enable ? ISPCCP2_LCM_CTRL_CHAN_EN : 0);
196 }
197
198 /*
199 * ccp2_phyif_config - Initialize CCP2 phy interface config
200 * @ccp2: Pointer to ISP CCP2 device
201 * @buscfg: CCP2 platform data
202 *
203 * Configure the CCP2 physical interface module from platform data.
204 *
205 * Returns -EIO if strobe is chosen in CSI1 mode, or 0 on success.
206 */
ccp2_phyif_config(struct isp_ccp2_device * ccp2,const struct isp_ccp2_cfg * buscfg)207 static int ccp2_phyif_config(struct isp_ccp2_device *ccp2,
208 const struct isp_ccp2_cfg *buscfg)
209 {
210 struct isp_device *isp = to_isp_device(ccp2);
211 u32 val;
212
213 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) |
214 ISPCCP2_CTRL_MODE;
215 /* Data/strobe physical layer */
216 BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK,
217 buscfg->phy_layer);
218 BIT_SET(val, ISPCCP2_CTRL_IO_OUT_SEL_SHIFT,
219 ISPCCP2_CTRL_IO_OUT_SEL_MASK, buscfg->ccp2_mode);
220 BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK,
221 buscfg->strobe_clk_pol);
222 BIT_SET(val, ISPCCP2_CTRL_VP_CLK_POL_SHIFT,
223 ISPCCP2_CTRL_VP_CLK_POL_MASK, buscfg->vp_clk_pol);
224 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
225
226 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
227 if (!(val & ISPCCP2_CTRL_MODE)) {
228 if (buscfg->ccp2_mode == ISP_CCP2_MODE_CCP2)
229 dev_warn(isp->dev, "OMAP3 CCP2 bus not available\n");
230 if (buscfg->phy_layer == ISP_CCP2_PHY_DATA_STROBE)
231 /* Strobe mode requires CCP2 */
232 return -EIO;
233 }
234
235 return 0;
236 }
237
238 /*
239 * ccp2_vp_config - Initialize CCP2 video port interface.
240 * @ccp2: Pointer to ISP CCP2 device
241 * @vpclk_div: Video port divisor
242 *
243 * Configure the CCP2 video port with the given clock divisor. The valid divisor
244 * values depend on the ISP revision:
245 *
246 * - revision 1.0 and 2.0 1 to 4
247 * - revision 15.0 1 to 65536
248 *
249 * The exact divisor value used might differ from the requested value, as ISP
250 * revision 15.0 represent the divisor by 65536 divided by an integer.
251 */
ccp2_vp_config(struct isp_ccp2_device * ccp2,unsigned int vpclk_div)252 static void ccp2_vp_config(struct isp_ccp2_device *ccp2,
253 unsigned int vpclk_div)
254 {
255 struct isp_device *isp = to_isp_device(ccp2);
256 u32 val;
257
258 /* ISPCCP2_CTRL Video port */
259 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
260 val |= ISPCCP2_CTRL_VP_ONLY_EN; /* Disable the memory write port */
261
262 if (isp->revision == ISP_REVISION_15_0) {
263 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 65536);
264 vpclk_div = min(ISPCCP2_VPCLK_FRACDIV / vpclk_div, 65535U);
265 BIT_SET(val, ISPCCP2_CTRL_VPCLK_DIV_SHIFT,
266 ISPCCP2_CTRL_VPCLK_DIV_MASK, vpclk_div);
267 } else {
268 vpclk_div = clamp_t(unsigned int, vpclk_div, 1, 4);
269 BIT_SET(val, ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT,
270 ISPCCP2_CTRL_VP_OUT_CTRL_MASK, vpclk_div - 1);
271 }
272
273 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);
274 }
275
276 /*
277 * ccp2_lcx_config - Initialize CCP2 logical channel interface.
278 * @ccp2: Pointer to ISP CCP2 device
279 * @config: Pointer to ISP LCx config structure.
280 *
281 * This will analyze the parameters passed by the interface config
282 * and configure CSI1/CCP2 logical channel
283 *
284 */
ccp2_lcx_config(struct isp_ccp2_device * ccp2,struct isp_interface_lcx_config * config)285 static void ccp2_lcx_config(struct isp_ccp2_device *ccp2,
286 struct isp_interface_lcx_config *config)
287 {
288 struct isp_device *isp = to_isp_device(ccp2);
289 u32 val, format;
290
291 switch (config->format) {
292 case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
293 format = ISPCCP2_LCx_CTRL_FORMAT_RAW8_DPCM10_VP;
294 break;
295 case MEDIA_BUS_FMT_SGRBG10_1X10:
296 default:
297 format = ISPCCP2_LCx_CTRL_FORMAT_RAW10_VP; /* RAW10+VP */
298 break;
299 }
300 /* ISPCCP2_LCx_CTRL logical channel #0 */
301 val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0))
302 | (ISPCCP2_LCx_CTRL_REGION_EN); /* Region */
303
304 if (isp->revision == ISP_REVISION_15_0) {
305 /* CRC */
306 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0,
307 ISPCCP2_LCx_CTRL_CRC_MASK,
308 config->crc);
309 /* Format = RAW10+VP or RAW8+DPCM10+VP*/
310 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0,
311 ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0, format);
312 } else {
313 BIT_SET(val, ISPCCP2_LCx_CTRL_CRC_SHIFT,
314 ISPCCP2_LCx_CTRL_CRC_MASK,
315 config->crc);
316
317 BIT_SET(val, ISPCCP2_LCx_CTRL_FORMAT_SHIFT,
318 ISPCCP2_LCx_CTRL_FORMAT_MASK, format);
319 }
320 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_CTRL(0));
321
322 /* ISPCCP2_DAT_START for logical channel #0 */
323 isp_reg_writel(isp, config->data_start << ISPCCP2_LCx_DAT_SHIFT,
324 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_START(0));
325
326 /* ISPCCP2_DAT_SIZE for logical channel #0 */
327 isp_reg_writel(isp, config->data_size << ISPCCP2_LCx_DAT_SHIFT,
328 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCx_DAT_SIZE(0));
329
330 /* Enable error IRQs for logical channel #0 */
331 val = ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
332 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
333 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
334 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
335 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
336 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
337
338 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQSTATUS);
339 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LC01_IRQENABLE, val);
340 }
341
342 /*
343 * ccp2_if_configure - Configure ccp2 with data from sensor
344 * @ccp2: Pointer to ISP CCP2 device
345 *
346 * Return 0 on success or a negative error code
347 */
ccp2_if_configure(struct isp_ccp2_device * ccp2)348 static int ccp2_if_configure(struct isp_ccp2_device *ccp2)
349 {
350 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
351 const struct isp_bus_cfg *buscfg;
352 struct v4l2_mbus_framefmt *format;
353 struct media_pad *pad;
354 struct v4l2_subdev *sensor;
355 u32 lines = 0;
356 int ret;
357
358 ccp2_pwr_cfg(ccp2);
359
360 pad = media_entity_remote_pad(&ccp2->pads[CCP2_PAD_SINK]);
361 sensor = media_entity_to_v4l2_subdev(pad->entity);
362 buscfg = v4l2_subdev_to_bus_cfg(pipe->external);
363
364 ret = ccp2_phyif_config(ccp2, &buscfg->bus.ccp2);
365 if (ret < 0)
366 return ret;
367
368 ccp2_vp_config(ccp2, buscfg->bus.ccp2.vpclk_div + 1);
369
370 v4l2_subdev_call(sensor, sensor, g_skip_top_lines, &lines);
371
372 format = &ccp2->formats[CCP2_PAD_SINK];
373
374 ccp2->if_cfg.data_start = lines;
375 ccp2->if_cfg.crc = buscfg->bus.ccp2.crc;
376 ccp2->if_cfg.format = format->code;
377 ccp2->if_cfg.data_size = format->height;
378
379 ccp2_lcx_config(ccp2, &ccp2->if_cfg);
380
381 return 0;
382 }
383
ccp2_adjust_bandwidth(struct isp_ccp2_device * ccp2)384 static int ccp2_adjust_bandwidth(struct isp_ccp2_device *ccp2)
385 {
386 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
387 struct isp_device *isp = to_isp_device(ccp2);
388 const struct v4l2_mbus_framefmt *ofmt = &ccp2->formats[CCP2_PAD_SOURCE];
389 unsigned long l3_ick = pipe->l3_ick;
390 struct v4l2_fract *timeperframe;
391 unsigned int vpclk_div = 2;
392 unsigned int value;
393 u64 bound;
394 u64 area;
395
396 /* Compute the minimum clock divisor, based on the pipeline maximum
397 * data rate. This is an absolute lower bound if we don't want SBL
398 * overflows, so round the value up.
399 */
400 vpclk_div = max_t(unsigned int, DIV_ROUND_UP(l3_ick, pipe->max_rate),
401 vpclk_div);
402
403 /* Compute the maximum clock divisor, based on the requested frame rate.
404 * This is a soft lower bound to achieve a frame rate equal or higher
405 * than the requested value, so round the value down.
406 */
407 timeperframe = &pipe->max_timeperframe;
408
409 if (timeperframe->numerator) {
410 area = ofmt->width * ofmt->height;
411 bound = div_u64(area * timeperframe->denominator,
412 timeperframe->numerator);
413 value = min_t(u64, bound, l3_ick);
414 vpclk_div = max_t(unsigned int, l3_ick / value, vpclk_div);
415 }
416
417 dev_dbg(isp->dev, "%s: minimum clock divisor = %u\n", __func__,
418 vpclk_div);
419
420 return vpclk_div;
421 }
422
423 /*
424 * ccp2_mem_configure - Initialize CCP2 memory input/output interface
425 * @ccp2: Pointer to ISP CCP2 device
426 * @config: Pointer to ISP mem interface config structure
427 *
428 * This will analyze the parameters passed by the interface config
429 * structure, and configure the respective registers for proper
430 * CSI1/CCP2 memory input.
431 */
ccp2_mem_configure(struct isp_ccp2_device * ccp2,struct isp_interface_mem_config * config)432 static void ccp2_mem_configure(struct isp_ccp2_device *ccp2,
433 struct isp_interface_mem_config *config)
434 {
435 struct isp_device *isp = to_isp_device(ccp2);
436 u32 sink_pixcode = ccp2->formats[CCP2_PAD_SINK].code;
437 u32 source_pixcode = ccp2->formats[CCP2_PAD_SOURCE].code;
438 unsigned int dpcm_decompress = 0;
439 u32 val, hwords;
440
441 if (sink_pixcode != source_pixcode &&
442 sink_pixcode == MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8)
443 dpcm_decompress = 1;
444
445 ccp2_pwr_cfg(ccp2);
446
447 /* Hsize, Skip */
448 isp_reg_writel(isp, ISPCCP2_LCM_HSIZE_SKIP_MIN |
449 (config->hsize_count << ISPCCP2_LCM_HSIZE_SHIFT),
450 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_HSIZE);
451
452 /* Vsize, no. of lines */
453 isp_reg_writel(isp, config->vsize_count << ISPCCP2_LCM_VSIZE_SHIFT,
454 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_VSIZE);
455
456 if (ccp2->video_in.bpl_padding == 0)
457 config->src_ofst = 0;
458 else
459 config->src_ofst = ccp2->video_in.bpl_value;
460
461 isp_reg_writel(isp, config->src_ofst, OMAP3_ISP_IOMEM_CCP2,
462 ISPCCP2_LCM_SRC_OFST);
463
464 /* Source and Destination formats */
465 val = ISPCCP2_LCM_CTRL_DST_FORMAT_RAW10 <<
466 ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT;
467
468 if (dpcm_decompress) {
469 /* source format is RAW8 */
470 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW8 <<
471 ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
472
473 /* RAW8 + DPCM10 - simple predictor */
474 val |= ISPCCP2_LCM_CTRL_SRC_DPCM_PRED;
475
476 /* enable source DPCM decompression */
477 val |= ISPCCP2_LCM_CTRL_SRC_DECOMPR_DPCM10 <<
478 ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT;
479 } else {
480 /* source format is RAW10 */
481 val |= ISPCCP2_LCM_CTRL_SRC_FORMAT_RAW10 <<
482 ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT;
483 }
484
485 /* Burst size to 32x64 */
486 val |= ISPCCP2_LCM_CTRL_BURST_SIZE_32X <<
487 ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT;
488
489 isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_CTRL);
490
491 /* Prefetch setup */
492 if (dpcm_decompress)
493 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
494 config->hsize_count) >> 3;
495 else
496 hwords = (ISPCCP2_LCM_HSIZE_SKIP_MIN +
497 config->hsize_count) >> 2;
498
499 isp_reg_writel(isp, hwords << ISPCCP2_LCM_PREFETCH_SHIFT,
500 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_PREFETCH);
501
502 /* Video port */
503 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL,
504 ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE);
505 ccp2_vp_config(ccp2, ccp2_adjust_bandwidth(ccp2));
506
507 /* Clear LCM interrupts */
508 isp_reg_writel(isp, ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ |
509 ISPCCP2_LCM_IRQSTATUS_EOF_IRQ,
510 OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQSTATUS);
511
512 /* Enable LCM interrupts */
513 isp_reg_set(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_IRQENABLE,
514 ISPCCP2_LCM_IRQSTATUS_EOF_IRQ |
515 ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ);
516 }
517
518 /*
519 * ccp2_set_inaddr - Sets memory address of input frame.
520 * @ccp2: Pointer to ISP CCP2 device
521 * @addr: 32bit memory address aligned on 32byte boundary.
522 *
523 * Configures the memory address from which the input frame is to be read.
524 */
ccp2_set_inaddr(struct isp_ccp2_device * ccp2,u32 addr)525 static void ccp2_set_inaddr(struct isp_ccp2_device *ccp2, u32 addr)
526 {
527 struct isp_device *isp = to_isp_device(ccp2);
528
529 isp_reg_writel(isp, addr, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_LCM_SRC_ADDR);
530 }
531
532 /* -----------------------------------------------------------------------------
533 * Interrupt handling
534 */
535
ccp2_isr_buffer(struct isp_ccp2_device * ccp2)536 static void ccp2_isr_buffer(struct isp_ccp2_device *ccp2)
537 {
538 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
539 struct isp_buffer *buffer;
540
541 buffer = omap3isp_video_buffer_next(&ccp2->video_in);
542 if (buffer != NULL)
543 ccp2_set_inaddr(ccp2, buffer->dma);
544
545 pipe->state |= ISP_PIPELINE_IDLE_INPUT;
546
547 if (ccp2->state == ISP_PIPELINE_STREAM_SINGLESHOT) {
548 if (isp_pipeline_ready(pipe))
549 omap3isp_pipeline_set_stream(pipe,
550 ISP_PIPELINE_STREAM_SINGLESHOT);
551 }
552 }
553
554 /*
555 * omap3isp_ccp2_isr - Handle ISP CCP2 interrupts
556 * @ccp2: Pointer to ISP CCP2 device
557 *
558 * This will handle the CCP2 interrupts
559 */
omap3isp_ccp2_isr(struct isp_ccp2_device * ccp2)560 void omap3isp_ccp2_isr(struct isp_ccp2_device *ccp2)
561 {
562 struct isp_pipeline *pipe = to_isp_pipeline(&ccp2->subdev.entity);
563 struct isp_device *isp = to_isp_device(ccp2);
564 static const u32 ISPCCP2_LC01_ERROR =
565 ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ |
566 ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ |
567 ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ |
568 ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ |
569 ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ |
570 ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ;
571 u32 lcx_irqstatus, lcm_irqstatus;
572
573 /* First clear the interrupts */
574 lcx_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
575 ISPCCP2_LC01_IRQSTATUS);
576 isp_reg_writel(isp, lcx_irqstatus, OMAP3_ISP_IOMEM_CCP2,
577 ISPCCP2_LC01_IRQSTATUS);
578
579 lcm_irqstatus = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2,
580 ISPCCP2_LCM_IRQSTATUS);
581 isp_reg_writel(isp, lcm_irqstatus, OMAP3_ISP_IOMEM_CCP2,
582 ISPCCP2_LCM_IRQSTATUS);
583 /* Errors */
584 if (lcx_irqstatus & ISPCCP2_LC01_ERROR) {
585 pipe->error = true;
586 dev_dbg(isp->dev, "CCP2 err:%x\n", lcx_irqstatus);
587 return;
588 }
589
590 if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ) {
591 pipe->error = true;
592 dev_dbg(isp->dev, "CCP2 OCP err:%x\n", lcm_irqstatus);
593 }
594
595 if (omap3isp_module_sync_is_stopping(&ccp2->wait, &ccp2->stopping))
596 return;
597
598 /* Handle queued buffers on frame end interrupts */
599 if (lcm_irqstatus & ISPCCP2_LCM_IRQSTATUS_EOF_IRQ)
600 ccp2_isr_buffer(ccp2);
601 }
602
603 /* -----------------------------------------------------------------------------
604 * V4L2 subdev operations
605 */
606
607 static const unsigned int ccp2_fmts[] = {
608 MEDIA_BUS_FMT_SGRBG10_1X10,
609 MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
610 };
611
612 /*
613 * __ccp2_get_format - helper function for getting ccp2 format
614 * @ccp2 : Pointer to ISP CCP2 device
615 * @cfg: V4L2 subdev pad configuration
616 * @pad : pad number
617 * @which : wanted subdev format
618 * return format structure or NULL on error
619 */
620 static struct v4l2_mbus_framefmt *
__ccp2_get_format(struct isp_ccp2_device * ccp2,struct v4l2_subdev_pad_config * cfg,unsigned int pad,enum v4l2_subdev_format_whence which)621 __ccp2_get_format(struct isp_ccp2_device *ccp2, struct v4l2_subdev_pad_config *cfg,
622 unsigned int pad, enum v4l2_subdev_format_whence which)
623 {
624 if (which == V4L2_SUBDEV_FORMAT_TRY)
625 return v4l2_subdev_get_try_format(&ccp2->subdev, cfg, pad);
626 else
627 return &ccp2->formats[pad];
628 }
629
630 /*
631 * ccp2_try_format - Handle try format by pad subdev method
632 * @ccp2 : Pointer to ISP CCP2 device
633 * @cfg: V4L2 subdev pad configuration
634 * @pad : pad num
635 * @fmt : pointer to v4l2 mbus format structure
636 * @which : wanted subdev format
637 */
ccp2_try_format(struct isp_ccp2_device * ccp2,struct v4l2_subdev_pad_config * cfg,unsigned int pad,struct v4l2_mbus_framefmt * fmt,enum v4l2_subdev_format_whence which)638 static void ccp2_try_format(struct isp_ccp2_device *ccp2,
639 struct v4l2_subdev_pad_config *cfg, unsigned int pad,
640 struct v4l2_mbus_framefmt *fmt,
641 enum v4l2_subdev_format_whence which)
642 {
643 struct v4l2_mbus_framefmt *format;
644
645 switch (pad) {
646 case CCP2_PAD_SINK:
647 if (fmt->code != MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8)
648 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
649
650 if (ccp2->input == CCP2_INPUT_SENSOR) {
651 fmt->width = clamp_t(u32, fmt->width,
652 ISPCCP2_DAT_START_MIN,
653 ISPCCP2_DAT_START_MAX);
654 fmt->height = clamp_t(u32, fmt->height,
655 ISPCCP2_DAT_SIZE_MIN,
656 ISPCCP2_DAT_SIZE_MAX);
657 } else if (ccp2->input == CCP2_INPUT_MEMORY) {
658 fmt->width = clamp_t(u32, fmt->width,
659 ISPCCP2_LCM_HSIZE_COUNT_MIN,
660 ISPCCP2_LCM_HSIZE_COUNT_MAX);
661 fmt->height = clamp_t(u32, fmt->height,
662 ISPCCP2_LCM_VSIZE_MIN,
663 ISPCCP2_LCM_VSIZE_MAX);
664 }
665 break;
666
667 case CCP2_PAD_SOURCE:
668 /* Source format - copy sink format and change pixel code
669 * to SGRBG10_1X10 as we don't support CCP2 write to memory.
670 * When CCP2 write to memory feature will be added this
671 * should be changed properly.
672 */
673 format = __ccp2_get_format(ccp2, cfg, CCP2_PAD_SINK, which);
674 memcpy(fmt, format, sizeof(*fmt));
675 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
676 break;
677 }
678
679 fmt->field = V4L2_FIELD_NONE;
680 fmt->colorspace = V4L2_COLORSPACE_SRGB;
681 }
682
683 /*
684 * ccp2_enum_mbus_code - Handle pixel format enumeration
685 * @sd : pointer to v4l2 subdev structure
686 * @cfg: V4L2 subdev pad configuration
687 * @code : pointer to v4l2_subdev_mbus_code_enum structure
688 * return -EINVAL or zero on success
689 */
ccp2_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)690 static int ccp2_enum_mbus_code(struct v4l2_subdev *sd,
691 struct v4l2_subdev_pad_config *cfg,
692 struct v4l2_subdev_mbus_code_enum *code)
693 {
694 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
695 struct v4l2_mbus_framefmt *format;
696
697 if (code->pad == CCP2_PAD_SINK) {
698 if (code->index >= ARRAY_SIZE(ccp2_fmts))
699 return -EINVAL;
700
701 code->code = ccp2_fmts[code->index];
702 } else {
703 if (code->index != 0)
704 return -EINVAL;
705
706 format = __ccp2_get_format(ccp2, cfg, CCP2_PAD_SINK,
707 code->which);
708 code->code = format->code;
709 }
710
711 return 0;
712 }
713
ccp2_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)714 static int ccp2_enum_frame_size(struct v4l2_subdev *sd,
715 struct v4l2_subdev_pad_config *cfg,
716 struct v4l2_subdev_frame_size_enum *fse)
717 {
718 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
719 struct v4l2_mbus_framefmt format;
720
721 if (fse->index != 0)
722 return -EINVAL;
723
724 format.code = fse->code;
725 format.width = 1;
726 format.height = 1;
727 ccp2_try_format(ccp2, cfg, fse->pad, &format, fse->which);
728 fse->min_width = format.width;
729 fse->min_height = format.height;
730
731 if (format.code != fse->code)
732 return -EINVAL;
733
734 format.code = fse->code;
735 format.width = -1;
736 format.height = -1;
737 ccp2_try_format(ccp2, cfg, fse->pad, &format, fse->which);
738 fse->max_width = format.width;
739 fse->max_height = format.height;
740
741 return 0;
742 }
743
744 /*
745 * ccp2_get_format - Handle get format by pads subdev method
746 * @sd : pointer to v4l2 subdev structure
747 * @cfg: V4L2 subdev pad configuration
748 * @fmt : pointer to v4l2 subdev format structure
749 * return -EINVAL or zero on success
750 */
ccp2_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)751 static int ccp2_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
752 struct v4l2_subdev_format *fmt)
753 {
754 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
755 struct v4l2_mbus_framefmt *format;
756
757 format = __ccp2_get_format(ccp2, cfg, fmt->pad, fmt->which);
758 if (format == NULL)
759 return -EINVAL;
760
761 fmt->format = *format;
762 return 0;
763 }
764
765 /*
766 * ccp2_set_format - Handle set format by pads subdev method
767 * @sd : pointer to v4l2 subdev structure
768 * @cfg: V4L2 subdev pad configuration
769 * @fmt : pointer to v4l2 subdev format structure
770 * returns zero
771 */
ccp2_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)772 static int ccp2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
773 struct v4l2_subdev_format *fmt)
774 {
775 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
776 struct v4l2_mbus_framefmt *format;
777
778 format = __ccp2_get_format(ccp2, cfg, fmt->pad, fmt->which);
779 if (format == NULL)
780 return -EINVAL;
781
782 ccp2_try_format(ccp2, cfg, fmt->pad, &fmt->format, fmt->which);
783 *format = fmt->format;
784
785 /* Propagate the format from sink to source */
786 if (fmt->pad == CCP2_PAD_SINK) {
787 format = __ccp2_get_format(ccp2, cfg, CCP2_PAD_SOURCE,
788 fmt->which);
789 *format = fmt->format;
790 ccp2_try_format(ccp2, cfg, CCP2_PAD_SOURCE, format, fmt->which);
791 }
792
793 return 0;
794 }
795
796 /*
797 * ccp2_init_formats - Initialize formats on all pads
798 * @sd: ISP CCP2 V4L2 subdevice
799 * @fh: V4L2 subdev file handle
800 *
801 * Initialize all pad formats with default values. If fh is not NULL, try
802 * formats are initialized on the file handle. Otherwise active formats are
803 * initialized on the device.
804 */
ccp2_init_formats(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)805 static int ccp2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
806 {
807 struct v4l2_subdev_format format;
808
809 memset(&format, 0, sizeof(format));
810 format.pad = CCP2_PAD_SINK;
811 format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
812 format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
813 format.format.width = 4096;
814 format.format.height = 4096;
815 ccp2_set_format(sd, fh ? fh->pad : NULL, &format);
816
817 return 0;
818 }
819
820 /*
821 * ccp2_s_stream - Enable/Disable streaming on ccp2 subdev
822 * @sd : pointer to v4l2 subdev structure
823 * @enable: 1 == Enable, 0 == Disable
824 * return zero
825 */
ccp2_s_stream(struct v4l2_subdev * sd,int enable)826 static int ccp2_s_stream(struct v4l2_subdev *sd, int enable)
827 {
828 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
829 struct isp_device *isp = to_isp_device(ccp2);
830 struct device *dev = to_device(ccp2);
831 int ret;
832
833 if (ccp2->state == ISP_PIPELINE_STREAM_STOPPED) {
834 if (enable == ISP_PIPELINE_STREAM_STOPPED)
835 return 0;
836 atomic_set(&ccp2->stopping, 0);
837 }
838
839 switch (enable) {
840 case ISP_PIPELINE_STREAM_CONTINUOUS:
841 if (ccp2->phy) {
842 ret = omap3isp_csiphy_acquire(ccp2->phy, &sd->entity);
843 if (ret < 0)
844 return ret;
845 }
846
847 ccp2_if_configure(ccp2);
848 ccp2_print_status(ccp2);
849
850 /* Enable CSI1/CCP2 interface */
851 ret = ccp2_if_enable(ccp2, 1);
852 if (ret < 0) {
853 if (ccp2->phy)
854 omap3isp_csiphy_release(ccp2->phy);
855 return ret;
856 }
857 break;
858
859 case ISP_PIPELINE_STREAM_SINGLESHOT:
860 if (ccp2->state != ISP_PIPELINE_STREAM_SINGLESHOT) {
861 struct v4l2_mbus_framefmt *format;
862
863 format = &ccp2->formats[CCP2_PAD_SINK];
864
865 ccp2->mem_cfg.hsize_count = format->width;
866 ccp2->mem_cfg.vsize_count = format->height;
867 ccp2->mem_cfg.src_ofst = 0;
868
869 ccp2_mem_configure(ccp2, &ccp2->mem_cfg);
870 omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI1_READ);
871 ccp2_print_status(ccp2);
872 }
873 ccp2_mem_enable(ccp2, 1);
874 break;
875
876 case ISP_PIPELINE_STREAM_STOPPED:
877 if (omap3isp_module_sync_idle(&sd->entity, &ccp2->wait,
878 &ccp2->stopping))
879 dev_dbg(dev, "%s: module stop timeout.\n", sd->name);
880 if (ccp2->input == CCP2_INPUT_MEMORY) {
881 ccp2_mem_enable(ccp2, 0);
882 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI1_READ);
883 } else if (ccp2->input == CCP2_INPUT_SENSOR) {
884 /* Disable CSI1/CCP2 interface */
885 ccp2_if_enable(ccp2, 0);
886 if (ccp2->phy)
887 omap3isp_csiphy_release(ccp2->phy);
888 }
889 break;
890 }
891
892 ccp2->state = enable;
893 return 0;
894 }
895
896 /* subdev video operations */
897 static const struct v4l2_subdev_video_ops ccp2_sd_video_ops = {
898 .s_stream = ccp2_s_stream,
899 };
900
901 /* subdev pad operations */
902 static const struct v4l2_subdev_pad_ops ccp2_sd_pad_ops = {
903 .enum_mbus_code = ccp2_enum_mbus_code,
904 .enum_frame_size = ccp2_enum_frame_size,
905 .get_fmt = ccp2_get_format,
906 .set_fmt = ccp2_set_format,
907 };
908
909 /* subdev operations */
910 static const struct v4l2_subdev_ops ccp2_sd_ops = {
911 .video = &ccp2_sd_video_ops,
912 .pad = &ccp2_sd_pad_ops,
913 };
914
915 /* subdev internal operations */
916 static const struct v4l2_subdev_internal_ops ccp2_sd_internal_ops = {
917 .open = ccp2_init_formats,
918 };
919
920 /* --------------------------------------------------------------------------
921 * ISP ccp2 video device node
922 */
923
924 /*
925 * ccp2_video_queue - Queue video buffer.
926 * @video : Pointer to isp video structure
927 * @buffer: Pointer to isp_buffer structure
928 * return -EIO or zero on success
929 */
ccp2_video_queue(struct isp_video * video,struct isp_buffer * buffer)930 static int ccp2_video_queue(struct isp_video *video, struct isp_buffer *buffer)
931 {
932 struct isp_ccp2_device *ccp2 = &video->isp->isp_ccp2;
933
934 ccp2_set_inaddr(ccp2, buffer->dma);
935 return 0;
936 }
937
938 static const struct isp_video_operations ccp2_video_ops = {
939 .queue = ccp2_video_queue,
940 };
941
942 /* -----------------------------------------------------------------------------
943 * Media entity operations
944 */
945
946 /*
947 * ccp2_link_setup - Setup ccp2 connections.
948 * @entity : Pointer to media entity structure
949 * @local : Pointer to local pad array
950 * @remote : Pointer to remote pad array
951 * @flags : Link flags
952 * return -EINVAL on error or zero on success
953 */
ccp2_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)954 static int ccp2_link_setup(struct media_entity *entity,
955 const struct media_pad *local,
956 const struct media_pad *remote, u32 flags)
957 {
958 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
959 struct isp_ccp2_device *ccp2 = v4l2_get_subdevdata(sd);
960 unsigned int index = local->index;
961
962 /* FIXME: this is actually a hack! */
963 if (is_media_entity_v4l2_subdev(remote->entity))
964 index |= 2 << 16;
965
966 switch (index) {
967 case CCP2_PAD_SINK:
968 /* read from memory */
969 if (flags & MEDIA_LNK_FL_ENABLED) {
970 if (ccp2->input == CCP2_INPUT_SENSOR)
971 return -EBUSY;
972 ccp2->input = CCP2_INPUT_MEMORY;
973 } else {
974 if (ccp2->input == CCP2_INPUT_MEMORY)
975 ccp2->input = CCP2_INPUT_NONE;
976 }
977 break;
978
979 case CCP2_PAD_SINK | 2 << 16:
980 /* read from sensor/phy */
981 if (flags & MEDIA_LNK_FL_ENABLED) {
982 if (ccp2->input == CCP2_INPUT_MEMORY)
983 return -EBUSY;
984 ccp2->input = CCP2_INPUT_SENSOR;
985 } else {
986 if (ccp2->input == CCP2_INPUT_SENSOR)
987 ccp2->input = CCP2_INPUT_NONE;
988 } break;
989
990 case CCP2_PAD_SOURCE | 2 << 16:
991 /* write to video port/ccdc */
992 if (flags & MEDIA_LNK_FL_ENABLED)
993 ccp2->output = CCP2_OUTPUT_CCDC;
994 else
995 ccp2->output = CCP2_OUTPUT_NONE;
996 break;
997
998 default:
999 return -EINVAL;
1000 }
1001
1002 return 0;
1003 }
1004
1005 /* media operations */
1006 static const struct media_entity_operations ccp2_media_ops = {
1007 .link_setup = ccp2_link_setup,
1008 .link_validate = v4l2_subdev_link_validate,
1009 };
1010
1011 /*
1012 * omap3isp_ccp2_unregister_entities - Unregister media entities: subdev
1013 * @ccp2: Pointer to ISP CCP2 device
1014 */
omap3isp_ccp2_unregister_entities(struct isp_ccp2_device * ccp2)1015 void omap3isp_ccp2_unregister_entities(struct isp_ccp2_device *ccp2)
1016 {
1017 v4l2_device_unregister_subdev(&ccp2->subdev);
1018 omap3isp_video_unregister(&ccp2->video_in);
1019 }
1020
1021 /*
1022 * omap3isp_ccp2_register_entities - Register the subdev media entity
1023 * @ccp2: Pointer to ISP CCP2 device
1024 * @vdev: Pointer to v4l device
1025 * return negative error code or zero on success
1026 */
1027
omap3isp_ccp2_register_entities(struct isp_ccp2_device * ccp2,struct v4l2_device * vdev)1028 int omap3isp_ccp2_register_entities(struct isp_ccp2_device *ccp2,
1029 struct v4l2_device *vdev)
1030 {
1031 int ret;
1032
1033 /* Register the subdev and video nodes. */
1034 ccp2->subdev.dev = vdev->mdev->dev;
1035 ret = v4l2_device_register_subdev(vdev, &ccp2->subdev);
1036 if (ret < 0)
1037 goto error;
1038
1039 ret = omap3isp_video_register(&ccp2->video_in, vdev);
1040 if (ret < 0)
1041 goto error;
1042
1043 return 0;
1044
1045 error:
1046 omap3isp_ccp2_unregister_entities(ccp2);
1047 return ret;
1048 }
1049
1050 /* -----------------------------------------------------------------------------
1051 * ISP ccp2 initialisation and cleanup
1052 */
1053
1054 /*
1055 * ccp2_init_entities - Initialize ccp2 subdev and media entity.
1056 * @ccp2: Pointer to ISP CCP2 device
1057 * return negative error code or zero on success
1058 */
ccp2_init_entities(struct isp_ccp2_device * ccp2)1059 static int ccp2_init_entities(struct isp_ccp2_device *ccp2)
1060 {
1061 struct v4l2_subdev *sd = &ccp2->subdev;
1062 struct media_pad *pads = ccp2->pads;
1063 struct media_entity *me = &sd->entity;
1064 int ret;
1065
1066 ccp2->input = CCP2_INPUT_NONE;
1067 ccp2->output = CCP2_OUTPUT_NONE;
1068
1069 v4l2_subdev_init(sd, &ccp2_sd_ops);
1070 sd->internal_ops = &ccp2_sd_internal_ops;
1071 strscpy(sd->name, "OMAP3 ISP CCP2", sizeof(sd->name));
1072 sd->grp_id = 1 << 16; /* group ID for isp subdevs */
1073 v4l2_set_subdevdata(sd, ccp2);
1074 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1075
1076 pads[CCP2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1077 | MEDIA_PAD_FL_MUST_CONNECT;
1078 pads[CCP2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1079
1080 me->ops = &ccp2_media_ops;
1081 ret = media_entity_pads_init(me, CCP2_PADS_NUM, pads);
1082 if (ret < 0)
1083 return ret;
1084
1085 ccp2_init_formats(sd, NULL);
1086
1087 /*
1088 * The CCP2 has weird line alignment requirements, possibly caused by
1089 * DPCM8 decompression. Line length for data read from memory must be a
1090 * multiple of 128 bits (16 bytes) in continuous mode (when no padding
1091 * is present at end of lines). Additionally, if padding is used, the
1092 * padded line length must be a multiple of 32 bytes. To simplify the
1093 * implementation we use a fixed 32 bytes alignment regardless of the
1094 * input format and width. If strict 128 bits alignment support is
1095 * required ispvideo will need to be made aware of this special dual
1096 * alignment requirements.
1097 */
1098 ccp2->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1099 ccp2->video_in.bpl_alignment = 32;
1100 ccp2->video_in.bpl_max = 0xffffffe0;
1101 ccp2->video_in.isp = to_isp_device(ccp2);
1102 ccp2->video_in.ops = &ccp2_video_ops;
1103 ccp2->video_in.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1104
1105 ret = omap3isp_video_init(&ccp2->video_in, "CCP2");
1106 if (ret < 0)
1107 goto error;
1108
1109 return 0;
1110
1111 error:
1112 media_entity_cleanup(&ccp2->subdev.entity);
1113 return ret;
1114 }
1115
1116 /*
1117 * omap3isp_ccp2_init - CCP2 initialization.
1118 * @isp : Pointer to ISP device
1119 * return negative error code or zero on success
1120 */
omap3isp_ccp2_init(struct isp_device * isp)1121 int omap3isp_ccp2_init(struct isp_device *isp)
1122 {
1123 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1124 int ret;
1125
1126 init_waitqueue_head(&ccp2->wait);
1127
1128 /*
1129 * On the OMAP34xx the CSI1 receiver is operated in the CSIb IO
1130 * complex, which is powered by vdds_csib power rail. Hence the
1131 * request for the regulator.
1132 *
1133 * On the OMAP36xx, the CCP2 uses the CSI PHY1 or PHY2, shared with
1134 * the CSI2c or CSI2a receivers. The PHY then needs to be explicitly
1135 * configured.
1136 *
1137 * TODO: Don't hardcode the usage of PHY1 (shared with CSI2c).
1138 */
1139 if (isp->revision == ISP_REVISION_2_0) {
1140 ccp2->vdds_csib = devm_regulator_get(isp->dev, "vdds_csib");
1141 if (IS_ERR(ccp2->vdds_csib)) {
1142 if (PTR_ERR(ccp2->vdds_csib) == -EPROBE_DEFER) {
1143 dev_dbg(isp->dev,
1144 "Can't get regulator vdds_csib, deferring probing\n");
1145 return -EPROBE_DEFER;
1146 }
1147 dev_dbg(isp->dev,
1148 "Could not get regulator vdds_csib\n");
1149 ccp2->vdds_csib = NULL;
1150 }
1151 ccp2->phy = &isp->isp_csiphy2;
1152 } else if (isp->revision == ISP_REVISION_15_0) {
1153 ccp2->phy = &isp->isp_csiphy1;
1154 }
1155
1156 ret = ccp2_init_entities(ccp2);
1157 if (ret < 0)
1158 return ret;
1159
1160 ccp2_reset(ccp2);
1161 return 0;
1162 }
1163
1164 /*
1165 * omap3isp_ccp2_cleanup - CCP2 un-initialization
1166 * @isp : Pointer to ISP device
1167 */
omap3isp_ccp2_cleanup(struct isp_device * isp)1168 void omap3isp_ccp2_cleanup(struct isp_device *isp)
1169 {
1170 struct isp_ccp2_device *ccp2 = &isp->isp_ccp2;
1171
1172 omap3isp_video_cleanup(&ccp2->video_in);
1173 media_entity_cleanup(&ccp2->subdev.entity);
1174 }
1175
