1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 *
7 * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
8 * Younghwan Joo <yhwan.joo@samsung.com>
9 */
10 #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
11
12 #include <linux/device.h>
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/printk.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/slab.h>
21 #include <linux/types.h>
22 #include <media/v4l2-device.h>
23
24 #include "media-dev.h"
25 #include "fimc-isp-video.h"
26 #include "fimc-is-command.h"
27 #include "fimc-is-param.h"
28 #include "fimc-is-regs.h"
29 #include "fimc-is.h"
30
31 int fimc_isp_debug;
32 module_param_named(debug_isp, fimc_isp_debug, int, S_IRUGO | S_IWUSR);
33
34 static const struct fimc_fmt fimc_isp_formats[FIMC_ISP_NUM_FORMATS] = {
35 {
36 .fourcc = V4L2_PIX_FMT_SGRBG8,
37 .depth = { 8 },
38 .color = FIMC_FMT_RAW8,
39 .memplanes = 1,
40 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
41 }, {
42 .fourcc = V4L2_PIX_FMT_SGRBG10,
43 .depth = { 10 },
44 .color = FIMC_FMT_RAW10,
45 .memplanes = 1,
46 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
47 }, {
48 .fourcc = V4L2_PIX_FMT_SGRBG12,
49 .depth = { 12 },
50 .color = FIMC_FMT_RAW12,
51 .memplanes = 1,
52 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
53 },
54 };
55
56 /**
57 * fimc_isp_find_format - lookup color format by fourcc or media bus code
58 * @pixelformat: fourcc to match, ignored if null
59 * @mbus_code: media bus code to match, ignored if null
60 * @index: index to the fimc_isp_formats array, ignored if negative
61 */
fimc_isp_find_format(const u32 * pixelformat,const u32 * mbus_code,int index)62 const struct fimc_fmt *fimc_isp_find_format(const u32 *pixelformat,
63 const u32 *mbus_code, int index)
64 {
65 const struct fimc_fmt *fmt, *def_fmt = NULL;
66 unsigned int i;
67 int id = 0;
68
69 if (index >= (int)ARRAY_SIZE(fimc_isp_formats))
70 return NULL;
71
72 for (i = 0; i < ARRAY_SIZE(fimc_isp_formats); ++i) {
73 fmt = &fimc_isp_formats[i];
74 if (pixelformat && fmt->fourcc == *pixelformat)
75 return fmt;
76 if (mbus_code && fmt->mbus_code == *mbus_code)
77 return fmt;
78 if (index == id)
79 def_fmt = fmt;
80 id++;
81 }
82 return def_fmt;
83 }
84
fimc_isp_irq_handler(struct fimc_is * is)85 void fimc_isp_irq_handler(struct fimc_is *is)
86 {
87 is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20));
88 is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21));
89
90 fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP);
91 fimc_isp_video_irq_handler(is);
92
93 wake_up(&is->irq_queue);
94 }
95
96 /* Capture subdev media entity operations */
fimc_is_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)97 static int fimc_is_link_setup(struct media_entity *entity,
98 const struct media_pad *local,
99 const struct media_pad *remote, u32 flags)
100 {
101 return 0;
102 }
103
104 static const struct media_entity_operations fimc_is_subdev_media_ops = {
105 .link_setup = fimc_is_link_setup,
106 };
107
fimc_is_subdev_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)108 static int fimc_is_subdev_enum_mbus_code(struct v4l2_subdev *sd,
109 struct v4l2_subdev_pad_config *cfg,
110 struct v4l2_subdev_mbus_code_enum *code)
111 {
112 const struct fimc_fmt *fmt;
113
114 fmt = fimc_isp_find_format(NULL, NULL, code->index);
115 if (!fmt)
116 return -EINVAL;
117 code->code = fmt->mbus_code;
118 return 0;
119 }
120
fimc_isp_subdev_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)121 static int fimc_isp_subdev_get_fmt(struct v4l2_subdev *sd,
122 struct v4l2_subdev_pad_config *cfg,
123 struct v4l2_subdev_format *fmt)
124 {
125 struct fimc_isp *isp = v4l2_get_subdevdata(sd);
126 struct v4l2_mbus_framefmt *mf = &fmt->format;
127
128 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
129 *mf = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
130 return 0;
131 }
132
133 mf->colorspace = V4L2_COLORSPACE_SRGB;
134
135 mutex_lock(&isp->subdev_lock);
136
137 if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
138 /* ISP OTF input image format */
139 *mf = isp->sink_fmt;
140 } else {
141 /* ISP OTF output image format */
142 *mf = isp->src_fmt;
143
144 if (fmt->pad == FIMC_ISP_SD_PAD_SRC_FIFO) {
145 mf->colorspace = V4L2_COLORSPACE_JPEG;
146 mf->code = MEDIA_BUS_FMT_YUV10_1X30;
147 }
148 }
149
150 mutex_unlock(&isp->subdev_lock);
151
152 isp_dbg(1, sd, "%s: pad%d: fmt: 0x%x, %dx%d\n", __func__,
153 fmt->pad, mf->code, mf->width, mf->height);
154
155 return 0;
156 }
157
__isp_subdev_try_format(struct fimc_isp * isp,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)158 static void __isp_subdev_try_format(struct fimc_isp *isp,
159 struct v4l2_subdev_pad_config *cfg,
160 struct v4l2_subdev_format *fmt)
161 {
162 struct v4l2_mbus_framefmt *mf = &fmt->format;
163 struct v4l2_mbus_framefmt *format;
164
165 mf->colorspace = V4L2_COLORSPACE_SRGB;
166
167 if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
168 v4l_bound_align_image(&mf->width, FIMC_ISP_SINK_WIDTH_MIN,
169 FIMC_ISP_SINK_WIDTH_MAX, 0,
170 &mf->height, FIMC_ISP_SINK_HEIGHT_MIN,
171 FIMC_ISP_SINK_HEIGHT_MAX, 0, 0);
172 mf->code = MEDIA_BUS_FMT_SGRBG10_1X10;
173 } else {
174 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
175 format = v4l2_subdev_get_try_format(&isp->subdev, cfg,
176 FIMC_ISP_SD_PAD_SINK);
177 else
178 format = &isp->sink_fmt;
179
180 /* Allow changing format only on sink pad */
181 mf->width = format->width - FIMC_ISP_CAC_MARGIN_WIDTH;
182 mf->height = format->height - FIMC_ISP_CAC_MARGIN_HEIGHT;
183
184 if (fmt->pad == FIMC_ISP_SD_PAD_SRC_FIFO) {
185 mf->code = MEDIA_BUS_FMT_YUV10_1X30;
186 mf->colorspace = V4L2_COLORSPACE_JPEG;
187 } else {
188 mf->code = format->code;
189 }
190 }
191 }
192
fimc_isp_subdev_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)193 static int fimc_isp_subdev_set_fmt(struct v4l2_subdev *sd,
194 struct v4l2_subdev_pad_config *cfg,
195 struct v4l2_subdev_format *fmt)
196 {
197 struct fimc_isp *isp = v4l2_get_subdevdata(sd);
198 struct fimc_is *is = fimc_isp_to_is(isp);
199 struct v4l2_mbus_framefmt *mf = &fmt->format;
200 int ret = 0;
201
202 isp_dbg(1, sd, "%s: pad%d: code: 0x%x, %dx%d\n",
203 __func__, fmt->pad, mf->code, mf->width, mf->height);
204
205 mutex_lock(&isp->subdev_lock);
206 __isp_subdev_try_format(isp, cfg, fmt);
207
208 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
209 mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
210 *mf = fmt->format;
211
212 /* Propagate format to the source pads */
213 if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
214 struct v4l2_subdev_format format = *fmt;
215 unsigned int pad;
216
217 for (pad = FIMC_ISP_SD_PAD_SRC_FIFO;
218 pad < FIMC_ISP_SD_PADS_NUM; pad++) {
219 format.pad = pad;
220 __isp_subdev_try_format(isp, cfg, &format);
221 mf = v4l2_subdev_get_try_format(sd, cfg, pad);
222 *mf = format.format;
223 }
224 }
225 } else {
226 if (sd->entity.stream_count == 0) {
227 if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
228 struct v4l2_subdev_format format = *fmt;
229
230 isp->sink_fmt = *mf;
231
232 format.pad = FIMC_ISP_SD_PAD_SRC_DMA;
233 __isp_subdev_try_format(isp, cfg, &format);
234
235 isp->src_fmt = format.format;
236 __is_set_frame_size(is, &isp->src_fmt);
237 } else {
238 isp->src_fmt = *mf;
239 }
240 } else {
241 ret = -EBUSY;
242 }
243 }
244
245 mutex_unlock(&isp->subdev_lock);
246 return ret;
247 }
248
fimc_isp_subdev_s_stream(struct v4l2_subdev * sd,int on)249 static int fimc_isp_subdev_s_stream(struct v4l2_subdev *sd, int on)
250 {
251 struct fimc_isp *isp = v4l2_get_subdevdata(sd);
252 struct fimc_is *is = fimc_isp_to_is(isp);
253 int ret;
254
255 isp_dbg(1, sd, "%s: on: %d\n", __func__, on);
256
257 if (!test_bit(IS_ST_INIT_DONE, &is->state))
258 return -EBUSY;
259
260 fimc_is_mem_barrier();
261
262 if (on) {
263 if (__get_pending_param_count(is)) {
264 ret = fimc_is_itf_s_param(is, true);
265 if (ret < 0)
266 return ret;
267 }
268
269 isp_dbg(1, sd, "changing mode to %d\n", is->config_index);
270
271 ret = fimc_is_itf_mode_change(is);
272 if (ret)
273 return -EINVAL;
274
275 clear_bit(IS_ST_STREAM_ON, &is->state);
276 fimc_is_hw_stream_on(is);
277 ret = fimc_is_wait_event(is, IS_ST_STREAM_ON, 1,
278 FIMC_IS_CONFIG_TIMEOUT);
279 if (ret < 0) {
280 v4l2_err(sd, "stream on timeout\n");
281 return ret;
282 }
283 } else {
284 clear_bit(IS_ST_STREAM_OFF, &is->state);
285 fimc_is_hw_stream_off(is);
286 ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
287 FIMC_IS_CONFIG_TIMEOUT);
288 if (ret < 0) {
289 v4l2_err(sd, "stream off timeout\n");
290 return ret;
291 }
292 is->setfile.sub_index = 0;
293 }
294
295 return 0;
296 }
297
fimc_isp_subdev_s_power(struct v4l2_subdev * sd,int on)298 static int fimc_isp_subdev_s_power(struct v4l2_subdev *sd, int on)
299 {
300 struct fimc_isp *isp = v4l2_get_subdevdata(sd);
301 struct fimc_is *is = fimc_isp_to_is(isp);
302 int ret = 0;
303
304 pr_debug("on: %d\n", on);
305
306 if (on) {
307 ret = pm_runtime_get_sync(&is->pdev->dev);
308 if (ret < 0) {
309 pm_runtime_put(&is->pdev->dev);
310 return ret;
311 }
312 set_bit(IS_ST_PWR_ON, &is->state);
313
314 ret = fimc_is_start_firmware(is);
315 if (ret < 0) {
316 v4l2_err(sd, "firmware booting failed\n");
317 pm_runtime_put(&is->pdev->dev);
318 return ret;
319 }
320 set_bit(IS_ST_PWR_SUBIP_ON, &is->state);
321
322 ret = fimc_is_hw_initialize(is);
323 } else {
324 /* Close sensor */
325 if (!test_bit(IS_ST_PWR_ON, &is->state)) {
326 fimc_is_hw_close_sensor(is, 0);
327
328 ret = fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 0,
329 FIMC_IS_CONFIG_TIMEOUT);
330 if (ret < 0) {
331 v4l2_err(sd, "sensor close timeout\n");
332 return ret;
333 }
334 }
335
336 /* SUB IP power off */
337 if (test_bit(IS_ST_PWR_SUBIP_ON, &is->state)) {
338 fimc_is_hw_subip_power_off(is);
339 ret = fimc_is_wait_event(is, IS_ST_PWR_SUBIP_ON, 0,
340 FIMC_IS_CONFIG_TIMEOUT);
341 if (ret < 0) {
342 v4l2_err(sd, "sub-IP power off timeout\n");
343 return ret;
344 }
345 }
346
347 fimc_is_cpu_set_power(is, 0);
348 pm_runtime_put_sync(&is->pdev->dev);
349
350 clear_bit(IS_ST_PWR_ON, &is->state);
351 clear_bit(IS_ST_INIT_DONE, &is->state);
352 is->state = 0;
353 is->config[is->config_index].p_region_index[0] = 0;
354 is->config[is->config_index].p_region_index[1] = 0;
355 set_bit(IS_ST_IDLE, &is->state);
356 wmb();
357 }
358
359 return ret;
360 }
361
fimc_isp_subdev_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)362 static int fimc_isp_subdev_open(struct v4l2_subdev *sd,
363 struct v4l2_subdev_fh *fh)
364 {
365 struct v4l2_mbus_framefmt *format;
366 struct v4l2_mbus_framefmt fmt = {
367 .colorspace = V4L2_COLORSPACE_SRGB,
368 .code = fimc_isp_formats[0].mbus_code,
369 .width = DEFAULT_PREVIEW_STILL_WIDTH + FIMC_ISP_CAC_MARGIN_WIDTH,
370 .height = DEFAULT_PREVIEW_STILL_HEIGHT + FIMC_ISP_CAC_MARGIN_HEIGHT,
371 .field = V4L2_FIELD_NONE,
372 };
373
374 format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SINK);
375 *format = fmt;
376
377 format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SRC_FIFO);
378 fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
379 fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
380 *format = fmt;
381
382 format = v4l2_subdev_get_try_format(sd, fh->pad, FIMC_ISP_SD_PAD_SRC_DMA);
383 *format = fmt;
384
385 return 0;
386 }
387
fimc_isp_subdev_registered(struct v4l2_subdev * sd)388 static int fimc_isp_subdev_registered(struct v4l2_subdev *sd)
389 {
390 struct fimc_isp *isp = v4l2_get_subdevdata(sd);
391 int ret;
392
393 /* Use pipeline object allocated by the media device. */
394 isp->video_capture.ve.pipe = v4l2_get_subdev_hostdata(sd);
395
396 ret = fimc_isp_video_device_register(isp, sd->v4l2_dev,
397 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
398 if (ret < 0)
399 isp->video_capture.ve.pipe = NULL;
400
401 return ret;
402 }
403
fimc_isp_subdev_unregistered(struct v4l2_subdev * sd)404 static void fimc_isp_subdev_unregistered(struct v4l2_subdev *sd)
405 {
406 struct fimc_isp *isp = v4l2_get_subdevdata(sd);
407
408 fimc_isp_video_device_unregister(isp,
409 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
410 }
411
412 static const struct v4l2_subdev_internal_ops fimc_is_subdev_internal_ops = {
413 .registered = fimc_isp_subdev_registered,
414 .unregistered = fimc_isp_subdev_unregistered,
415 .open = fimc_isp_subdev_open,
416 };
417
418 static const struct v4l2_subdev_pad_ops fimc_is_subdev_pad_ops = {
419 .enum_mbus_code = fimc_is_subdev_enum_mbus_code,
420 .get_fmt = fimc_isp_subdev_get_fmt,
421 .set_fmt = fimc_isp_subdev_set_fmt,
422 };
423
424 static const struct v4l2_subdev_video_ops fimc_is_subdev_video_ops = {
425 .s_stream = fimc_isp_subdev_s_stream,
426 };
427
428 static const struct v4l2_subdev_core_ops fimc_is_core_ops = {
429 .s_power = fimc_isp_subdev_s_power,
430 };
431
432 static const struct v4l2_subdev_ops fimc_is_subdev_ops = {
433 .core = &fimc_is_core_ops,
434 .video = &fimc_is_subdev_video_ops,
435 .pad = &fimc_is_subdev_pad_ops,
436 };
437
__ctrl_set_white_balance(struct fimc_is * is,int value)438 static int __ctrl_set_white_balance(struct fimc_is *is, int value)
439 {
440 switch (value) {
441 case V4L2_WHITE_BALANCE_AUTO:
442 __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
443 break;
444 case V4L2_WHITE_BALANCE_DAYLIGHT:
445 __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
446 ISP_AWB_ILLUMINATION_DAYLIGHT);
447 break;
448 case V4L2_WHITE_BALANCE_CLOUDY:
449 __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
450 ISP_AWB_ILLUMINATION_CLOUDY);
451 break;
452 case V4L2_WHITE_BALANCE_INCANDESCENT:
453 __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
454 ISP_AWB_ILLUMINATION_TUNGSTEN);
455 break;
456 case V4L2_WHITE_BALANCE_FLUORESCENT:
457 __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION,
458 ISP_AWB_ILLUMINATION_FLUORESCENT);
459 break;
460 default:
461 return -EINVAL;
462 }
463
464 return 0;
465 }
466
__ctrl_set_aewb_lock(struct fimc_is * is,struct v4l2_ctrl * ctrl)467 static int __ctrl_set_aewb_lock(struct fimc_is *is,
468 struct v4l2_ctrl *ctrl)
469 {
470 bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
471 bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
472 struct isp_param *isp = &is->is_p_region->parameter.isp;
473 int cmd, ret;
474
475 cmd = ae_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
476 isp->aa.cmd = cmd;
477 isp->aa.target = ISP_AA_TARGET_AE;
478 fimc_is_set_param_bit(is, PARAM_ISP_AA);
479 is->af.ae_lock_state = ae_lock;
480 wmb();
481
482 ret = fimc_is_itf_s_param(is, false);
483 if (ret < 0)
484 return ret;
485
486 cmd = awb_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START;
487 isp->aa.cmd = cmd;
488 isp->aa.target = ISP_AA_TARGET_AE;
489 fimc_is_set_param_bit(is, PARAM_ISP_AA);
490 is->af.awb_lock_state = awb_lock;
491 wmb();
492
493 return fimc_is_itf_s_param(is, false);
494 }
495
496 /* Supported manual ISO values */
497 static const s64 iso_qmenu[] = {
498 50, 100, 200, 400, 800,
499 };
500
__ctrl_set_iso(struct fimc_is * is,int value)501 static int __ctrl_set_iso(struct fimc_is *is, int value)
502 {
503 unsigned int idx, iso;
504
505 if (value == V4L2_ISO_SENSITIVITY_AUTO) {
506 __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
507 return 0;
508 }
509 idx = is->isp.ctrls.iso->val;
510 if (idx >= ARRAY_SIZE(iso_qmenu))
511 return -EINVAL;
512
513 iso = iso_qmenu[idx];
514 __is_set_isp_iso(is, ISP_ISO_COMMAND_MANUAL, iso);
515 return 0;
516 }
517
__ctrl_set_metering(struct fimc_is * is,unsigned int value)518 static int __ctrl_set_metering(struct fimc_is *is, unsigned int value)
519 {
520 unsigned int val;
521
522 switch (value) {
523 case V4L2_EXPOSURE_METERING_AVERAGE:
524 val = ISP_METERING_COMMAND_AVERAGE;
525 break;
526 case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
527 val = ISP_METERING_COMMAND_CENTER;
528 break;
529 case V4L2_EXPOSURE_METERING_SPOT:
530 val = ISP_METERING_COMMAND_SPOT;
531 break;
532 case V4L2_EXPOSURE_METERING_MATRIX:
533 val = ISP_METERING_COMMAND_MATRIX;
534 break;
535 default:
536 return -EINVAL;
537 }
538
539 __is_set_isp_metering(is, IS_METERING_CONFIG_CMD, val);
540 return 0;
541 }
542
__ctrl_set_afc(struct fimc_is * is,int value)543 static int __ctrl_set_afc(struct fimc_is *is, int value)
544 {
545 switch (value) {
546 case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
547 __is_set_isp_afc(is, ISP_AFC_COMMAND_DISABLE, 0);
548 break;
549 case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
550 __is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 50);
551 break;
552 case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
553 __is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 60);
554 break;
555 case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
556 __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
557 break;
558 default:
559 return -EINVAL;
560 }
561
562 return 0;
563 }
564
__ctrl_set_image_effect(struct fimc_is * is,int value)565 static int __ctrl_set_image_effect(struct fimc_is *is, int value)
566 {
567 static const u8 effects[][2] = {
568 { V4L2_COLORFX_NONE, ISP_IMAGE_EFFECT_DISABLE },
569 { V4L2_COLORFX_BW, ISP_IMAGE_EFFECT_MONOCHROME },
570 { V4L2_COLORFX_SEPIA, ISP_IMAGE_EFFECT_SEPIA },
571 { V4L2_COLORFX_NEGATIVE, ISP_IMAGE_EFFECT_NEGATIVE_MONO },
572 { 16 /* TODO */, ISP_IMAGE_EFFECT_NEGATIVE_COLOR },
573 };
574 int i;
575
576 for (i = 0; i < ARRAY_SIZE(effects); i++) {
577 if (effects[i][0] != value)
578 continue;
579
580 __is_set_isp_effect(is, effects[i][1]);
581 return 0;
582 }
583
584 return -EINVAL;
585 }
586
fimc_is_s_ctrl(struct v4l2_ctrl * ctrl)587 static int fimc_is_s_ctrl(struct v4l2_ctrl *ctrl)
588 {
589 struct fimc_isp *isp = ctrl_to_fimc_isp(ctrl);
590 struct fimc_is *is = fimc_isp_to_is(isp);
591 bool set_param = true;
592 int ret = 0;
593
594 switch (ctrl->id) {
595 case V4L2_CID_CONTRAST:
596 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST,
597 ctrl->val);
598 break;
599
600 case V4L2_CID_SATURATION:
601 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SATURATION,
602 ctrl->val);
603 break;
604
605 case V4L2_CID_SHARPNESS:
606 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS,
607 ctrl->val);
608 break;
609
610 case V4L2_CID_EXPOSURE_ABSOLUTE:
611 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE,
612 ctrl->val);
613 break;
614
615 case V4L2_CID_BRIGHTNESS:
616 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS,
617 ctrl->val);
618 break;
619
620 case V4L2_CID_HUE:
621 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE,
622 ctrl->val);
623 break;
624
625 case V4L2_CID_EXPOSURE_METERING:
626 ret = __ctrl_set_metering(is, ctrl->val);
627 break;
628
629 case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
630 ret = __ctrl_set_white_balance(is, ctrl->val);
631 break;
632
633 case V4L2_CID_3A_LOCK:
634 ret = __ctrl_set_aewb_lock(is, ctrl);
635 set_param = false;
636 break;
637
638 case V4L2_CID_ISO_SENSITIVITY_AUTO:
639 ret = __ctrl_set_iso(is, ctrl->val);
640 break;
641
642 case V4L2_CID_POWER_LINE_FREQUENCY:
643 ret = __ctrl_set_afc(is, ctrl->val);
644 break;
645
646 case V4L2_CID_COLORFX:
647 __ctrl_set_image_effect(is, ctrl->val);
648 break;
649
650 default:
651 ret = -EINVAL;
652 break;
653 }
654
655 if (ret < 0) {
656 v4l2_err(&isp->subdev, "Failed to set control: %s (%d)\n",
657 ctrl->name, ctrl->val);
658 return ret;
659 }
660
661 if (set_param && test_bit(IS_ST_STREAM_ON, &is->state))
662 return fimc_is_itf_s_param(is, true);
663
664 return 0;
665 }
666
667 static const struct v4l2_ctrl_ops fimc_isp_ctrl_ops = {
668 .s_ctrl = fimc_is_s_ctrl,
669 };
670
__isp_subdev_set_default_format(struct fimc_isp * isp)671 static void __isp_subdev_set_default_format(struct fimc_isp *isp)
672 {
673 struct fimc_is *is = fimc_isp_to_is(isp);
674
675 isp->sink_fmt.width = DEFAULT_PREVIEW_STILL_WIDTH +
676 FIMC_ISP_CAC_MARGIN_WIDTH;
677 isp->sink_fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT +
678 FIMC_ISP_CAC_MARGIN_HEIGHT;
679 isp->sink_fmt.code = MEDIA_BUS_FMT_SGRBG10_1X10;
680
681 isp->src_fmt.width = DEFAULT_PREVIEW_STILL_WIDTH;
682 isp->src_fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT;
683 isp->src_fmt.code = MEDIA_BUS_FMT_SGRBG10_1X10;
684 __is_set_frame_size(is, &isp->src_fmt);
685 }
686
fimc_isp_subdev_create(struct fimc_isp * isp)687 int fimc_isp_subdev_create(struct fimc_isp *isp)
688 {
689 const struct v4l2_ctrl_ops *ops = &fimc_isp_ctrl_ops;
690 struct v4l2_ctrl_handler *handler = &isp->ctrls.handler;
691 struct v4l2_subdev *sd = &isp->subdev;
692 struct fimc_isp_ctrls *ctrls = &isp->ctrls;
693 int ret;
694
695 mutex_init(&isp->subdev_lock);
696
697 v4l2_subdev_init(sd, &fimc_is_subdev_ops);
698
699 sd->owner = THIS_MODULE;
700 sd->grp_id = GRP_ID_FIMC_IS;
701 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
702 snprintf(sd->name, sizeof(sd->name), "FIMC-IS-ISP");
703
704 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
705 isp->subdev_pads[FIMC_ISP_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
706 isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_FIFO].flags = MEDIA_PAD_FL_SOURCE;
707 isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_DMA].flags = MEDIA_PAD_FL_SOURCE;
708 ret = media_entity_pads_init(&sd->entity, FIMC_ISP_SD_PADS_NUM,
709 isp->subdev_pads);
710 if (ret)
711 return ret;
712
713 v4l2_ctrl_handler_init(handler, 20);
714
715 ctrls->saturation = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SATURATION,
716 -2, 2, 1, 0);
717 ctrls->brightness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_BRIGHTNESS,
718 -4, 4, 1, 0);
719 ctrls->contrast = v4l2_ctrl_new_std(handler, ops, V4L2_CID_CONTRAST,
720 -2, 2, 1, 0);
721 ctrls->sharpness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SHARPNESS,
722 -2, 2, 1, 0);
723 ctrls->hue = v4l2_ctrl_new_std(handler, ops, V4L2_CID_HUE,
724 -2, 2, 1, 0);
725
726 ctrls->auto_wb = v4l2_ctrl_new_std_menu(handler, ops,
727 V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
728 8, ~0x14e, V4L2_WHITE_BALANCE_AUTO);
729
730 ctrls->exposure = v4l2_ctrl_new_std(handler, ops,
731 V4L2_CID_EXPOSURE_ABSOLUTE,
732 -4, 4, 1, 0);
733
734 ctrls->exp_metering = v4l2_ctrl_new_std_menu(handler, ops,
735 V4L2_CID_EXPOSURE_METERING, 3,
736 ~0xf, V4L2_EXPOSURE_METERING_AVERAGE);
737
738 v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_POWER_LINE_FREQUENCY,
739 V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
740 V4L2_CID_POWER_LINE_FREQUENCY_AUTO);
741 /* ISO sensitivity */
742 ctrls->auto_iso = v4l2_ctrl_new_std_menu(handler, ops,
743 V4L2_CID_ISO_SENSITIVITY_AUTO, 1, 0,
744 V4L2_ISO_SENSITIVITY_AUTO);
745
746 ctrls->iso = v4l2_ctrl_new_int_menu(handler, ops,
747 V4L2_CID_ISO_SENSITIVITY, ARRAY_SIZE(iso_qmenu) - 1,
748 ARRAY_SIZE(iso_qmenu)/2 - 1, iso_qmenu);
749
750 ctrls->aewb_lock = v4l2_ctrl_new_std(handler, ops,
751 V4L2_CID_3A_LOCK, 0, 0x3, 0, 0);
752
753 /* TODO: Add support for NEGATIVE_COLOR option */
754 ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_COLORFX,
755 V4L2_COLORFX_SET_CBCR + 1, ~0x1000f, V4L2_COLORFX_NONE);
756
757 if (handler->error) {
758 media_entity_cleanup(&sd->entity);
759 return handler->error;
760 }
761
762 v4l2_ctrl_auto_cluster(2, &ctrls->auto_iso,
763 V4L2_ISO_SENSITIVITY_MANUAL, false);
764
765 sd->ctrl_handler = handler;
766 sd->internal_ops = &fimc_is_subdev_internal_ops;
767 sd->entity.ops = &fimc_is_subdev_media_ops;
768 v4l2_set_subdevdata(sd, isp);
769
770 __isp_subdev_set_default_format(isp);
771
772 return 0;
773 }
774
fimc_isp_subdev_destroy(struct fimc_isp * isp)775 void fimc_isp_subdev_destroy(struct fimc_isp *isp)
776 {
777 struct v4l2_subdev *sd = &isp->subdev;
778
779 v4l2_device_unregister_subdev(sd);
780 media_entity_cleanup(&sd->entity);
781 v4l2_ctrl_handler_free(&isp->ctrls.handler);
782 v4l2_set_subdevdata(sd, NULL);
783 }
784
