1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * netup_unidvb_core.c
4 *
5 * Main module for NetUP Universal Dual DVB-CI
6 *
7 * Copyright (C) 2014 NetUP Inc.
8 * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
9 * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
10 */
11
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kmod.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/list.h>
21 #include <media/videobuf2-v4l2.h>
22 #include <media/videobuf2-vmalloc.h>
23
24 #include "netup_unidvb.h"
25 #include "cxd2841er.h"
26 #include "horus3a.h"
27 #include "ascot2e.h"
28 #include "helene.h"
29 #include "lnbh25.h"
30
31 static int spi_enable;
32 module_param(spi_enable, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
33
34 MODULE_DESCRIPTION("Driver for NetUP Dual Universal DVB CI PCIe card");
35 MODULE_AUTHOR("info@netup.ru");
36 MODULE_VERSION(NETUP_UNIDVB_VERSION);
37 MODULE_LICENSE("GPL");
38
39 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
40
41 /* Avalon-MM PCI-E registers */
42 #define AVL_PCIE_IENR 0x50
43 #define AVL_PCIE_ISR 0x40
44 #define AVL_IRQ_ENABLE 0x80
45 #define AVL_IRQ_ASSERTED 0x80
46 /* GPIO registers */
47 #define GPIO_REG_IO 0x4880
48 #define GPIO_REG_IO_TOGGLE 0x4882
49 #define GPIO_REG_IO_SET 0x4884
50 #define GPIO_REG_IO_CLEAR 0x4886
51 /* GPIO bits */
52 #define GPIO_FEA_RESET (1 << 0)
53 #define GPIO_FEB_RESET (1 << 1)
54 #define GPIO_RFA_CTL (1 << 2)
55 #define GPIO_RFB_CTL (1 << 3)
56 #define GPIO_FEA_TU_RESET (1 << 4)
57 #define GPIO_FEB_TU_RESET (1 << 5)
58 /* DMA base address */
59 #define NETUP_DMA0_ADDR 0x4900
60 #define NETUP_DMA1_ADDR 0x4940
61 /* 8 DMA blocks * 128 packets * 188 bytes*/
62 #define NETUP_DMA_BLOCKS_COUNT 8
63 #define NETUP_DMA_PACKETS_COUNT 128
64 /* DMA status bits */
65 #define BIT_DMA_RUN 1
66 #define BIT_DMA_ERROR 2
67 #define BIT_DMA_IRQ 0x200
68
69 /**
70 * struct netup_dma_regs - the map of DMA module registers
71 * @ctrlstat_set: Control register, write to set control bits
72 * @ctrlstat_clear: Control register, write to clear control bits
73 * @start_addr_lo: DMA ring buffer start address, lower part
74 * @start_addr_hi: DMA ring buffer start address, higher part
75 * @size: DMA ring buffer size register
76 * * Bits [0-7]: DMA packet size, 188 bytes
77 * * Bits [16-23]: packets count in block, 128 packets
78 * * Bits [24-31]: blocks count, 8 blocks
79 * @timeout: DMA timeout in units of 8ns
80 * For example, value of 375000000 equals to 3 sec
81 * @curr_addr_lo: Current ring buffer head address, lower part
82 * @curr_addr_hi: Current ring buffer head address, higher part
83 * @stat_pkt_received: Statistic register, not tested
84 * @stat_pkt_accepted: Statistic register, not tested
85 * @stat_pkt_overruns: Statistic register, not tested
86 * @stat_pkt_underruns: Statistic register, not tested
87 * @stat_fifo_overruns: Statistic register, not tested
88 */
89 struct netup_dma_regs {
90 __le32 ctrlstat_set;
91 __le32 ctrlstat_clear;
92 __le32 start_addr_lo;
93 __le32 start_addr_hi;
94 __le32 size;
95 __le32 timeout;
96 __le32 curr_addr_lo;
97 __le32 curr_addr_hi;
98 __le32 stat_pkt_received;
99 __le32 stat_pkt_accepted;
100 __le32 stat_pkt_overruns;
101 __le32 stat_pkt_underruns;
102 __le32 stat_fifo_overruns;
103 } __packed __aligned(1);
104
105 struct netup_unidvb_buffer {
106 struct vb2_v4l2_buffer vb;
107 struct list_head list;
108 u32 size;
109 };
110
111 static int netup_unidvb_tuner_ctrl(void *priv, int is_dvb_tc);
112 static void netup_unidvb_queue_cleanup(struct netup_dma *dma);
113
114 static struct cxd2841er_config demod_config = {
115 .i2c_addr = 0xc8,
116 .xtal = SONY_XTAL_24000,
117 .flags = CXD2841ER_USE_GATECTRL | CXD2841ER_ASCOT
118 };
119
120 static struct horus3a_config horus3a_conf = {
121 .i2c_address = 0xc0,
122 .xtal_freq_mhz = 16,
123 .set_tuner_callback = netup_unidvb_tuner_ctrl
124 };
125
126 static struct ascot2e_config ascot2e_conf = {
127 .i2c_address = 0xc2,
128 .set_tuner_callback = netup_unidvb_tuner_ctrl
129 };
130
131 static struct helene_config helene_conf = {
132 .i2c_address = 0xc0,
133 .xtal = SONY_HELENE_XTAL_24000,
134 .set_tuner_callback = netup_unidvb_tuner_ctrl
135 };
136
137 static struct lnbh25_config lnbh25_conf = {
138 .i2c_address = 0x10,
139 .data2_config = LNBH25_TEN | LNBH25_EXTM
140 };
141
netup_unidvb_tuner_ctrl(void * priv,int is_dvb_tc)142 static int netup_unidvb_tuner_ctrl(void *priv, int is_dvb_tc)
143 {
144 u8 reg, mask;
145 struct netup_dma *dma = priv;
146 struct netup_unidvb_dev *ndev;
147
148 if (!priv)
149 return -EINVAL;
150 ndev = dma->ndev;
151 dev_dbg(&ndev->pci_dev->dev, "%s(): num %d is_dvb_tc %d\n",
152 __func__, dma->num, is_dvb_tc);
153 reg = readb(ndev->bmmio0 + GPIO_REG_IO);
154 mask = (dma->num == 0) ? GPIO_RFA_CTL : GPIO_RFB_CTL;
155
156 /* inverted tuner control in hw rev. 1.4 */
157 if (ndev->rev == NETUP_HW_REV_1_4)
158 is_dvb_tc = !is_dvb_tc;
159
160 if (!is_dvb_tc)
161 reg |= mask;
162 else
163 reg &= ~mask;
164 writeb(reg, ndev->bmmio0 + GPIO_REG_IO);
165 return 0;
166 }
167
netup_unidvb_dev_enable(struct netup_unidvb_dev * ndev)168 static void netup_unidvb_dev_enable(struct netup_unidvb_dev *ndev)
169 {
170 u16 gpio_reg;
171
172 /* enable PCI-E interrupts */
173 writel(AVL_IRQ_ENABLE, ndev->bmmio0 + AVL_PCIE_IENR);
174 /* unreset frontends bits[0:1] */
175 writeb(0x00, ndev->bmmio0 + GPIO_REG_IO);
176 msleep(100);
177 gpio_reg =
178 GPIO_FEA_RESET | GPIO_FEB_RESET |
179 GPIO_FEA_TU_RESET | GPIO_FEB_TU_RESET |
180 GPIO_RFA_CTL | GPIO_RFB_CTL;
181 writeb(gpio_reg, ndev->bmmio0 + GPIO_REG_IO);
182 dev_dbg(&ndev->pci_dev->dev,
183 "%s(): AVL_PCIE_IENR 0x%x GPIO_REG_IO 0x%x\n",
184 __func__, readl(ndev->bmmio0 + AVL_PCIE_IENR),
185 (int)readb(ndev->bmmio0 + GPIO_REG_IO));
186
187 }
188
netup_unidvb_dma_enable(struct netup_dma * dma,int enable)189 static void netup_unidvb_dma_enable(struct netup_dma *dma, int enable)
190 {
191 u32 irq_mask = (dma->num == 0 ?
192 NETUP_UNIDVB_IRQ_DMA1 : NETUP_UNIDVB_IRQ_DMA2);
193
194 dev_dbg(&dma->ndev->pci_dev->dev,
195 "%s(): DMA%d enable %d\n", __func__, dma->num, enable);
196 if (enable) {
197 writel(BIT_DMA_RUN, &dma->regs->ctrlstat_set);
198 writew(irq_mask, dma->ndev->bmmio0 + REG_IMASK_SET);
199 } else {
200 writel(BIT_DMA_RUN, &dma->regs->ctrlstat_clear);
201 writew(irq_mask, dma->ndev->bmmio0 + REG_IMASK_CLEAR);
202 }
203 }
204
netup_dma_interrupt(struct netup_dma * dma)205 static irqreturn_t netup_dma_interrupt(struct netup_dma *dma)
206 {
207 u64 addr_curr;
208 u32 size;
209 unsigned long flags;
210 struct device *dev = &dma->ndev->pci_dev->dev;
211
212 spin_lock_irqsave(&dma->lock, flags);
213 addr_curr = ((u64)readl(&dma->regs->curr_addr_hi) << 32) |
214 (u64)readl(&dma->regs->curr_addr_lo) | dma->high_addr;
215 /* clear IRQ */
216 writel(BIT_DMA_IRQ, &dma->regs->ctrlstat_clear);
217 /* sanity check */
218 if (addr_curr < dma->addr_phys ||
219 addr_curr > dma->addr_phys + dma->ring_buffer_size) {
220 if (addr_curr != 0) {
221 dev_err(dev,
222 "%s(): addr 0x%llx not from 0x%llx:0x%llx\n",
223 __func__, addr_curr, (u64)dma->addr_phys,
224 (u64)(dma->addr_phys + dma->ring_buffer_size));
225 }
226 goto irq_handled;
227 }
228 size = (addr_curr >= dma->addr_last) ?
229 (u32)(addr_curr - dma->addr_last) :
230 (u32)(dma->ring_buffer_size - (dma->addr_last - addr_curr));
231 if (dma->data_size != 0) {
232 printk_ratelimited("%s(): lost interrupt, data size %d\n",
233 __func__, dma->data_size);
234 dma->data_size += size;
235 }
236 if (dma->data_size == 0 || dma->data_size > dma->ring_buffer_size) {
237 dma->data_size = size;
238 dma->data_offset = (u32)(dma->addr_last - dma->addr_phys);
239 }
240 dma->addr_last = addr_curr;
241 queue_work(dma->ndev->wq, &dma->work);
242 irq_handled:
243 spin_unlock_irqrestore(&dma->lock, flags);
244 return IRQ_HANDLED;
245 }
246
netup_unidvb_isr(int irq,void * dev_id)247 static irqreturn_t netup_unidvb_isr(int irq, void *dev_id)
248 {
249 struct pci_dev *pci_dev = (struct pci_dev *)dev_id;
250 struct netup_unidvb_dev *ndev = pci_get_drvdata(pci_dev);
251 u32 reg40, reg_isr;
252 irqreturn_t iret = IRQ_NONE;
253
254 /* disable interrupts */
255 writel(0, ndev->bmmio0 + AVL_PCIE_IENR);
256 /* check IRQ source */
257 reg40 = readl(ndev->bmmio0 + AVL_PCIE_ISR);
258 if ((reg40 & AVL_IRQ_ASSERTED) != 0) {
259 /* IRQ is being signaled */
260 reg_isr = readw(ndev->bmmio0 + REG_ISR);
261 if (reg_isr & NETUP_UNIDVB_IRQ_I2C0) {
262 iret = netup_i2c_interrupt(&ndev->i2c[0]);
263 } else if (reg_isr & NETUP_UNIDVB_IRQ_I2C1) {
264 iret = netup_i2c_interrupt(&ndev->i2c[1]);
265 } else if (reg_isr & NETUP_UNIDVB_IRQ_SPI) {
266 iret = netup_spi_interrupt(ndev->spi);
267 } else if (reg_isr & NETUP_UNIDVB_IRQ_DMA1) {
268 iret = netup_dma_interrupt(&ndev->dma[0]);
269 } else if (reg_isr & NETUP_UNIDVB_IRQ_DMA2) {
270 iret = netup_dma_interrupt(&ndev->dma[1]);
271 } else if (reg_isr & NETUP_UNIDVB_IRQ_CI) {
272 iret = netup_ci_interrupt(ndev);
273 } else {
274 dev_err(&pci_dev->dev,
275 "%s(): unknown interrupt 0x%x\n",
276 __func__, reg_isr);
277 }
278 }
279 /* re-enable interrupts */
280 writel(AVL_IRQ_ENABLE, ndev->bmmio0 + AVL_PCIE_IENR);
281 return iret;
282 }
283
netup_unidvb_queue_setup(struct vb2_queue * vq,unsigned int * nbuffers,unsigned int * nplanes,unsigned int sizes[],struct device * alloc_devs[])284 static int netup_unidvb_queue_setup(struct vb2_queue *vq,
285 unsigned int *nbuffers,
286 unsigned int *nplanes,
287 unsigned int sizes[],
288 struct device *alloc_devs[])
289 {
290 struct netup_dma *dma = vb2_get_drv_priv(vq);
291
292 dev_dbg(&dma->ndev->pci_dev->dev, "%s()\n", __func__);
293
294 *nplanes = 1;
295 if (vq->num_buffers + *nbuffers < VIDEO_MAX_FRAME)
296 *nbuffers = VIDEO_MAX_FRAME - vq->num_buffers;
297 sizes[0] = PAGE_ALIGN(NETUP_DMA_PACKETS_COUNT * 188);
298 dev_dbg(&dma->ndev->pci_dev->dev, "%s() nbuffers=%d sizes[0]=%d\n",
299 __func__, *nbuffers, sizes[0]);
300 return 0;
301 }
302
netup_unidvb_buf_prepare(struct vb2_buffer * vb)303 static int netup_unidvb_buf_prepare(struct vb2_buffer *vb)
304 {
305 struct netup_dma *dma = vb2_get_drv_priv(vb->vb2_queue);
306 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
307 struct netup_unidvb_buffer *buf = container_of(vbuf,
308 struct netup_unidvb_buffer, vb);
309
310 dev_dbg(&dma->ndev->pci_dev->dev, "%s(): buf 0x%p\n", __func__, buf);
311 buf->size = 0;
312 return 0;
313 }
314
netup_unidvb_buf_queue(struct vb2_buffer * vb)315 static void netup_unidvb_buf_queue(struct vb2_buffer *vb)
316 {
317 unsigned long flags;
318 struct netup_dma *dma = vb2_get_drv_priv(vb->vb2_queue);
319 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
320 struct netup_unidvb_buffer *buf = container_of(vbuf,
321 struct netup_unidvb_buffer, vb);
322
323 dev_dbg(&dma->ndev->pci_dev->dev, "%s(): %p\n", __func__, buf);
324 spin_lock_irqsave(&dma->lock, flags);
325 list_add_tail(&buf->list, &dma->free_buffers);
326 spin_unlock_irqrestore(&dma->lock, flags);
327 mod_timer(&dma->timeout, jiffies + msecs_to_jiffies(1000));
328 }
329
netup_unidvb_start_streaming(struct vb2_queue * q,unsigned int count)330 static int netup_unidvb_start_streaming(struct vb2_queue *q, unsigned int count)
331 {
332 struct netup_dma *dma = vb2_get_drv_priv(q);
333
334 dev_dbg(&dma->ndev->pci_dev->dev, "%s()\n", __func__);
335 netup_unidvb_dma_enable(dma, 1);
336 return 0;
337 }
338
netup_unidvb_stop_streaming(struct vb2_queue * q)339 static void netup_unidvb_stop_streaming(struct vb2_queue *q)
340 {
341 struct netup_dma *dma = vb2_get_drv_priv(q);
342
343 dev_dbg(&dma->ndev->pci_dev->dev, "%s()\n", __func__);
344 netup_unidvb_dma_enable(dma, 0);
345 netup_unidvb_queue_cleanup(dma);
346 }
347
348 static const struct vb2_ops dvb_qops = {
349 .queue_setup = netup_unidvb_queue_setup,
350 .buf_prepare = netup_unidvb_buf_prepare,
351 .buf_queue = netup_unidvb_buf_queue,
352 .start_streaming = netup_unidvb_start_streaming,
353 .stop_streaming = netup_unidvb_stop_streaming,
354 };
355
netup_unidvb_queue_init(struct netup_dma * dma,struct vb2_queue * vb_queue)356 static int netup_unidvb_queue_init(struct netup_dma *dma,
357 struct vb2_queue *vb_queue)
358 {
359 int res;
360
361 /* Init videobuf2 queue structure */
362 vb_queue->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
363 vb_queue->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ;
364 vb_queue->drv_priv = dma;
365 vb_queue->buf_struct_size = sizeof(struct netup_unidvb_buffer);
366 vb_queue->ops = &dvb_qops;
367 vb_queue->mem_ops = &vb2_vmalloc_memops;
368 vb_queue->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
369 res = vb2_queue_init(vb_queue);
370 if (res != 0) {
371 dev_err(&dma->ndev->pci_dev->dev,
372 "%s(): vb2_queue_init failed (%d)\n", __func__, res);
373 }
374 return res;
375 }
376
netup_unidvb_dvb_init(struct netup_unidvb_dev * ndev,int num)377 static int netup_unidvb_dvb_init(struct netup_unidvb_dev *ndev,
378 int num)
379 {
380 int fe_count = 2;
381 int i = 0;
382 struct vb2_dvb_frontend *fes[2];
383 u8 fe_name[32];
384
385 if (ndev->rev == NETUP_HW_REV_1_3)
386 demod_config.xtal = SONY_XTAL_20500;
387 else
388 demod_config.xtal = SONY_XTAL_24000;
389
390 if (num < 0 || num > 1) {
391 dev_dbg(&ndev->pci_dev->dev,
392 "%s(): unable to init DVB bus %d\n", __func__, num);
393 return -ENODEV;
394 }
395 mutex_init(&ndev->frontends[num].lock);
396 INIT_LIST_HEAD(&ndev->frontends[num].felist);
397
398 for (i = 0; i < fe_count; i++) {
399 if (vb2_dvb_alloc_frontend(&ndev->frontends[num], i+1)
400 == NULL) {
401 dev_err(&ndev->pci_dev->dev,
402 "%s(): unable to allocate vb2_dvb_frontend\n",
403 __func__);
404 return -ENOMEM;
405 }
406 }
407
408 for (i = 0; i < fe_count; i++) {
409 fes[i] = vb2_dvb_get_frontend(&ndev->frontends[num], i+1);
410 if (fes[i] == NULL) {
411 dev_err(&ndev->pci_dev->dev,
412 "%s(): frontends has not been allocated\n",
413 __func__);
414 return -EINVAL;
415 }
416 }
417
418 for (i = 0; i < fe_count; i++) {
419 netup_unidvb_queue_init(&ndev->dma[num], &fes[i]->dvb.dvbq);
420 snprintf(fe_name, sizeof(fe_name), "netup_fe%d", i);
421 fes[i]->dvb.name = fe_name;
422 }
423
424 fes[0]->dvb.frontend = dvb_attach(cxd2841er_attach_s,
425 &demod_config, &ndev->i2c[num].adap);
426 if (fes[0]->dvb.frontend == NULL) {
427 dev_dbg(&ndev->pci_dev->dev,
428 "%s(): unable to attach DVB-S/S2 frontend\n",
429 __func__);
430 goto frontend_detach;
431 }
432
433 if (ndev->rev == NETUP_HW_REV_1_3) {
434 horus3a_conf.set_tuner_priv = &ndev->dma[num];
435 if (!dvb_attach(horus3a_attach, fes[0]->dvb.frontend,
436 &horus3a_conf, &ndev->i2c[num].adap)) {
437 dev_dbg(&ndev->pci_dev->dev,
438 "%s(): unable to attach HORUS3A DVB-S/S2 tuner frontend\n",
439 __func__);
440 goto frontend_detach;
441 }
442 } else {
443 helene_conf.set_tuner_priv = &ndev->dma[num];
444 if (!dvb_attach(helene_attach_s, fes[0]->dvb.frontend,
445 &helene_conf, &ndev->i2c[num].adap)) {
446 dev_err(&ndev->pci_dev->dev,
447 "%s(): unable to attach HELENE DVB-S/S2 tuner frontend\n",
448 __func__);
449 goto frontend_detach;
450 }
451 }
452
453 if (!dvb_attach(lnbh25_attach, fes[0]->dvb.frontend,
454 &lnbh25_conf, &ndev->i2c[num].adap)) {
455 dev_dbg(&ndev->pci_dev->dev,
456 "%s(): unable to attach SEC frontend\n", __func__);
457 goto frontend_detach;
458 }
459
460 /* DVB-T/T2 frontend */
461 fes[1]->dvb.frontend = dvb_attach(cxd2841er_attach_t_c,
462 &demod_config, &ndev->i2c[num].adap);
463 if (fes[1]->dvb.frontend == NULL) {
464 dev_dbg(&ndev->pci_dev->dev,
465 "%s(): unable to attach Ter frontend\n", __func__);
466 goto frontend_detach;
467 }
468 fes[1]->dvb.frontend->id = 1;
469 if (ndev->rev == NETUP_HW_REV_1_3) {
470 ascot2e_conf.set_tuner_priv = &ndev->dma[num];
471 if (!dvb_attach(ascot2e_attach, fes[1]->dvb.frontend,
472 &ascot2e_conf, &ndev->i2c[num].adap)) {
473 dev_dbg(&ndev->pci_dev->dev,
474 "%s(): unable to attach Ter tuner frontend\n",
475 __func__);
476 goto frontend_detach;
477 }
478 } else {
479 helene_conf.set_tuner_priv = &ndev->dma[num];
480 if (!dvb_attach(helene_attach, fes[1]->dvb.frontend,
481 &helene_conf, &ndev->i2c[num].adap)) {
482 dev_err(&ndev->pci_dev->dev,
483 "%s(): unable to attach HELENE Ter tuner frontend\n",
484 __func__);
485 goto frontend_detach;
486 }
487 }
488
489 if (vb2_dvb_register_bus(&ndev->frontends[num],
490 THIS_MODULE, NULL,
491 &ndev->pci_dev->dev, NULL, adapter_nr, 1)) {
492 dev_dbg(&ndev->pci_dev->dev,
493 "%s(): unable to register DVB bus %d\n",
494 __func__, num);
495 goto frontend_detach;
496 }
497 dev_info(&ndev->pci_dev->dev, "DVB init done, num=%d\n", num);
498 return 0;
499 frontend_detach:
500 vb2_dvb_dealloc_frontends(&ndev->frontends[num]);
501 return -EINVAL;
502 }
503
netup_unidvb_dvb_fini(struct netup_unidvb_dev * ndev,int num)504 static void netup_unidvb_dvb_fini(struct netup_unidvb_dev *ndev, int num)
505 {
506 if (num < 0 || num > 1) {
507 dev_err(&ndev->pci_dev->dev,
508 "%s(): unable to unregister DVB bus %d\n",
509 __func__, num);
510 return;
511 }
512 vb2_dvb_unregister_bus(&ndev->frontends[num]);
513 dev_info(&ndev->pci_dev->dev,
514 "%s(): DVB bus %d unregistered\n", __func__, num);
515 }
516
netup_unidvb_dvb_setup(struct netup_unidvb_dev * ndev)517 static int netup_unidvb_dvb_setup(struct netup_unidvb_dev *ndev)
518 {
519 int res;
520
521 res = netup_unidvb_dvb_init(ndev, 0);
522 if (res)
523 return res;
524 res = netup_unidvb_dvb_init(ndev, 1);
525 if (res) {
526 netup_unidvb_dvb_fini(ndev, 0);
527 return res;
528 }
529 return 0;
530 }
531
netup_unidvb_ring_copy(struct netup_dma * dma,struct netup_unidvb_buffer * buf)532 static int netup_unidvb_ring_copy(struct netup_dma *dma,
533 struct netup_unidvb_buffer *buf)
534 {
535 u32 copy_bytes, ring_bytes;
536 u32 buff_bytes = NETUP_DMA_PACKETS_COUNT * 188 - buf->size;
537 u8 *p = vb2_plane_vaddr(&buf->vb.vb2_buf, 0);
538 struct netup_unidvb_dev *ndev = dma->ndev;
539
540 if (p == NULL) {
541 dev_err(&ndev->pci_dev->dev,
542 "%s(): buffer is NULL\n", __func__);
543 return -EINVAL;
544 }
545 p += buf->size;
546 if (dma->data_offset + dma->data_size > dma->ring_buffer_size) {
547 ring_bytes = dma->ring_buffer_size - dma->data_offset;
548 copy_bytes = (ring_bytes > buff_bytes) ?
549 buff_bytes : ring_bytes;
550 memcpy_fromio(p, (u8 __iomem *)(dma->addr_virt + dma->data_offset), copy_bytes);
551 p += copy_bytes;
552 buf->size += copy_bytes;
553 buff_bytes -= copy_bytes;
554 dma->data_size -= copy_bytes;
555 dma->data_offset += copy_bytes;
556 if (dma->data_offset == dma->ring_buffer_size)
557 dma->data_offset = 0;
558 }
559 if (buff_bytes > 0) {
560 ring_bytes = dma->data_size;
561 copy_bytes = (ring_bytes > buff_bytes) ?
562 buff_bytes : ring_bytes;
563 memcpy_fromio(p, (u8 __iomem *)(dma->addr_virt + dma->data_offset), copy_bytes);
564 buf->size += copy_bytes;
565 dma->data_size -= copy_bytes;
566 dma->data_offset += copy_bytes;
567 if (dma->data_offset == dma->ring_buffer_size)
568 dma->data_offset = 0;
569 }
570 return 0;
571 }
572
netup_unidvb_dma_worker(struct work_struct * work)573 static void netup_unidvb_dma_worker(struct work_struct *work)
574 {
575 struct netup_dma *dma = container_of(work, struct netup_dma, work);
576 struct netup_unidvb_dev *ndev = dma->ndev;
577 struct netup_unidvb_buffer *buf;
578 unsigned long flags;
579
580 spin_lock_irqsave(&dma->lock, flags);
581 if (dma->data_size == 0) {
582 dev_dbg(&ndev->pci_dev->dev,
583 "%s(): data_size == 0\n", __func__);
584 goto work_done;
585 }
586 while (dma->data_size > 0) {
587 if (list_empty(&dma->free_buffers)) {
588 dev_dbg(&ndev->pci_dev->dev,
589 "%s(): no free buffers\n", __func__);
590 goto work_done;
591 }
592 buf = list_first_entry(&dma->free_buffers,
593 struct netup_unidvb_buffer, list);
594 if (buf->size >= NETUP_DMA_PACKETS_COUNT * 188) {
595 dev_dbg(&ndev->pci_dev->dev,
596 "%s(): buffer overflow, size %d\n",
597 __func__, buf->size);
598 goto work_done;
599 }
600 if (netup_unidvb_ring_copy(dma, buf))
601 goto work_done;
602 if (buf->size == NETUP_DMA_PACKETS_COUNT * 188) {
603 list_del(&buf->list);
604 dev_dbg(&ndev->pci_dev->dev,
605 "%s(): buffer %p done, size %d\n",
606 __func__, buf, buf->size);
607 buf->vb.vb2_buf.timestamp = ktime_get_ns();
608 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, buf->size);
609 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
610 }
611 }
612 work_done:
613 dma->data_size = 0;
614 spin_unlock_irqrestore(&dma->lock, flags);
615 }
616
netup_unidvb_queue_cleanup(struct netup_dma * dma)617 static void netup_unidvb_queue_cleanup(struct netup_dma *dma)
618 {
619 struct netup_unidvb_buffer *buf;
620 unsigned long flags;
621
622 spin_lock_irqsave(&dma->lock, flags);
623 while (!list_empty(&dma->free_buffers)) {
624 buf = list_first_entry(&dma->free_buffers,
625 struct netup_unidvb_buffer, list);
626 list_del(&buf->list);
627 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
628 }
629 spin_unlock_irqrestore(&dma->lock, flags);
630 }
631
netup_unidvb_dma_timeout(struct timer_list * t)632 static void netup_unidvb_dma_timeout(struct timer_list *t)
633 {
634 struct netup_dma *dma = from_timer(dma, t, timeout);
635 struct netup_unidvb_dev *ndev = dma->ndev;
636
637 dev_dbg(&ndev->pci_dev->dev, "%s()\n", __func__);
638 netup_unidvb_queue_cleanup(dma);
639 }
640
netup_unidvb_dma_init(struct netup_unidvb_dev * ndev,int num)641 static int netup_unidvb_dma_init(struct netup_unidvb_dev *ndev, int num)
642 {
643 struct netup_dma *dma;
644 struct device *dev = &ndev->pci_dev->dev;
645
646 if (num < 0 || num > 1) {
647 dev_err(dev, "%s(): unable to register DMA%d\n",
648 __func__, num);
649 return -ENODEV;
650 }
651 dma = &ndev->dma[num];
652 dev_info(dev, "%s(): starting DMA%d\n", __func__, num);
653 dma->num = num;
654 dma->ndev = ndev;
655 spin_lock_init(&dma->lock);
656 INIT_WORK(&dma->work, netup_unidvb_dma_worker);
657 INIT_LIST_HEAD(&dma->free_buffers);
658 timer_setup(&dma->timeout, netup_unidvb_dma_timeout, 0);
659 dma->ring_buffer_size = ndev->dma_size / 2;
660 dma->addr_virt = ndev->dma_virt + dma->ring_buffer_size * num;
661 dma->addr_phys = (dma_addr_t)((u64)ndev->dma_phys +
662 dma->ring_buffer_size * num);
663 dev_info(dev, "%s(): DMA%d buffer virt/phys 0x%p/0x%llx size %d\n",
664 __func__, num, dma->addr_virt,
665 (unsigned long long)dma->addr_phys,
666 dma->ring_buffer_size);
667 memset_io((u8 __iomem *)dma->addr_virt, 0, dma->ring_buffer_size);
668 dma->addr_last = dma->addr_phys;
669 dma->high_addr = (u32)(dma->addr_phys & 0xC0000000);
670 dma->regs = (struct netup_dma_regs __iomem *)(num == 0 ?
671 ndev->bmmio0 + NETUP_DMA0_ADDR :
672 ndev->bmmio0 + NETUP_DMA1_ADDR);
673 writel((NETUP_DMA_BLOCKS_COUNT << 24) |
674 (NETUP_DMA_PACKETS_COUNT << 8) | 188, &dma->regs->size);
675 writel((u32)(dma->addr_phys & 0x3FFFFFFF), &dma->regs->start_addr_lo);
676 writel(0, &dma->regs->start_addr_hi);
677 writel(dma->high_addr, ndev->bmmio0 + 0x1000);
678 writel(375000000, &dma->regs->timeout);
679 msleep(1000);
680 writel(BIT_DMA_IRQ, &dma->regs->ctrlstat_clear);
681 return 0;
682 }
683
netup_unidvb_dma_fini(struct netup_unidvb_dev * ndev,int num)684 static void netup_unidvb_dma_fini(struct netup_unidvb_dev *ndev, int num)
685 {
686 struct netup_dma *dma;
687
688 if (num < 0 || num > 1)
689 return;
690 dev_dbg(&ndev->pci_dev->dev, "%s(): num %d\n", __func__, num);
691 dma = &ndev->dma[num];
692 netup_unidvb_dma_enable(dma, 0);
693 msleep(50);
694 cancel_work_sync(&dma->work);
695 del_timer(&dma->timeout);
696 }
697
netup_unidvb_dma_setup(struct netup_unidvb_dev * ndev)698 static int netup_unidvb_dma_setup(struct netup_unidvb_dev *ndev)
699 {
700 int res;
701
702 res = netup_unidvb_dma_init(ndev, 0);
703 if (res)
704 return res;
705 res = netup_unidvb_dma_init(ndev, 1);
706 if (res) {
707 netup_unidvb_dma_fini(ndev, 0);
708 return res;
709 }
710 netup_unidvb_dma_enable(&ndev->dma[0], 0);
711 netup_unidvb_dma_enable(&ndev->dma[1], 0);
712 return 0;
713 }
714
netup_unidvb_ci_setup(struct netup_unidvb_dev * ndev,struct pci_dev * pci_dev)715 static int netup_unidvb_ci_setup(struct netup_unidvb_dev *ndev,
716 struct pci_dev *pci_dev)
717 {
718 int res;
719
720 writew(NETUP_UNIDVB_IRQ_CI, ndev->bmmio0 + REG_IMASK_SET);
721 res = netup_unidvb_ci_register(ndev, 0, pci_dev);
722 if (res)
723 return res;
724 res = netup_unidvb_ci_register(ndev, 1, pci_dev);
725 if (res)
726 netup_unidvb_ci_unregister(ndev, 0);
727 return res;
728 }
729
netup_unidvb_request_mmio(struct pci_dev * pci_dev)730 static int netup_unidvb_request_mmio(struct pci_dev *pci_dev)
731 {
732 if (!request_mem_region(pci_resource_start(pci_dev, 0),
733 pci_resource_len(pci_dev, 0), NETUP_UNIDVB_NAME)) {
734 dev_err(&pci_dev->dev,
735 "%s(): unable to request MMIO bar 0 at 0x%llx\n",
736 __func__,
737 (unsigned long long)pci_resource_start(pci_dev, 0));
738 return -EBUSY;
739 }
740 if (!request_mem_region(pci_resource_start(pci_dev, 1),
741 pci_resource_len(pci_dev, 1), NETUP_UNIDVB_NAME)) {
742 dev_err(&pci_dev->dev,
743 "%s(): unable to request MMIO bar 1 at 0x%llx\n",
744 __func__,
745 (unsigned long long)pci_resource_start(pci_dev, 1));
746 release_mem_region(pci_resource_start(pci_dev, 0),
747 pci_resource_len(pci_dev, 0));
748 return -EBUSY;
749 }
750 return 0;
751 }
752
netup_unidvb_request_modules(struct device * dev)753 static int netup_unidvb_request_modules(struct device *dev)
754 {
755 static const char * const modules[] = {
756 "lnbh25", "ascot2e", "horus3a", "cxd2841er", "helene", NULL
757 };
758 const char * const *curr_mod = modules;
759 int err;
760
761 while (*curr_mod != NULL) {
762 err = request_module(*curr_mod);
763 if (err) {
764 dev_warn(dev, "request_module(%s) failed: %d\n",
765 *curr_mod, err);
766 }
767 ++curr_mod;
768 }
769 return 0;
770 }
771
netup_unidvb_initdev(struct pci_dev * pci_dev,const struct pci_device_id * pci_id)772 static int netup_unidvb_initdev(struct pci_dev *pci_dev,
773 const struct pci_device_id *pci_id)
774 {
775 u8 board_revision;
776 u16 board_vendor;
777 struct netup_unidvb_dev *ndev;
778 int old_firmware = 0;
779
780 netup_unidvb_request_modules(&pci_dev->dev);
781
782 /* Check card revision */
783 if (pci_dev->revision != NETUP_PCI_DEV_REVISION) {
784 dev_err(&pci_dev->dev,
785 "netup_unidvb: expected card revision %d, got %d\n",
786 NETUP_PCI_DEV_REVISION, pci_dev->revision);
787 dev_err(&pci_dev->dev,
788 "Please upgrade firmware!\n");
789 dev_err(&pci_dev->dev,
790 "Instructions on http://www.netup.tv\n");
791 old_firmware = 1;
792 spi_enable = 1;
793 }
794
795 /* allocate device context */
796 ndev = kzalloc(sizeof(*ndev), GFP_KERNEL);
797 if (!ndev)
798 goto dev_alloc_err;
799
800 /* detect hardware revision */
801 if (pci_dev->device == NETUP_HW_REV_1_3)
802 ndev->rev = NETUP_HW_REV_1_3;
803 else
804 ndev->rev = NETUP_HW_REV_1_4;
805
806 dev_info(&pci_dev->dev,
807 "%s(): board (0x%x) hardware revision 0x%x\n",
808 __func__, pci_dev->device, ndev->rev);
809
810 ndev->old_fw = old_firmware;
811 ndev->wq = create_singlethread_workqueue(NETUP_UNIDVB_NAME);
812 if (!ndev->wq) {
813 dev_err(&pci_dev->dev,
814 "%s(): unable to create workqueue\n", __func__);
815 goto wq_create_err;
816 }
817 ndev->pci_dev = pci_dev;
818 ndev->pci_bus = pci_dev->bus->number;
819 ndev->pci_slot = PCI_SLOT(pci_dev->devfn);
820 ndev->pci_func = PCI_FUNC(pci_dev->devfn);
821 ndev->board_num = ndev->pci_bus*10 + ndev->pci_slot;
822 pci_set_drvdata(pci_dev, ndev);
823 /* PCI init */
824 dev_info(&pci_dev->dev, "%s(): PCI device (%d). Bus:0x%x Slot:0x%x\n",
825 __func__, ndev->board_num, ndev->pci_bus, ndev->pci_slot);
826
827 if (pci_enable_device(pci_dev)) {
828 dev_err(&pci_dev->dev, "%s(): pci_enable_device failed\n",
829 __func__);
830 goto pci_enable_err;
831 }
832 /* read PCI info */
833 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &board_revision);
834 pci_read_config_word(pci_dev, PCI_VENDOR_ID, &board_vendor);
835 if (board_vendor != NETUP_VENDOR_ID) {
836 dev_err(&pci_dev->dev, "%s(): unknown board vendor 0x%x",
837 __func__, board_vendor);
838 goto pci_detect_err;
839 }
840 dev_info(&pci_dev->dev,
841 "%s(): board vendor 0x%x, revision 0x%x\n",
842 __func__, board_vendor, board_revision);
843 pci_set_master(pci_dev);
844 if (pci_set_dma_mask(pci_dev, 0xffffffff) < 0) {
845 dev_err(&pci_dev->dev,
846 "%s(): 32bit PCI DMA is not supported\n", __func__);
847 goto pci_detect_err;
848 }
849 dev_info(&pci_dev->dev, "%s(): using 32bit PCI DMA\n", __func__);
850 /* Clear "no snoop" and "relaxed ordering" bits, use default MRRS. */
851 pcie_capability_clear_and_set_word(pci_dev, PCI_EXP_DEVCTL,
852 PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_RELAX_EN |
853 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
854 /* Adjust PCIe completion timeout. */
855 pcie_capability_clear_and_set_word(pci_dev,
856 PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0x2);
857
858 if (netup_unidvb_request_mmio(pci_dev)) {
859 dev_err(&pci_dev->dev,
860 "%s(): unable to request MMIO regions\n", __func__);
861 goto pci_detect_err;
862 }
863 ndev->lmmio0 = ioremap(pci_resource_start(pci_dev, 0),
864 pci_resource_len(pci_dev, 0));
865 if (!ndev->lmmio0) {
866 dev_err(&pci_dev->dev,
867 "%s(): unable to remap MMIO bar 0\n", __func__);
868 goto pci_bar0_error;
869 }
870 ndev->lmmio1 = ioremap(pci_resource_start(pci_dev, 1),
871 pci_resource_len(pci_dev, 1));
872 if (!ndev->lmmio1) {
873 dev_err(&pci_dev->dev,
874 "%s(): unable to remap MMIO bar 1\n", __func__);
875 goto pci_bar1_error;
876 }
877 ndev->bmmio0 = (u8 __iomem *)ndev->lmmio0;
878 ndev->bmmio1 = (u8 __iomem *)ndev->lmmio1;
879 dev_info(&pci_dev->dev,
880 "%s(): PCI MMIO at 0x%p (%d); 0x%p (%d); IRQ %d",
881 __func__,
882 ndev->lmmio0, (u32)pci_resource_len(pci_dev, 0),
883 ndev->lmmio1, (u32)pci_resource_len(pci_dev, 1),
884 pci_dev->irq);
885 if (request_irq(pci_dev->irq, netup_unidvb_isr, IRQF_SHARED,
886 "netup_unidvb", pci_dev) < 0) {
887 dev_err(&pci_dev->dev,
888 "%s(): can't get IRQ %d\n", __func__, pci_dev->irq);
889 goto irq_request_err;
890 }
891 ndev->dma_size = 2 * 188 *
892 NETUP_DMA_BLOCKS_COUNT * NETUP_DMA_PACKETS_COUNT;
893 ndev->dma_virt = dma_alloc_coherent(&pci_dev->dev,
894 ndev->dma_size, &ndev->dma_phys, GFP_KERNEL);
895 if (!ndev->dma_virt) {
896 dev_err(&pci_dev->dev, "%s(): unable to allocate DMA buffer\n",
897 __func__);
898 goto dma_alloc_err;
899 }
900 netup_unidvb_dev_enable(ndev);
901 if (spi_enable && netup_spi_init(ndev)) {
902 dev_warn(&pci_dev->dev,
903 "netup_unidvb: SPI flash setup failed\n");
904 goto spi_setup_err;
905 }
906 if (old_firmware) {
907 dev_err(&pci_dev->dev,
908 "netup_unidvb: card initialization was incomplete\n");
909 return 0;
910 }
911 if (netup_i2c_register(ndev)) {
912 dev_err(&pci_dev->dev, "netup_unidvb: I2C setup failed\n");
913 goto i2c_setup_err;
914 }
915 /* enable I2C IRQs */
916 writew(NETUP_UNIDVB_IRQ_I2C0 | NETUP_UNIDVB_IRQ_I2C1,
917 ndev->bmmio0 + REG_IMASK_SET);
918 usleep_range(5000, 10000);
919 if (netup_unidvb_dvb_setup(ndev)) {
920 dev_err(&pci_dev->dev, "netup_unidvb: DVB setup failed\n");
921 goto dvb_setup_err;
922 }
923 if (netup_unidvb_ci_setup(ndev, pci_dev)) {
924 dev_err(&pci_dev->dev, "netup_unidvb: CI setup failed\n");
925 goto ci_setup_err;
926 }
927 if (netup_unidvb_dma_setup(ndev)) {
928 dev_err(&pci_dev->dev, "netup_unidvb: DMA setup failed\n");
929 goto dma_setup_err;
930 }
931 dev_info(&pci_dev->dev,
932 "netup_unidvb: device has been initialized\n");
933 return 0;
934 dma_setup_err:
935 netup_unidvb_ci_unregister(ndev, 0);
936 netup_unidvb_ci_unregister(ndev, 1);
937 ci_setup_err:
938 netup_unidvb_dvb_fini(ndev, 0);
939 netup_unidvb_dvb_fini(ndev, 1);
940 dvb_setup_err:
941 netup_i2c_unregister(ndev);
942 i2c_setup_err:
943 if (ndev->spi)
944 netup_spi_release(ndev);
945 spi_setup_err:
946 dma_free_coherent(&pci_dev->dev, ndev->dma_size,
947 ndev->dma_virt, ndev->dma_phys);
948 dma_alloc_err:
949 free_irq(pci_dev->irq, pci_dev);
950 irq_request_err:
951 iounmap(ndev->lmmio1);
952 pci_bar1_error:
953 iounmap(ndev->lmmio0);
954 pci_bar0_error:
955 release_mem_region(pci_resource_start(pci_dev, 0),
956 pci_resource_len(pci_dev, 0));
957 release_mem_region(pci_resource_start(pci_dev, 1),
958 pci_resource_len(pci_dev, 1));
959 pci_detect_err:
960 pci_disable_device(pci_dev);
961 pci_enable_err:
962 pci_set_drvdata(pci_dev, NULL);
963 destroy_workqueue(ndev->wq);
964 wq_create_err:
965 kfree(ndev);
966 dev_alloc_err:
967 dev_err(&pci_dev->dev,
968 "%s(): failed to initialize device\n", __func__);
969 return -EIO;
970 }
971
netup_unidvb_finidev(struct pci_dev * pci_dev)972 static void netup_unidvb_finidev(struct pci_dev *pci_dev)
973 {
974 struct netup_unidvb_dev *ndev = pci_get_drvdata(pci_dev);
975
976 dev_info(&pci_dev->dev, "%s(): trying to stop device\n", __func__);
977 if (!ndev->old_fw) {
978 netup_unidvb_dma_fini(ndev, 0);
979 netup_unidvb_dma_fini(ndev, 1);
980 netup_unidvb_ci_unregister(ndev, 0);
981 netup_unidvb_ci_unregister(ndev, 1);
982 netup_unidvb_dvb_fini(ndev, 0);
983 netup_unidvb_dvb_fini(ndev, 1);
984 netup_i2c_unregister(ndev);
985 }
986 if (ndev->spi)
987 netup_spi_release(ndev);
988 writew(0xffff, ndev->bmmio0 + REG_IMASK_CLEAR);
989 dma_free_coherent(&ndev->pci_dev->dev, ndev->dma_size,
990 ndev->dma_virt, ndev->dma_phys);
991 free_irq(pci_dev->irq, pci_dev);
992 iounmap(ndev->lmmio0);
993 iounmap(ndev->lmmio1);
994 release_mem_region(pci_resource_start(pci_dev, 0),
995 pci_resource_len(pci_dev, 0));
996 release_mem_region(pci_resource_start(pci_dev, 1),
997 pci_resource_len(pci_dev, 1));
998 pci_disable_device(pci_dev);
999 pci_set_drvdata(pci_dev, NULL);
1000 destroy_workqueue(ndev->wq);
1001 kfree(ndev);
1002 dev_info(&pci_dev->dev,
1003 "%s(): device has been successfully stopped\n", __func__);
1004 }
1005
1006
1007 static const struct pci_device_id netup_unidvb_pci_tbl[] = {
1008 { PCI_DEVICE(0x1b55, 0x18f6) }, /* hw rev. 1.3 */
1009 { PCI_DEVICE(0x1b55, 0x18f7) }, /* hw rev. 1.4 */
1010 { 0, }
1011 };
1012 MODULE_DEVICE_TABLE(pci, netup_unidvb_pci_tbl);
1013
1014 static struct pci_driver netup_unidvb_pci_driver = {
1015 .name = "netup_unidvb",
1016 .id_table = netup_unidvb_pci_tbl,
1017 .probe = netup_unidvb_initdev,
1018 .remove = netup_unidvb_finidev,
1019 };
1020
1021 module_pci_driver(netup_unidvb_pci_driver);
1022
