1 /* QLogic qedr NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <linux/module.h>
33 #include <rdma/ib_verbs.h>
34 #include <rdma/ib_addr.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/iw_cm.h>
37 #include <rdma/ib_mad.h>
38 #include <linux/netdevice.h>
39 #include <linux/iommu.h>
40 #include <linux/pci.h>
41 #include <net/addrconf.h>
42
43 #include <linux/qed/qed_chain.h>
44 #include <linux/qed/qed_if.h>
45 #include "qedr.h"
46 #include "verbs.h"
47 #include <rdma/qedr-abi.h>
48 #include "qedr_iw_cm.h"
49
50 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
51 MODULE_AUTHOR("QLogic Corporation");
52 MODULE_LICENSE("Dual BSD/GPL");
53
54 #define QEDR_WQ_MULTIPLIER_DFT (3)
55
qedr_ib_dispatch_event(struct qedr_dev * dev,u8 port_num,enum ib_event_type type)56 static void qedr_ib_dispatch_event(struct qedr_dev *dev, u8 port_num,
57 enum ib_event_type type)
58 {
59 struct ib_event ibev;
60
61 ibev.device = &dev->ibdev;
62 ibev.element.port_num = port_num;
63 ibev.event = type;
64
65 ib_dispatch_event(&ibev);
66 }
67
qedr_link_layer(struct ib_device * device,u8 port_num)68 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
69 u8 port_num)
70 {
71 return IB_LINK_LAYER_ETHERNET;
72 }
73
qedr_get_dev_fw_str(struct ib_device * ibdev,char * str)74 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
75 {
76 struct qedr_dev *qedr = get_qedr_dev(ibdev);
77 u32 fw_ver = (u32)qedr->attr.fw_ver;
78
79 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
80 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
81 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
82 }
83
qedr_roce_port_immutable(struct ib_device * ibdev,u8 port_num,struct ib_port_immutable * immutable)84 static int qedr_roce_port_immutable(struct ib_device *ibdev, u8 port_num,
85 struct ib_port_immutable *immutable)
86 {
87 struct ib_port_attr attr;
88 int err;
89
90 err = qedr_query_port(ibdev, port_num, &attr);
91 if (err)
92 return err;
93
94 immutable->pkey_tbl_len = attr.pkey_tbl_len;
95 immutable->gid_tbl_len = attr.gid_tbl_len;
96 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
97 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
98 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
99
100 return 0;
101 }
102
qedr_iw_port_immutable(struct ib_device * ibdev,u8 port_num,struct ib_port_immutable * immutable)103 static int qedr_iw_port_immutable(struct ib_device *ibdev, u8 port_num,
104 struct ib_port_immutable *immutable)
105 {
106 struct ib_port_attr attr;
107 int err;
108
109 err = qedr_query_port(ibdev, port_num, &attr);
110 if (err)
111 return err;
112
113 immutable->gid_tbl_len = 1;
114 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
115 immutable->max_mad_size = 0;
116
117 return 0;
118 }
119
120 /* QEDR sysfs interface */
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)121 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
122 char *buf)
123 {
124 struct qedr_dev *dev =
125 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
126
127 return scnprintf(buf, PAGE_SIZE, "0x%x\n", dev->attr.hw_ver);
128 }
129 static DEVICE_ATTR_RO(hw_rev);
130
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)131 static ssize_t hca_type_show(struct device *device,
132 struct device_attribute *attr, char *buf)
133 {
134 struct qedr_dev *dev =
135 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
136
137 return scnprintf(buf, PAGE_SIZE, "FastLinQ QL%x %s\n",
138 dev->pdev->device,
139 rdma_protocol_iwarp(&dev->ibdev, 1) ?
140 "iWARP" : "RoCE");
141 }
142 static DEVICE_ATTR_RO(hca_type);
143
144 static struct attribute *qedr_attributes[] = {
145 &dev_attr_hw_rev.attr,
146 &dev_attr_hca_type.attr,
147 NULL
148 };
149
150 static const struct attribute_group qedr_attr_group = {
151 .attrs = qedr_attributes,
152 };
153
154 static const struct ib_device_ops qedr_iw_dev_ops = {
155 .get_port_immutable = qedr_iw_port_immutable,
156 .iw_accept = qedr_iw_accept,
157 .iw_add_ref = qedr_iw_qp_add_ref,
158 .iw_connect = qedr_iw_connect,
159 .iw_create_listen = qedr_iw_create_listen,
160 .iw_destroy_listen = qedr_iw_destroy_listen,
161 .iw_get_qp = qedr_iw_get_qp,
162 .iw_reject = qedr_iw_reject,
163 .iw_rem_ref = qedr_iw_qp_rem_ref,
164 .query_gid = qedr_iw_query_gid,
165 };
166
qedr_iw_register_device(struct qedr_dev * dev)167 static int qedr_iw_register_device(struct qedr_dev *dev)
168 {
169 dev->ibdev.node_type = RDMA_NODE_RNIC;
170
171 ib_set_device_ops(&dev->ibdev, &qedr_iw_dev_ops);
172
173 memcpy(dev->ibdev.iw_ifname,
174 dev->ndev->name, sizeof(dev->ibdev.iw_ifname));
175
176 return 0;
177 }
178
179 static const struct ib_device_ops qedr_roce_dev_ops = {
180 .alloc_xrcd = qedr_alloc_xrcd,
181 .dealloc_xrcd = qedr_dealloc_xrcd,
182 .get_port_immutable = qedr_roce_port_immutable,
183 .query_pkey = qedr_query_pkey,
184 };
185
qedr_roce_register_device(struct qedr_dev * dev)186 static void qedr_roce_register_device(struct qedr_dev *dev)
187 {
188 dev->ibdev.node_type = RDMA_NODE_IB_CA;
189
190 ib_set_device_ops(&dev->ibdev, &qedr_roce_dev_ops);
191
192 dev->ibdev.uverbs_cmd_mask |= QEDR_UVERBS(OPEN_XRCD) |
193 QEDR_UVERBS(CLOSE_XRCD) |
194 QEDR_UVERBS(CREATE_XSRQ);
195 }
196
197 static const struct ib_device_ops qedr_dev_ops = {
198 .owner = THIS_MODULE,
199 .driver_id = RDMA_DRIVER_QEDR,
200 .uverbs_abi_ver = QEDR_ABI_VERSION,
201
202 .alloc_mr = qedr_alloc_mr,
203 .alloc_pd = qedr_alloc_pd,
204 .alloc_ucontext = qedr_alloc_ucontext,
205 .create_ah = qedr_create_ah,
206 .create_cq = qedr_create_cq,
207 .create_qp = qedr_create_qp,
208 .create_srq = qedr_create_srq,
209 .dealloc_pd = qedr_dealloc_pd,
210 .dealloc_ucontext = qedr_dealloc_ucontext,
211 .dereg_mr = qedr_dereg_mr,
212 .destroy_ah = qedr_destroy_ah,
213 .destroy_cq = qedr_destroy_cq,
214 .destroy_qp = qedr_destroy_qp,
215 .destroy_srq = qedr_destroy_srq,
216 .get_dev_fw_str = qedr_get_dev_fw_str,
217 .get_dma_mr = qedr_get_dma_mr,
218 .get_link_layer = qedr_link_layer,
219 .map_mr_sg = qedr_map_mr_sg,
220 .mmap = qedr_mmap,
221 .mmap_free = qedr_mmap_free,
222 .modify_qp = qedr_modify_qp,
223 .modify_srq = qedr_modify_srq,
224 .poll_cq = qedr_poll_cq,
225 .post_recv = qedr_post_recv,
226 .post_send = qedr_post_send,
227 .post_srq_recv = qedr_post_srq_recv,
228 .process_mad = qedr_process_mad,
229 .query_device = qedr_query_device,
230 .query_port = qedr_query_port,
231 .query_qp = qedr_query_qp,
232 .query_srq = qedr_query_srq,
233 .reg_user_mr = qedr_reg_user_mr,
234 .req_notify_cq = qedr_arm_cq,
235 .resize_cq = qedr_resize_cq,
236
237 INIT_RDMA_OBJ_SIZE(ib_ah, qedr_ah, ibah),
238 INIT_RDMA_OBJ_SIZE(ib_cq, qedr_cq, ibcq),
239 INIT_RDMA_OBJ_SIZE(ib_pd, qedr_pd, ibpd),
240 INIT_RDMA_OBJ_SIZE(ib_srq, qedr_srq, ibsrq),
241 INIT_RDMA_OBJ_SIZE(ib_xrcd, qedr_xrcd, ibxrcd),
242 INIT_RDMA_OBJ_SIZE(ib_ucontext, qedr_ucontext, ibucontext),
243 };
244
qedr_register_device(struct qedr_dev * dev)245 static int qedr_register_device(struct qedr_dev *dev)
246 {
247 int rc;
248
249 dev->ibdev.node_guid = dev->attr.node_guid;
250 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
251
252 dev->ibdev.uverbs_cmd_mask = QEDR_UVERBS(GET_CONTEXT) |
253 QEDR_UVERBS(QUERY_DEVICE) |
254 QEDR_UVERBS(QUERY_PORT) |
255 QEDR_UVERBS(ALLOC_PD) |
256 QEDR_UVERBS(DEALLOC_PD) |
257 QEDR_UVERBS(CREATE_COMP_CHANNEL) |
258 QEDR_UVERBS(CREATE_CQ) |
259 QEDR_UVERBS(RESIZE_CQ) |
260 QEDR_UVERBS(DESTROY_CQ) |
261 QEDR_UVERBS(REQ_NOTIFY_CQ) |
262 QEDR_UVERBS(CREATE_QP) |
263 QEDR_UVERBS(MODIFY_QP) |
264 QEDR_UVERBS(QUERY_QP) |
265 QEDR_UVERBS(DESTROY_QP) |
266 QEDR_UVERBS(CREATE_SRQ) |
267 QEDR_UVERBS(DESTROY_SRQ) |
268 QEDR_UVERBS(QUERY_SRQ) |
269 QEDR_UVERBS(MODIFY_SRQ) |
270 QEDR_UVERBS(POST_SRQ_RECV) |
271 QEDR_UVERBS(REG_MR) |
272 QEDR_UVERBS(DEREG_MR) |
273 QEDR_UVERBS(POLL_CQ) |
274 QEDR_UVERBS(POST_SEND) |
275 QEDR_UVERBS(POST_RECV);
276
277 if (IS_IWARP(dev)) {
278 rc = qedr_iw_register_device(dev);
279 if (rc)
280 return rc;
281 } else {
282 qedr_roce_register_device(dev);
283 }
284
285 dev->ibdev.phys_port_cnt = 1;
286 dev->ibdev.num_comp_vectors = dev->num_cnq;
287 dev->ibdev.dev.parent = &dev->pdev->dev;
288
289 rdma_set_device_sysfs_group(&dev->ibdev, &qedr_attr_group);
290 ib_set_device_ops(&dev->ibdev, &qedr_dev_ops);
291
292 rc = ib_device_set_netdev(&dev->ibdev, dev->ndev, 1);
293 if (rc)
294 return rc;
295
296 dma_set_max_seg_size(&dev->pdev->dev, UINT_MAX);
297 return ib_register_device(&dev->ibdev, "qedr%d", &dev->pdev->dev);
298 }
299
300 /* This function allocates fast-path status block memory */
qedr_alloc_mem_sb(struct qedr_dev * dev,struct qed_sb_info * sb_info,u16 sb_id)301 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
302 struct qed_sb_info *sb_info, u16 sb_id)
303 {
304 struct status_block_e4 *sb_virt;
305 dma_addr_t sb_phys;
306 int rc;
307
308 sb_virt = dma_alloc_coherent(&dev->pdev->dev,
309 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
310 if (!sb_virt)
311 return -ENOMEM;
312
313 rc = dev->ops->common->sb_init(dev->cdev, sb_info,
314 sb_virt, sb_phys, sb_id,
315 QED_SB_TYPE_CNQ);
316 if (rc) {
317 pr_err("Status block initialization failed\n");
318 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
319 sb_virt, sb_phys);
320 return rc;
321 }
322
323 return 0;
324 }
325
qedr_free_mem_sb(struct qedr_dev * dev,struct qed_sb_info * sb_info,int sb_id)326 static void qedr_free_mem_sb(struct qedr_dev *dev,
327 struct qed_sb_info *sb_info, int sb_id)
328 {
329 if (sb_info->sb_virt) {
330 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id,
331 QED_SB_TYPE_CNQ);
332 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
333 (void *)sb_info->sb_virt, sb_info->sb_phys);
334 }
335 }
336
qedr_free_resources(struct qedr_dev * dev)337 static void qedr_free_resources(struct qedr_dev *dev)
338 {
339 int i;
340
341 if (IS_IWARP(dev))
342 destroy_workqueue(dev->iwarp_wq);
343
344 for (i = 0; i < dev->num_cnq; i++) {
345 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
346 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
347 }
348
349 kfree(dev->cnq_array);
350 kfree(dev->sb_array);
351 kfree(dev->sgid_tbl);
352 }
353
qedr_alloc_resources(struct qedr_dev * dev)354 static int qedr_alloc_resources(struct qedr_dev *dev)
355 {
356 struct qed_chain_init_params params = {
357 .mode = QED_CHAIN_MODE_PBL,
358 .intended_use = QED_CHAIN_USE_TO_CONSUME,
359 .cnt_type = QED_CHAIN_CNT_TYPE_U16,
360 .elem_size = sizeof(struct regpair *),
361 };
362 struct qedr_cnq *cnq;
363 __le16 *cons_pi;
364 int i, rc;
365
366 dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid),
367 GFP_KERNEL);
368 if (!dev->sgid_tbl)
369 return -ENOMEM;
370
371 spin_lock_init(&dev->sgid_lock);
372 xa_init_flags(&dev->srqs, XA_FLAGS_LOCK_IRQ);
373
374 if (IS_IWARP(dev)) {
375 xa_init(&dev->qps);
376 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
377 }
378
379 /* Allocate Status blocks for CNQ */
380 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
381 GFP_KERNEL);
382 if (!dev->sb_array) {
383 rc = -ENOMEM;
384 goto err1;
385 }
386
387 dev->cnq_array = kcalloc(dev->num_cnq,
388 sizeof(*dev->cnq_array), GFP_KERNEL);
389 if (!dev->cnq_array) {
390 rc = -ENOMEM;
391 goto err2;
392 }
393
394 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
395
396 /* Allocate CNQ PBLs */
397 params.num_elems = min_t(u32, QED_RDMA_MAX_CNQ_SIZE,
398 QEDR_ROCE_MAX_CNQ_SIZE);
399
400 for (i = 0; i < dev->num_cnq; i++) {
401 cnq = &dev->cnq_array[i];
402
403 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
404 dev->sb_start + i);
405 if (rc)
406 goto err3;
407
408 rc = dev->ops->common->chain_alloc(dev->cdev, &cnq->pbl,
409 ¶ms);
410 if (rc)
411 goto err4;
412
413 cnq->dev = dev;
414 cnq->sb = &dev->sb_array[i];
415 cons_pi = dev->sb_array[i].sb_virt->pi_array;
416 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
417 cnq->index = i;
418 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
419
420 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
421 i, qed_chain_get_cons_idx(&cnq->pbl));
422 }
423
424 return 0;
425 err4:
426 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
427 err3:
428 for (--i; i >= 0; i--) {
429 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
430 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
431 }
432 kfree(dev->cnq_array);
433 err2:
434 kfree(dev->sb_array);
435 err1:
436 kfree(dev->sgid_tbl);
437 return rc;
438 }
439
qedr_pci_set_atomic(struct qedr_dev * dev,struct pci_dev * pdev)440 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
441 {
442 int rc = pci_enable_atomic_ops_to_root(pdev,
443 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
444
445 if (rc) {
446 dev->atomic_cap = IB_ATOMIC_NONE;
447 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
448 } else {
449 dev->atomic_cap = IB_ATOMIC_GLOB;
450 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
451 }
452 }
453
454 static const struct qed_rdma_ops *qed_ops;
455
456 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
457
qedr_irq_handler(int irq,void * handle)458 static irqreturn_t qedr_irq_handler(int irq, void *handle)
459 {
460 u16 hw_comp_cons, sw_comp_cons;
461 struct qedr_cnq *cnq = handle;
462 struct regpair *cq_handle;
463 struct qedr_cq *cq;
464
465 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
466
467 qed_sb_update_sb_idx(cnq->sb);
468
469 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
470 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
471
472 /* Align protocol-index and chain reads */
473 rmb();
474
475 while (sw_comp_cons != hw_comp_cons) {
476 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
477 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
478 cq_handle->lo);
479
480 if (cq == NULL) {
481 DP_ERR(cnq->dev,
482 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
483 cq_handle->hi, cq_handle->lo, sw_comp_cons,
484 hw_comp_cons);
485
486 break;
487 }
488
489 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
490 DP_ERR(cnq->dev,
491 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
492 cq_handle->hi, cq_handle->lo, cq);
493 break;
494 }
495
496 cq->arm_flags = 0;
497
498 if (!cq->destroyed && cq->ibcq.comp_handler)
499 (*cq->ibcq.comp_handler)
500 (&cq->ibcq, cq->ibcq.cq_context);
501
502 /* The CQ's CNQ notification counter is checked before
503 * destroying the CQ in a busy-wait loop that waits for all of
504 * the CQ's CNQ interrupts to be processed. It is increased
505 * here, only after the completion handler, to ensure that the
506 * the handler is not running when the CQ is destroyed.
507 */
508 cq->cnq_notif++;
509
510 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
511
512 cnq->n_comp++;
513 }
514
515 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
516 sw_comp_cons);
517
518 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
519
520 return IRQ_HANDLED;
521 }
522
qedr_sync_free_irqs(struct qedr_dev * dev)523 static void qedr_sync_free_irqs(struct qedr_dev *dev)
524 {
525 u32 vector;
526 u16 idx;
527 int i;
528
529 for (i = 0; i < dev->int_info.used_cnt; i++) {
530 if (dev->int_info.msix_cnt) {
531 idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
532 vector = dev->int_info.msix[idx].vector;
533 synchronize_irq(vector);
534 free_irq(vector, &dev->cnq_array[i]);
535 }
536 }
537
538 dev->int_info.used_cnt = 0;
539 }
540
qedr_req_msix_irqs(struct qedr_dev * dev)541 static int qedr_req_msix_irqs(struct qedr_dev *dev)
542 {
543 int i, rc = 0;
544 u16 idx;
545
546 if (dev->num_cnq > dev->int_info.msix_cnt) {
547 DP_ERR(dev,
548 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
549 dev->num_cnq, dev->int_info.msix_cnt);
550 return -EINVAL;
551 }
552
553 for (i = 0; i < dev->num_cnq; i++) {
554 idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
555 rc = request_irq(dev->int_info.msix[idx].vector,
556 qedr_irq_handler, 0, dev->cnq_array[i].name,
557 &dev->cnq_array[i]);
558 if (rc) {
559 DP_ERR(dev, "Request cnq %d irq failed\n", i);
560 qedr_sync_free_irqs(dev);
561 } else {
562 DP_DEBUG(dev, QEDR_MSG_INIT,
563 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
564 dev->cnq_array[i].name, i,
565 &dev->cnq_array[i]);
566 dev->int_info.used_cnt++;
567 }
568 }
569
570 return rc;
571 }
572
qedr_setup_irqs(struct qedr_dev * dev)573 static int qedr_setup_irqs(struct qedr_dev *dev)
574 {
575 int rc;
576
577 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
578
579 /* Learn Interrupt configuration */
580 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
581 if (rc < 0)
582 return rc;
583
584 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
585 if (rc) {
586 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
587 return rc;
588 }
589
590 if (dev->int_info.msix_cnt) {
591 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
592 dev->int_info.msix_cnt);
593 rc = qedr_req_msix_irqs(dev);
594 if (rc)
595 return rc;
596 }
597
598 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
599
600 return 0;
601 }
602
qedr_set_device_attr(struct qedr_dev * dev)603 static int qedr_set_device_attr(struct qedr_dev *dev)
604 {
605 struct qed_rdma_device *qed_attr;
606 struct qedr_device_attr *attr;
607 u32 page_size;
608
609 /* Part 1 - query core capabilities */
610 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
611
612 /* Part 2 - check capabilities */
613 page_size = ~qed_attr->page_size_caps + 1;
614 if (page_size > PAGE_SIZE) {
615 DP_ERR(dev,
616 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
617 PAGE_SIZE, page_size);
618 return -ENODEV;
619 }
620
621 /* Part 3 - copy and update capabilities */
622 attr = &dev->attr;
623 attr->vendor_id = qed_attr->vendor_id;
624 attr->vendor_part_id = qed_attr->vendor_part_id;
625 attr->hw_ver = qed_attr->hw_ver;
626 attr->fw_ver = qed_attr->fw_ver;
627 attr->node_guid = qed_attr->node_guid;
628 attr->sys_image_guid = qed_attr->sys_image_guid;
629 attr->max_cnq = qed_attr->max_cnq;
630 attr->max_sge = qed_attr->max_sge;
631 attr->max_inline = qed_attr->max_inline;
632 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
633 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
634 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
635 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
636 attr->max_dev_resp_rd_atomic_resc =
637 qed_attr->max_dev_resp_rd_atomic_resc;
638 attr->max_cq = qed_attr->max_cq;
639 attr->max_qp = qed_attr->max_qp;
640 attr->max_mr = qed_attr->max_mr;
641 attr->max_mr_size = qed_attr->max_mr_size;
642 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
643 attr->max_mw = qed_attr->max_mw;
644 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
645 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
646 attr->max_pd = qed_attr->max_pd;
647 attr->max_ah = qed_attr->max_ah;
648 attr->max_pkey = qed_attr->max_pkey;
649 attr->max_srq = qed_attr->max_srq;
650 attr->max_srq_wr = qed_attr->max_srq_wr;
651 attr->dev_caps = qed_attr->dev_caps;
652 attr->page_size_caps = qed_attr->page_size_caps;
653 attr->dev_ack_delay = qed_attr->dev_ack_delay;
654 attr->reserved_lkey = qed_attr->reserved_lkey;
655 attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
656 attr->max_stats_queues = qed_attr->max_stats_queues;
657
658 return 0;
659 }
660
qedr_unaffiliated_event(void * context,u8 event_code)661 static void qedr_unaffiliated_event(void *context, u8 event_code)
662 {
663 pr_err("unaffiliated event not implemented yet\n");
664 }
665
qedr_affiliated_event(void * context,u8 e_code,void * fw_handle)666 static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
667 {
668 #define EVENT_TYPE_NOT_DEFINED 0
669 #define EVENT_TYPE_CQ 1
670 #define EVENT_TYPE_QP 2
671 #define EVENT_TYPE_SRQ 3
672 struct qedr_dev *dev = (struct qedr_dev *)context;
673 struct regpair *async_handle = (struct regpair *)fw_handle;
674 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
675 u8 event_type = EVENT_TYPE_NOT_DEFINED;
676 struct ib_event event;
677 struct ib_srq *ibsrq;
678 struct qedr_srq *srq;
679 unsigned long flags;
680 struct ib_cq *ibcq;
681 struct ib_qp *ibqp;
682 struct qedr_cq *cq;
683 struct qedr_qp *qp;
684 u16 srq_id;
685
686 if (IS_ROCE(dev)) {
687 switch (e_code) {
688 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
689 event.event = IB_EVENT_CQ_ERR;
690 event_type = EVENT_TYPE_CQ;
691 break;
692 case ROCE_ASYNC_EVENT_SQ_DRAINED:
693 event.event = IB_EVENT_SQ_DRAINED;
694 event_type = EVENT_TYPE_QP;
695 break;
696 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
697 event.event = IB_EVENT_QP_FATAL;
698 event_type = EVENT_TYPE_QP;
699 break;
700 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
701 event.event = IB_EVENT_QP_REQ_ERR;
702 event_type = EVENT_TYPE_QP;
703 break;
704 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
705 event.event = IB_EVENT_QP_ACCESS_ERR;
706 event_type = EVENT_TYPE_QP;
707 break;
708 case ROCE_ASYNC_EVENT_SRQ_LIMIT:
709 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
710 event_type = EVENT_TYPE_SRQ;
711 break;
712 case ROCE_ASYNC_EVENT_SRQ_EMPTY:
713 event.event = IB_EVENT_SRQ_ERR;
714 event_type = EVENT_TYPE_SRQ;
715 break;
716 case ROCE_ASYNC_EVENT_XRC_DOMAIN_ERR:
717 event.event = IB_EVENT_QP_ACCESS_ERR;
718 event_type = EVENT_TYPE_QP;
719 break;
720 case ROCE_ASYNC_EVENT_INVALID_XRCETH_ERR:
721 event.event = IB_EVENT_QP_ACCESS_ERR;
722 event_type = EVENT_TYPE_QP;
723 break;
724 case ROCE_ASYNC_EVENT_XRC_SRQ_CATASTROPHIC_ERR:
725 event.event = IB_EVENT_CQ_ERR;
726 event_type = EVENT_TYPE_CQ;
727 break;
728 default:
729 DP_ERR(dev, "unsupported event %d on handle=%llx\n",
730 e_code, roce_handle64);
731 }
732 } else {
733 switch (e_code) {
734 case QED_IWARP_EVENT_SRQ_LIMIT:
735 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
736 event_type = EVENT_TYPE_SRQ;
737 break;
738 case QED_IWARP_EVENT_SRQ_EMPTY:
739 event.event = IB_EVENT_SRQ_ERR;
740 event_type = EVENT_TYPE_SRQ;
741 break;
742 default:
743 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
744 roce_handle64);
745 }
746 }
747 switch (event_type) {
748 case EVENT_TYPE_CQ:
749 cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
750 if (cq) {
751 ibcq = &cq->ibcq;
752 if (ibcq->event_handler) {
753 event.device = ibcq->device;
754 event.element.cq = ibcq;
755 ibcq->event_handler(&event, ibcq->cq_context);
756 }
757 } else {
758 WARN(1,
759 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
760 roce_handle64);
761 }
762 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq);
763 break;
764 case EVENT_TYPE_QP:
765 qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
766 if (qp) {
767 ibqp = &qp->ibqp;
768 if (ibqp->event_handler) {
769 event.device = ibqp->device;
770 event.element.qp = ibqp;
771 ibqp->event_handler(&event, ibqp->qp_context);
772 }
773 } else {
774 WARN(1,
775 "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
776 roce_handle64);
777 }
778 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp);
779 break;
780 case EVENT_TYPE_SRQ:
781 srq_id = (u16)roce_handle64;
782 xa_lock_irqsave(&dev->srqs, flags);
783 srq = xa_load(&dev->srqs, srq_id);
784 if (srq) {
785 ibsrq = &srq->ibsrq;
786 if (ibsrq->event_handler) {
787 event.device = ibsrq->device;
788 event.element.srq = ibsrq;
789 ibsrq->event_handler(&event,
790 ibsrq->srq_context);
791 }
792 } else {
793 DP_NOTICE(dev,
794 "SRQ event with NULL pointer ibsrq. Handle=%llx\n",
795 roce_handle64);
796 }
797 xa_unlock_irqrestore(&dev->srqs, flags);
798 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq);
799 default:
800 break;
801 }
802 }
803
qedr_init_hw(struct qedr_dev * dev)804 static int qedr_init_hw(struct qedr_dev *dev)
805 {
806 struct qed_rdma_add_user_out_params out_params;
807 struct qed_rdma_start_in_params *in_params;
808 struct qed_rdma_cnq_params *cur_pbl;
809 struct qed_rdma_events events;
810 dma_addr_t p_phys_table;
811 u32 page_cnt;
812 int rc = 0;
813 int i;
814
815 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL);
816 if (!in_params) {
817 rc = -ENOMEM;
818 goto out;
819 }
820
821 in_params->desired_cnq = dev->num_cnq;
822 for (i = 0; i < dev->num_cnq; i++) {
823 cur_pbl = &in_params->cnq_pbl_list[i];
824
825 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
826 cur_pbl->num_pbl_pages = page_cnt;
827
828 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
829 cur_pbl->pbl_ptr = (u64)p_phys_table;
830 }
831
832 events.affiliated_event = qedr_affiliated_event;
833 events.unaffiliated_event = qedr_unaffiliated_event;
834 events.context = dev;
835
836 in_params->events = &events;
837 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
838 in_params->max_mtu = dev->ndev->mtu;
839 dev->iwarp_max_mtu = dev->ndev->mtu;
840 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
841
842 rc = dev->ops->rdma_init(dev->cdev, in_params);
843 if (rc)
844 goto out;
845
846 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
847 if (rc)
848 goto out;
849
850 dev->db_addr = out_params.dpi_addr;
851 dev->db_phys_addr = out_params.dpi_phys_addr;
852 dev->db_size = out_params.dpi_size;
853 dev->dpi = out_params.dpi;
854
855 rc = qedr_set_device_attr(dev);
856 out:
857 kfree(in_params);
858 if (rc)
859 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
860
861 return rc;
862 }
863
qedr_stop_hw(struct qedr_dev * dev)864 static void qedr_stop_hw(struct qedr_dev *dev)
865 {
866 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
867 dev->ops->rdma_stop(dev->rdma_ctx);
868 }
869
qedr_add(struct qed_dev * cdev,struct pci_dev * pdev,struct net_device * ndev)870 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
871 struct net_device *ndev)
872 {
873 struct qed_dev_rdma_info dev_info;
874 struct qedr_dev *dev;
875 int rc = 0;
876
877 dev = ib_alloc_device(qedr_dev, ibdev);
878 if (!dev) {
879 pr_err("Unable to allocate ib device\n");
880 return NULL;
881 }
882
883 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
884
885 dev->pdev = pdev;
886 dev->ndev = ndev;
887 dev->cdev = cdev;
888
889 qed_ops = qed_get_rdma_ops();
890 if (!qed_ops) {
891 DP_ERR(dev, "Failed to get qed roce operations\n");
892 goto init_err;
893 }
894
895 dev->ops = qed_ops;
896 rc = qed_ops->fill_dev_info(cdev, &dev_info);
897 if (rc)
898 goto init_err;
899
900 dev->user_dpm_enabled = dev_info.user_dpm_enabled;
901 dev->rdma_type = dev_info.rdma_type;
902 dev->num_hwfns = dev_info.common.num_hwfns;
903
904 if (IS_IWARP(dev) && QEDR_IS_CMT(dev)) {
905 rc = dev->ops->iwarp_set_engine_affin(cdev, false);
906 if (rc) {
907 DP_ERR(dev, "iWARP is disabled over a 100g device Enabling it may impact L2 performance. To enable it run devlink dev param set <dev> name iwarp_cmt value true cmode runtime\n");
908 goto init_err;
909 }
910 }
911 dev->affin_hwfn_idx = dev->ops->common->get_affin_hwfn_idx(cdev);
912
913 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
914
915 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
916 if (!dev->num_cnq) {
917 DP_ERR(dev, "Failed. At least one CNQ is required.\n");
918 rc = -ENOMEM;
919 goto init_err;
920 }
921
922 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
923
924 qedr_pci_set_atomic(dev, pdev);
925
926 rc = qedr_alloc_resources(dev);
927 if (rc)
928 goto init_err;
929
930 rc = qedr_init_hw(dev);
931 if (rc)
932 goto alloc_err;
933
934 rc = qedr_setup_irqs(dev);
935 if (rc)
936 goto irq_err;
937
938 rc = qedr_register_device(dev);
939 if (rc) {
940 DP_ERR(dev, "Unable to allocate register device\n");
941 goto reg_err;
942 }
943
944 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
945 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
946
947 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
948 return dev;
949
950 reg_err:
951 qedr_sync_free_irqs(dev);
952 irq_err:
953 qedr_stop_hw(dev);
954 alloc_err:
955 qedr_free_resources(dev);
956 init_err:
957 ib_dealloc_device(&dev->ibdev);
958 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
959
960 return NULL;
961 }
962
qedr_remove(struct qedr_dev * dev)963 static void qedr_remove(struct qedr_dev *dev)
964 {
965 /* First unregister with stack to stop all the active traffic
966 * of the registered clients.
967 */
968 ib_unregister_device(&dev->ibdev);
969
970 qedr_stop_hw(dev);
971 qedr_sync_free_irqs(dev);
972 qedr_free_resources(dev);
973
974 if (IS_IWARP(dev) && QEDR_IS_CMT(dev))
975 dev->ops->iwarp_set_engine_affin(dev->cdev, true);
976
977 ib_dealloc_device(&dev->ibdev);
978 }
979
qedr_close(struct qedr_dev * dev)980 static void qedr_close(struct qedr_dev *dev)
981 {
982 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
983 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
984 }
985
qedr_shutdown(struct qedr_dev * dev)986 static void qedr_shutdown(struct qedr_dev *dev)
987 {
988 qedr_close(dev);
989 qedr_remove(dev);
990 }
991
qedr_open(struct qedr_dev * dev)992 static void qedr_open(struct qedr_dev *dev)
993 {
994 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
995 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
996 }
997
qedr_mac_address_change(struct qedr_dev * dev)998 static void qedr_mac_address_change(struct qedr_dev *dev)
999 {
1000 union ib_gid *sgid = &dev->sgid_tbl[0];
1001 u8 guid[8], mac_addr[6];
1002 int rc;
1003
1004 /* Update SGID */
1005 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
1006 guid[0] = mac_addr[0] ^ 2;
1007 guid[1] = mac_addr[1];
1008 guid[2] = mac_addr[2];
1009 guid[3] = 0xff;
1010 guid[4] = 0xfe;
1011 guid[5] = mac_addr[3];
1012 guid[6] = mac_addr[4];
1013 guid[7] = mac_addr[5];
1014 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
1015 memcpy(&sgid->raw[8], guid, sizeof(guid));
1016
1017 /* Update LL2 */
1018 rc = dev->ops->ll2_set_mac_filter(dev->cdev,
1019 dev->gsi_ll2_mac_address,
1020 dev->ndev->dev_addr);
1021
1022 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
1023
1024 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
1025
1026 if (rc)
1027 DP_ERR(dev, "Error updating mac filter\n");
1028 }
1029
1030 /* event handling via NIC driver ensures that all the NIC specific
1031 * initialization done before RoCE driver notifies
1032 * event to stack.
1033 */
qedr_notify(struct qedr_dev * dev,enum qede_rdma_event event)1034 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
1035 {
1036 switch (event) {
1037 case QEDE_UP:
1038 qedr_open(dev);
1039 break;
1040 case QEDE_DOWN:
1041 qedr_close(dev);
1042 break;
1043 case QEDE_CLOSE:
1044 qedr_shutdown(dev);
1045 break;
1046 case QEDE_CHANGE_ADDR:
1047 qedr_mac_address_change(dev);
1048 break;
1049 case QEDE_CHANGE_MTU:
1050 if (rdma_protocol_iwarp(&dev->ibdev, 1))
1051 if (dev->ndev->mtu != dev->iwarp_max_mtu)
1052 DP_NOTICE(dev,
1053 "Mtu was changed from %d to %d. This will not take affect for iWARP until qedr is reloaded\n",
1054 dev->iwarp_max_mtu, dev->ndev->mtu);
1055 break;
1056 default:
1057 pr_err("Event not supported\n");
1058 }
1059 }
1060
1061 static struct qedr_driver qedr_drv = {
1062 .name = "qedr_driver",
1063 .add = qedr_add,
1064 .remove = qedr_remove,
1065 .notify = qedr_notify,
1066 };
1067
qedr_init_module(void)1068 static int __init qedr_init_module(void)
1069 {
1070 return qede_rdma_register_driver(&qedr_drv);
1071 }
1072
qedr_exit_module(void)1073 static void __exit qedr_exit_module(void)
1074 {
1075 qede_rdma_unregister_driver(&qedr_drv);
1076 }
1077
1078 module_init(qedr_init_module);
1079 module_exit(qedr_exit_module);
1080
