1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * BMI160 - Bosch IMU (accel, gyro plus external magnetometer)
4 *
5 * Copyright (c) 2016, Intel Corporation.
6 * Copyright (c) 2019, Martin Kelly.
7 *
8 * IIO core driver for BMI160, with support for I2C/SPI busses
9 *
10 * TODO: magnetometer, hardware FIFO
11 */
12 #include <linux/module.h>
13 #include <linux/regmap.h>
14 #include <linux/acpi.h>
15 #include <linux/delay.h>
16 #include <linux/irq.h>
17 #include <linux/of_irq.h>
18 #include <linux/regulator/consumer.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/triggered_buffer.h>
22 #include <linux/iio/trigger_consumer.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/trigger.h>
26
27 #include "bmi160.h"
28
29 #define BMI160_REG_CHIP_ID 0x00
30 #define BMI160_CHIP_ID_VAL 0xD1
31
32 #define BMI160_REG_PMU_STATUS 0x03
33
34 /* X axis data low byte address, the rest can be obtained using axis offset */
35 #define BMI160_REG_DATA_MAGN_XOUT_L 0x04
36 #define BMI160_REG_DATA_GYRO_XOUT_L 0x0C
37 #define BMI160_REG_DATA_ACCEL_XOUT_L 0x12
38
39 #define BMI160_REG_ACCEL_CONFIG 0x40
40 #define BMI160_ACCEL_CONFIG_ODR_MASK GENMASK(3, 0)
41 #define BMI160_ACCEL_CONFIG_BWP_MASK GENMASK(6, 4)
42
43 #define BMI160_REG_ACCEL_RANGE 0x41
44 #define BMI160_ACCEL_RANGE_2G 0x03
45 #define BMI160_ACCEL_RANGE_4G 0x05
46 #define BMI160_ACCEL_RANGE_8G 0x08
47 #define BMI160_ACCEL_RANGE_16G 0x0C
48
49 #define BMI160_REG_GYRO_CONFIG 0x42
50 #define BMI160_GYRO_CONFIG_ODR_MASK GENMASK(3, 0)
51 #define BMI160_GYRO_CONFIG_BWP_MASK GENMASK(5, 4)
52
53 #define BMI160_REG_GYRO_RANGE 0x43
54 #define BMI160_GYRO_RANGE_2000DPS 0x00
55 #define BMI160_GYRO_RANGE_1000DPS 0x01
56 #define BMI160_GYRO_RANGE_500DPS 0x02
57 #define BMI160_GYRO_RANGE_250DPS 0x03
58 #define BMI160_GYRO_RANGE_125DPS 0x04
59
60 #define BMI160_REG_CMD 0x7E
61 #define BMI160_CMD_ACCEL_PM_SUSPEND 0x10
62 #define BMI160_CMD_ACCEL_PM_NORMAL 0x11
63 #define BMI160_CMD_ACCEL_PM_LOW_POWER 0x12
64 #define BMI160_CMD_GYRO_PM_SUSPEND 0x14
65 #define BMI160_CMD_GYRO_PM_NORMAL 0x15
66 #define BMI160_CMD_GYRO_PM_FAST_STARTUP 0x17
67 #define BMI160_CMD_SOFTRESET 0xB6
68
69 #define BMI160_REG_INT_EN 0x51
70 #define BMI160_DRDY_INT_EN BIT(4)
71
72 #define BMI160_REG_INT_OUT_CTRL 0x53
73 #define BMI160_INT_OUT_CTRL_MASK 0x0f
74 #define BMI160_INT1_OUT_CTRL_SHIFT 0
75 #define BMI160_INT2_OUT_CTRL_SHIFT 4
76 #define BMI160_EDGE_TRIGGERED BIT(0)
77 #define BMI160_ACTIVE_HIGH BIT(1)
78 #define BMI160_OPEN_DRAIN BIT(2)
79 #define BMI160_OUTPUT_EN BIT(3)
80
81 #define BMI160_REG_INT_LATCH 0x54
82 #define BMI160_INT1_LATCH_MASK BIT(4)
83 #define BMI160_INT2_LATCH_MASK BIT(5)
84
85 /* INT1 and INT2 are in the opposite order as in INT_OUT_CTRL! */
86 #define BMI160_REG_INT_MAP 0x56
87 #define BMI160_INT1_MAP_DRDY_EN 0x80
88 #define BMI160_INT2_MAP_DRDY_EN 0x08
89
90 #define BMI160_REG_DUMMY 0x7F
91
92 #define BMI160_NORMAL_WRITE_USLEEP 2
93 #define BMI160_SUSPENDED_WRITE_USLEEP 450
94
95 #define BMI160_ACCEL_PMU_MIN_USLEEP 3800
96 #define BMI160_GYRO_PMU_MIN_USLEEP 80000
97 #define BMI160_SOFTRESET_USLEEP 1000
98
99 #define BMI160_CHANNEL(_type, _axis, _index) { \
100 .type = _type, \
101 .modified = 1, \
102 .channel2 = IIO_MOD_##_axis, \
103 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
104 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
105 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
106 .scan_index = _index, \
107 .scan_type = { \
108 .sign = 's', \
109 .realbits = 16, \
110 .storagebits = 16, \
111 .endianness = IIO_LE, \
112 }, \
113 .ext_info = bmi160_ext_info, \
114 }
115
116 /* scan indexes follow DATA register order */
117 enum bmi160_scan_axis {
118 BMI160_SCAN_EXT_MAGN_X = 0,
119 BMI160_SCAN_EXT_MAGN_Y,
120 BMI160_SCAN_EXT_MAGN_Z,
121 BMI160_SCAN_RHALL,
122 BMI160_SCAN_GYRO_X,
123 BMI160_SCAN_GYRO_Y,
124 BMI160_SCAN_GYRO_Z,
125 BMI160_SCAN_ACCEL_X,
126 BMI160_SCAN_ACCEL_Y,
127 BMI160_SCAN_ACCEL_Z,
128 BMI160_SCAN_TIMESTAMP,
129 };
130
131 enum bmi160_sensor_type {
132 BMI160_ACCEL = 0,
133 BMI160_GYRO,
134 BMI160_EXT_MAGN,
135 BMI160_NUM_SENSORS /* must be last */
136 };
137
138 enum bmi160_int_pin {
139 BMI160_PIN_INT1,
140 BMI160_PIN_INT2
141 };
142
143 const struct regmap_config bmi160_regmap_config = {
144 .reg_bits = 8,
145 .val_bits = 8,
146 };
147 EXPORT_SYMBOL(bmi160_regmap_config);
148
149 struct bmi160_regs {
150 u8 data; /* LSB byte register for X-axis */
151 u8 config;
152 u8 config_odr_mask;
153 u8 config_bwp_mask;
154 u8 range;
155 u8 pmu_cmd_normal;
156 u8 pmu_cmd_suspend;
157 };
158
159 static struct bmi160_regs bmi160_regs[] = {
160 [BMI160_ACCEL] = {
161 .data = BMI160_REG_DATA_ACCEL_XOUT_L,
162 .config = BMI160_REG_ACCEL_CONFIG,
163 .config_odr_mask = BMI160_ACCEL_CONFIG_ODR_MASK,
164 .config_bwp_mask = BMI160_ACCEL_CONFIG_BWP_MASK,
165 .range = BMI160_REG_ACCEL_RANGE,
166 .pmu_cmd_normal = BMI160_CMD_ACCEL_PM_NORMAL,
167 .pmu_cmd_suspend = BMI160_CMD_ACCEL_PM_SUSPEND,
168 },
169 [BMI160_GYRO] = {
170 .data = BMI160_REG_DATA_GYRO_XOUT_L,
171 .config = BMI160_REG_GYRO_CONFIG,
172 .config_odr_mask = BMI160_GYRO_CONFIG_ODR_MASK,
173 .config_bwp_mask = BMI160_GYRO_CONFIG_BWP_MASK,
174 .range = BMI160_REG_GYRO_RANGE,
175 .pmu_cmd_normal = BMI160_CMD_GYRO_PM_NORMAL,
176 .pmu_cmd_suspend = BMI160_CMD_GYRO_PM_SUSPEND,
177 },
178 };
179
180 static unsigned long bmi160_pmu_time[] = {
181 [BMI160_ACCEL] = BMI160_ACCEL_PMU_MIN_USLEEP,
182 [BMI160_GYRO] = BMI160_GYRO_PMU_MIN_USLEEP,
183 };
184
185 struct bmi160_scale {
186 u8 bits;
187 int uscale;
188 };
189
190 struct bmi160_odr {
191 u8 bits;
192 int odr;
193 int uodr;
194 };
195
196 static const struct bmi160_scale bmi160_accel_scale[] = {
197 { BMI160_ACCEL_RANGE_2G, 598},
198 { BMI160_ACCEL_RANGE_4G, 1197},
199 { BMI160_ACCEL_RANGE_8G, 2394},
200 { BMI160_ACCEL_RANGE_16G, 4788},
201 };
202
203 static const struct bmi160_scale bmi160_gyro_scale[] = {
204 { BMI160_GYRO_RANGE_2000DPS, 1065},
205 { BMI160_GYRO_RANGE_1000DPS, 532},
206 { BMI160_GYRO_RANGE_500DPS, 266},
207 { BMI160_GYRO_RANGE_250DPS, 133},
208 { BMI160_GYRO_RANGE_125DPS, 66},
209 };
210
211 struct bmi160_scale_item {
212 const struct bmi160_scale *tbl;
213 int num;
214 };
215
216 static const struct bmi160_scale_item bmi160_scale_table[] = {
217 [BMI160_ACCEL] = {
218 .tbl = bmi160_accel_scale,
219 .num = ARRAY_SIZE(bmi160_accel_scale),
220 },
221 [BMI160_GYRO] = {
222 .tbl = bmi160_gyro_scale,
223 .num = ARRAY_SIZE(bmi160_gyro_scale),
224 },
225 };
226
227 static const struct bmi160_odr bmi160_accel_odr[] = {
228 {0x01, 0, 781250},
229 {0x02, 1, 562500},
230 {0x03, 3, 125000},
231 {0x04, 6, 250000},
232 {0x05, 12, 500000},
233 {0x06, 25, 0},
234 {0x07, 50, 0},
235 {0x08, 100, 0},
236 {0x09, 200, 0},
237 {0x0A, 400, 0},
238 {0x0B, 800, 0},
239 {0x0C, 1600, 0},
240 };
241
242 static const struct bmi160_odr bmi160_gyro_odr[] = {
243 {0x06, 25, 0},
244 {0x07, 50, 0},
245 {0x08, 100, 0},
246 {0x09, 200, 0},
247 {0x0A, 400, 0},
248 {0x0B, 800, 0},
249 {0x0C, 1600, 0},
250 {0x0D, 3200, 0},
251 };
252
253 struct bmi160_odr_item {
254 const struct bmi160_odr *tbl;
255 int num;
256 };
257
258 static const struct bmi160_odr_item bmi160_odr_table[] = {
259 [BMI160_ACCEL] = {
260 .tbl = bmi160_accel_odr,
261 .num = ARRAY_SIZE(bmi160_accel_odr),
262 },
263 [BMI160_GYRO] = {
264 .tbl = bmi160_gyro_odr,
265 .num = ARRAY_SIZE(bmi160_gyro_odr),
266 },
267 };
268
269 static const struct iio_mount_matrix *
bmi160_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)270 bmi160_get_mount_matrix(const struct iio_dev *indio_dev,
271 const struct iio_chan_spec *chan)
272 {
273 struct bmi160_data *data = iio_priv(indio_dev);
274
275 return &data->orientation;
276 }
277
278 static const struct iio_chan_spec_ext_info bmi160_ext_info[] = {
279 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmi160_get_mount_matrix),
280 { }
281 };
282
283 static const struct iio_chan_spec bmi160_channels[] = {
284 BMI160_CHANNEL(IIO_ACCEL, X, BMI160_SCAN_ACCEL_X),
285 BMI160_CHANNEL(IIO_ACCEL, Y, BMI160_SCAN_ACCEL_Y),
286 BMI160_CHANNEL(IIO_ACCEL, Z, BMI160_SCAN_ACCEL_Z),
287 BMI160_CHANNEL(IIO_ANGL_VEL, X, BMI160_SCAN_GYRO_X),
288 BMI160_CHANNEL(IIO_ANGL_VEL, Y, BMI160_SCAN_GYRO_Y),
289 BMI160_CHANNEL(IIO_ANGL_VEL, Z, BMI160_SCAN_GYRO_Z),
290 IIO_CHAN_SOFT_TIMESTAMP(BMI160_SCAN_TIMESTAMP),
291 };
292
bmi160_to_sensor(enum iio_chan_type iio_type)293 static enum bmi160_sensor_type bmi160_to_sensor(enum iio_chan_type iio_type)
294 {
295 switch (iio_type) {
296 case IIO_ACCEL:
297 return BMI160_ACCEL;
298 case IIO_ANGL_VEL:
299 return BMI160_GYRO;
300 default:
301 return -EINVAL;
302 }
303 }
304
305 static
bmi160_set_mode(struct bmi160_data * data,enum bmi160_sensor_type t,bool mode)306 int bmi160_set_mode(struct bmi160_data *data, enum bmi160_sensor_type t,
307 bool mode)
308 {
309 int ret;
310 u8 cmd;
311
312 if (mode)
313 cmd = bmi160_regs[t].pmu_cmd_normal;
314 else
315 cmd = bmi160_regs[t].pmu_cmd_suspend;
316
317 ret = regmap_write(data->regmap, BMI160_REG_CMD, cmd);
318 if (ret)
319 return ret;
320
321 usleep_range(bmi160_pmu_time[t], bmi160_pmu_time[t] + 1000);
322
323 return 0;
324 }
325
326 static
bmi160_set_scale(struct bmi160_data * data,enum bmi160_sensor_type t,int uscale)327 int bmi160_set_scale(struct bmi160_data *data, enum bmi160_sensor_type t,
328 int uscale)
329 {
330 int i;
331
332 for (i = 0; i < bmi160_scale_table[t].num; i++)
333 if (bmi160_scale_table[t].tbl[i].uscale == uscale)
334 break;
335
336 if (i == bmi160_scale_table[t].num)
337 return -EINVAL;
338
339 return regmap_write(data->regmap, bmi160_regs[t].range,
340 bmi160_scale_table[t].tbl[i].bits);
341 }
342
343 static
bmi160_get_scale(struct bmi160_data * data,enum bmi160_sensor_type t,int * uscale)344 int bmi160_get_scale(struct bmi160_data *data, enum bmi160_sensor_type t,
345 int *uscale)
346 {
347 int i, ret, val;
348
349 ret = regmap_read(data->regmap, bmi160_regs[t].range, &val);
350 if (ret)
351 return ret;
352
353 for (i = 0; i < bmi160_scale_table[t].num; i++)
354 if (bmi160_scale_table[t].tbl[i].bits == val) {
355 *uscale = bmi160_scale_table[t].tbl[i].uscale;
356 return 0;
357 }
358
359 return -EINVAL;
360 }
361
bmi160_get_data(struct bmi160_data * data,int chan_type,int axis,int * val)362 static int bmi160_get_data(struct bmi160_data *data, int chan_type,
363 int axis, int *val)
364 {
365 u8 reg;
366 int ret;
367 __le16 sample;
368 enum bmi160_sensor_type t = bmi160_to_sensor(chan_type);
369
370 reg = bmi160_regs[t].data + (axis - IIO_MOD_X) * sizeof(sample);
371
372 ret = regmap_bulk_read(data->regmap, reg, &sample, sizeof(sample));
373 if (ret)
374 return ret;
375
376 *val = sign_extend32(le16_to_cpu(sample), 15);
377
378 return 0;
379 }
380
381 static
bmi160_set_odr(struct bmi160_data * data,enum bmi160_sensor_type t,int odr,int uodr)382 int bmi160_set_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
383 int odr, int uodr)
384 {
385 int i;
386
387 for (i = 0; i < bmi160_odr_table[t].num; i++)
388 if (bmi160_odr_table[t].tbl[i].odr == odr &&
389 bmi160_odr_table[t].tbl[i].uodr == uodr)
390 break;
391
392 if (i >= bmi160_odr_table[t].num)
393 return -EINVAL;
394
395 return regmap_update_bits(data->regmap,
396 bmi160_regs[t].config,
397 bmi160_regs[t].config_odr_mask,
398 bmi160_odr_table[t].tbl[i].bits);
399 }
400
bmi160_get_odr(struct bmi160_data * data,enum bmi160_sensor_type t,int * odr,int * uodr)401 static int bmi160_get_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
402 int *odr, int *uodr)
403 {
404 int i, val, ret;
405
406 ret = regmap_read(data->regmap, bmi160_regs[t].config, &val);
407 if (ret)
408 return ret;
409
410 val &= bmi160_regs[t].config_odr_mask;
411
412 for (i = 0; i < bmi160_odr_table[t].num; i++)
413 if (val == bmi160_odr_table[t].tbl[i].bits)
414 break;
415
416 if (i >= bmi160_odr_table[t].num)
417 return -EINVAL;
418
419 *odr = bmi160_odr_table[t].tbl[i].odr;
420 *uodr = bmi160_odr_table[t].tbl[i].uodr;
421
422 return 0;
423 }
424
bmi160_trigger_handler(int irq,void * p)425 static irqreturn_t bmi160_trigger_handler(int irq, void *p)
426 {
427 struct iio_poll_func *pf = p;
428 struct iio_dev *indio_dev = pf->indio_dev;
429 struct bmi160_data *data = iio_priv(indio_dev);
430 __le16 buf[16];
431 /* 3 sens x 3 axis x __le16 + 3 x __le16 pad + 4 x __le16 tstamp */
432 int i, ret, j = 0, base = BMI160_REG_DATA_MAGN_XOUT_L;
433 __le16 sample;
434
435 for_each_set_bit(i, indio_dev->active_scan_mask,
436 indio_dev->masklength) {
437 ret = regmap_bulk_read(data->regmap, base + i * sizeof(sample),
438 &sample, sizeof(sample));
439 if (ret)
440 goto done;
441 buf[j++] = sample;
442 }
443
444 iio_push_to_buffers_with_timestamp(indio_dev, buf, pf->timestamp);
445 done:
446 iio_trigger_notify_done(indio_dev->trig);
447 return IRQ_HANDLED;
448 }
449
bmi160_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)450 static int bmi160_read_raw(struct iio_dev *indio_dev,
451 struct iio_chan_spec const *chan,
452 int *val, int *val2, long mask)
453 {
454 int ret;
455 struct bmi160_data *data = iio_priv(indio_dev);
456
457 switch (mask) {
458 case IIO_CHAN_INFO_RAW:
459 ret = bmi160_get_data(data, chan->type, chan->channel2, val);
460 if (ret)
461 return ret;
462 return IIO_VAL_INT;
463 case IIO_CHAN_INFO_SCALE:
464 *val = 0;
465 ret = bmi160_get_scale(data,
466 bmi160_to_sensor(chan->type), val2);
467 return ret ? ret : IIO_VAL_INT_PLUS_MICRO;
468 case IIO_CHAN_INFO_SAMP_FREQ:
469 ret = bmi160_get_odr(data, bmi160_to_sensor(chan->type),
470 val, val2);
471 return ret ? ret : IIO_VAL_INT_PLUS_MICRO;
472 default:
473 return -EINVAL;
474 }
475
476 return 0;
477 }
478
bmi160_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)479 static int bmi160_write_raw(struct iio_dev *indio_dev,
480 struct iio_chan_spec const *chan,
481 int val, int val2, long mask)
482 {
483 struct bmi160_data *data = iio_priv(indio_dev);
484
485 switch (mask) {
486 case IIO_CHAN_INFO_SCALE:
487 return bmi160_set_scale(data,
488 bmi160_to_sensor(chan->type), val2);
489 break;
490 case IIO_CHAN_INFO_SAMP_FREQ:
491 return bmi160_set_odr(data, bmi160_to_sensor(chan->type),
492 val, val2);
493 default:
494 return -EINVAL;
495 }
496
497 return 0;
498 }
499
500 static
501 IIO_CONST_ATTR(in_accel_sampling_frequency_available,
502 "0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600");
503 static
504 IIO_CONST_ATTR(in_anglvel_sampling_frequency_available,
505 "25 50 100 200 400 800 1600 3200");
506 static
507 IIO_CONST_ATTR(in_accel_scale_available,
508 "0.000598 0.001197 0.002394 0.004788");
509 static
510 IIO_CONST_ATTR(in_anglvel_scale_available,
511 "0.001065 0.000532 0.000266 0.000133 0.000066");
512
513 static struct attribute *bmi160_attrs[] = {
514 &iio_const_attr_in_accel_sampling_frequency_available.dev_attr.attr,
515 &iio_const_attr_in_anglvel_sampling_frequency_available.dev_attr.attr,
516 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
517 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
518 NULL,
519 };
520
521 static const struct attribute_group bmi160_attrs_group = {
522 .attrs = bmi160_attrs,
523 };
524
525 static const struct iio_info bmi160_info = {
526 .read_raw = bmi160_read_raw,
527 .write_raw = bmi160_write_raw,
528 .attrs = &bmi160_attrs_group,
529 };
530
bmi160_match_acpi_device(struct device * dev)531 static const char *bmi160_match_acpi_device(struct device *dev)
532 {
533 const struct acpi_device_id *id;
534
535 id = acpi_match_device(dev->driver->acpi_match_table, dev);
536 if (!id)
537 return NULL;
538
539 return dev_name(dev);
540 }
541
bmi160_write_conf_reg(struct regmap * regmap,unsigned int reg,unsigned int mask,unsigned int bits,unsigned int write_usleep)542 static int bmi160_write_conf_reg(struct regmap *regmap, unsigned int reg,
543 unsigned int mask, unsigned int bits,
544 unsigned int write_usleep)
545 {
546 int ret;
547 unsigned int val;
548
549 ret = regmap_read(regmap, reg, &val);
550 if (ret)
551 return ret;
552
553 val = (val & ~mask) | bits;
554
555 ret = regmap_write(regmap, reg, val);
556 if (ret)
557 return ret;
558
559 /*
560 * We need to wait after writing before we can write again. See the
561 * datasheet, page 93.
562 */
563 usleep_range(write_usleep, write_usleep + 1000);
564
565 return 0;
566 }
567
bmi160_config_pin(struct regmap * regmap,enum bmi160_int_pin pin,bool open_drain,u8 irq_mask,unsigned long write_usleep)568 static int bmi160_config_pin(struct regmap *regmap, enum bmi160_int_pin pin,
569 bool open_drain, u8 irq_mask,
570 unsigned long write_usleep)
571 {
572 int ret;
573 struct device *dev = regmap_get_device(regmap);
574 u8 int_out_ctrl_shift;
575 u8 int_latch_mask;
576 u8 int_map_mask;
577 u8 int_out_ctrl_mask;
578 u8 int_out_ctrl_bits;
579 const char *pin_name;
580
581 switch (pin) {
582 case BMI160_PIN_INT1:
583 int_out_ctrl_shift = BMI160_INT1_OUT_CTRL_SHIFT;
584 int_latch_mask = BMI160_INT1_LATCH_MASK;
585 int_map_mask = BMI160_INT1_MAP_DRDY_EN;
586 break;
587 case BMI160_PIN_INT2:
588 int_out_ctrl_shift = BMI160_INT2_OUT_CTRL_SHIFT;
589 int_latch_mask = BMI160_INT2_LATCH_MASK;
590 int_map_mask = BMI160_INT2_MAP_DRDY_EN;
591 break;
592 }
593 int_out_ctrl_mask = BMI160_INT_OUT_CTRL_MASK << int_out_ctrl_shift;
594
595 /*
596 * Enable the requested pin with the right settings:
597 * - Push-pull/open-drain
598 * - Active low/high
599 * - Edge/level triggered
600 */
601 int_out_ctrl_bits = BMI160_OUTPUT_EN;
602 if (open_drain)
603 /* Default is push-pull. */
604 int_out_ctrl_bits |= BMI160_OPEN_DRAIN;
605 int_out_ctrl_bits |= irq_mask;
606 int_out_ctrl_bits <<= int_out_ctrl_shift;
607
608 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_OUT_CTRL,
609 int_out_ctrl_mask, int_out_ctrl_bits,
610 write_usleep);
611 if (ret)
612 return ret;
613
614 /* Set the pin to input mode with no latching. */
615 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_LATCH,
616 int_latch_mask, int_latch_mask,
617 write_usleep);
618 if (ret)
619 return ret;
620
621 /* Map interrupts to the requested pin. */
622 ret = bmi160_write_conf_reg(regmap, BMI160_REG_INT_MAP,
623 int_map_mask, int_map_mask,
624 write_usleep);
625 if (ret) {
626 switch (pin) {
627 case BMI160_PIN_INT1:
628 pin_name = "INT1";
629 break;
630 case BMI160_PIN_INT2:
631 pin_name = "INT2";
632 break;
633 }
634 dev_err(dev, "Failed to configure %s IRQ pin", pin_name);
635 }
636
637 return ret;
638 }
639
bmi160_enable_irq(struct regmap * regmap,bool enable)640 int bmi160_enable_irq(struct regmap *regmap, bool enable)
641 {
642 unsigned int enable_bit = 0;
643
644 if (enable)
645 enable_bit = BMI160_DRDY_INT_EN;
646
647 return bmi160_write_conf_reg(regmap, BMI160_REG_INT_EN,
648 BMI160_DRDY_INT_EN, enable_bit,
649 BMI160_NORMAL_WRITE_USLEEP);
650 }
651 EXPORT_SYMBOL(bmi160_enable_irq);
652
bmi160_get_irq(struct device_node * of_node,enum bmi160_int_pin * pin)653 static int bmi160_get_irq(struct device_node *of_node, enum bmi160_int_pin *pin)
654 {
655 int irq;
656
657 /* Use INT1 if possible, otherwise fall back to INT2. */
658 irq = of_irq_get_byname(of_node, "INT1");
659 if (irq > 0) {
660 *pin = BMI160_PIN_INT1;
661 return irq;
662 }
663
664 irq = of_irq_get_byname(of_node, "INT2");
665 if (irq > 0)
666 *pin = BMI160_PIN_INT2;
667
668 return irq;
669 }
670
bmi160_config_device_irq(struct iio_dev * indio_dev,int irq_type,enum bmi160_int_pin pin)671 static int bmi160_config_device_irq(struct iio_dev *indio_dev, int irq_type,
672 enum bmi160_int_pin pin)
673 {
674 bool open_drain;
675 u8 irq_mask;
676 struct bmi160_data *data = iio_priv(indio_dev);
677 struct device *dev = regmap_get_device(data->regmap);
678
679 /* Level-triggered, active-low is the default if we set all zeroes. */
680 if (irq_type == IRQF_TRIGGER_RISING)
681 irq_mask = BMI160_ACTIVE_HIGH | BMI160_EDGE_TRIGGERED;
682 else if (irq_type == IRQF_TRIGGER_FALLING)
683 irq_mask = BMI160_EDGE_TRIGGERED;
684 else if (irq_type == IRQF_TRIGGER_HIGH)
685 irq_mask = BMI160_ACTIVE_HIGH;
686 else if (irq_type == IRQF_TRIGGER_LOW)
687 irq_mask = 0;
688 else {
689 dev_err(&indio_dev->dev,
690 "Invalid interrupt type 0x%x specified\n", irq_type);
691 return -EINVAL;
692 }
693
694 open_drain = of_property_read_bool(dev->of_node, "drive-open-drain");
695
696 return bmi160_config_pin(data->regmap, pin, open_drain, irq_mask,
697 BMI160_NORMAL_WRITE_USLEEP);
698 }
699
bmi160_setup_irq(struct iio_dev * indio_dev,int irq,enum bmi160_int_pin pin)700 static int bmi160_setup_irq(struct iio_dev *indio_dev, int irq,
701 enum bmi160_int_pin pin)
702 {
703 struct irq_data *desc;
704 u32 irq_type;
705 int ret;
706
707 desc = irq_get_irq_data(irq);
708 if (!desc) {
709 dev_err(&indio_dev->dev, "Could not find IRQ %d\n", irq);
710 return -EINVAL;
711 }
712
713 irq_type = irqd_get_trigger_type(desc);
714
715 ret = bmi160_config_device_irq(indio_dev, irq_type, pin);
716 if (ret)
717 return ret;
718
719 return bmi160_probe_trigger(indio_dev, irq, irq_type);
720 }
721
bmi160_chip_init(struct bmi160_data * data,bool use_spi)722 static int bmi160_chip_init(struct bmi160_data *data, bool use_spi)
723 {
724 int ret;
725 unsigned int val;
726 struct device *dev = regmap_get_device(data->regmap);
727
728 ret = regulator_bulk_enable(ARRAY_SIZE(data->supplies), data->supplies);
729 if (ret) {
730 dev_err(dev, "Failed to enable regulators: %d\n", ret);
731 return ret;
732 }
733
734 ret = regmap_write(data->regmap, BMI160_REG_CMD, BMI160_CMD_SOFTRESET);
735 if (ret)
736 return ret;
737
738 usleep_range(BMI160_SOFTRESET_USLEEP, BMI160_SOFTRESET_USLEEP + 1);
739
740 /*
741 * CS rising edge is needed before starting SPI, so do a dummy read
742 * See Section 3.2.1, page 86 of the datasheet
743 */
744 if (use_spi) {
745 ret = regmap_read(data->regmap, BMI160_REG_DUMMY, &val);
746 if (ret)
747 return ret;
748 }
749
750 ret = regmap_read(data->regmap, BMI160_REG_CHIP_ID, &val);
751 if (ret) {
752 dev_err(dev, "Error reading chip id\n");
753 return ret;
754 }
755 if (val != BMI160_CHIP_ID_VAL) {
756 dev_err(dev, "Wrong chip id, got %x expected %x\n",
757 val, BMI160_CHIP_ID_VAL);
758 return -ENODEV;
759 }
760
761 ret = bmi160_set_mode(data, BMI160_ACCEL, true);
762 if (ret)
763 return ret;
764
765 ret = bmi160_set_mode(data, BMI160_GYRO, true);
766 if (ret)
767 return ret;
768
769 return 0;
770 }
771
bmi160_data_rdy_trigger_set_state(struct iio_trigger * trig,bool enable)772 static int bmi160_data_rdy_trigger_set_state(struct iio_trigger *trig,
773 bool enable)
774 {
775 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
776 struct bmi160_data *data = iio_priv(indio_dev);
777
778 return bmi160_enable_irq(data->regmap, enable);
779 }
780
781 static const struct iio_trigger_ops bmi160_trigger_ops = {
782 .set_trigger_state = &bmi160_data_rdy_trigger_set_state,
783 };
784
bmi160_probe_trigger(struct iio_dev * indio_dev,int irq,u32 irq_type)785 int bmi160_probe_trigger(struct iio_dev *indio_dev, int irq, u32 irq_type)
786 {
787 struct bmi160_data *data = iio_priv(indio_dev);
788 int ret;
789
790 data->trig = devm_iio_trigger_alloc(&indio_dev->dev, "%s-dev%d",
791 indio_dev->name, indio_dev->id);
792
793 if (data->trig == NULL)
794 return -ENOMEM;
795
796 ret = devm_request_irq(&indio_dev->dev, irq,
797 &iio_trigger_generic_data_rdy_poll,
798 irq_type, "bmi160", data->trig);
799 if (ret)
800 return ret;
801
802 data->trig->dev.parent = regmap_get_device(data->regmap);
803 data->trig->ops = &bmi160_trigger_ops;
804 iio_trigger_set_drvdata(data->trig, indio_dev);
805
806 ret = devm_iio_trigger_register(&indio_dev->dev, data->trig);
807 if (ret)
808 return ret;
809
810 indio_dev->trig = iio_trigger_get(data->trig);
811
812 return 0;
813 }
814
bmi160_chip_uninit(void * data)815 static void bmi160_chip_uninit(void *data)
816 {
817 struct bmi160_data *bmi_data = data;
818 struct device *dev = regmap_get_device(bmi_data->regmap);
819 int ret;
820
821 bmi160_set_mode(bmi_data, BMI160_GYRO, false);
822 bmi160_set_mode(bmi_data, BMI160_ACCEL, false);
823
824 ret = regulator_bulk_disable(ARRAY_SIZE(bmi_data->supplies),
825 bmi_data->supplies);
826 if (ret)
827 dev_err(dev, "Failed to disable regulators: %d\n", ret);
828 }
829
bmi160_core_probe(struct device * dev,struct regmap * regmap,const char * name,bool use_spi)830 int bmi160_core_probe(struct device *dev, struct regmap *regmap,
831 const char *name, bool use_spi)
832 {
833 struct iio_dev *indio_dev;
834 struct bmi160_data *data;
835 int irq;
836 enum bmi160_int_pin int_pin;
837 int ret;
838
839 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
840 if (!indio_dev)
841 return -ENOMEM;
842
843 data = iio_priv(indio_dev);
844 dev_set_drvdata(dev, indio_dev);
845 data->regmap = regmap;
846
847 data->supplies[0].supply = "vdd";
848 data->supplies[1].supply = "vddio";
849 ret = devm_regulator_bulk_get(dev,
850 ARRAY_SIZE(data->supplies),
851 data->supplies);
852 if (ret) {
853 dev_err(dev, "Failed to get regulators: %d\n", ret);
854 return ret;
855 }
856
857 ret = iio_read_mount_matrix(dev, "mount-matrix",
858 &data->orientation);
859 if (ret)
860 return ret;
861
862 ret = bmi160_chip_init(data, use_spi);
863 if (ret)
864 return ret;
865
866 ret = devm_add_action_or_reset(dev, bmi160_chip_uninit, data);
867 if (ret)
868 return ret;
869
870 if (!name && ACPI_HANDLE(dev))
871 name = bmi160_match_acpi_device(dev);
872
873 indio_dev->channels = bmi160_channels;
874 indio_dev->num_channels = ARRAY_SIZE(bmi160_channels);
875 indio_dev->name = name;
876 indio_dev->modes = INDIO_DIRECT_MODE;
877 indio_dev->info = &bmi160_info;
878
879 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
880 iio_pollfunc_store_time,
881 bmi160_trigger_handler, NULL);
882 if (ret)
883 return ret;
884
885 irq = bmi160_get_irq(dev->of_node, &int_pin);
886 if (irq > 0) {
887 ret = bmi160_setup_irq(indio_dev, irq, int_pin);
888 if (ret)
889 dev_err(&indio_dev->dev, "Failed to setup IRQ %d\n",
890 irq);
891 } else {
892 dev_info(&indio_dev->dev, "Not setting up IRQ trigger\n");
893 }
894
895 return devm_iio_device_register(dev, indio_dev);
896 }
897 EXPORT_SYMBOL_GPL(bmi160_core_probe);
898
899 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
900 MODULE_DESCRIPTION("Bosch BMI160 driver");
901 MODULE_LICENSE("GPL v2");
902
