1 // SPDX-License-Identifier: GPL-2.0-only
2 /**
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10
11 #include <linux/i2c.h>
12 #include <linux/time.h>
13 #include <linux/interrupt.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
19 #include <linux/slab.h>
20 #include <linux/io.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/of_irq.h>
24 #include <linux/spinlock.h>
25
26 /*
27 * HSI2C controller from Samsung supports 2 modes of operation
28 * 1. Auto mode: Where in master automatically controls the whole transaction
29 * 2. Manual mode: Software controls the transaction by issuing commands
30 * START, READ, WRITE, STOP, RESTART in I2C_MANUAL_CMD register.
31 *
32 * Operation mode can be selected by setting AUTO_MODE bit in I2C_CONF register
33 *
34 * Special bits are available for both modes of operation to set commands
35 * and for checking transfer status
36 */
37
38 /* Register Map */
39 #define HSI2C_CTL 0x00
40 #define HSI2C_FIFO_CTL 0x04
41 #define HSI2C_TRAILIG_CTL 0x08
42 #define HSI2C_CLK_CTL 0x0C
43 #define HSI2C_CLK_SLOT 0x10
44 #define HSI2C_INT_ENABLE 0x20
45 #define HSI2C_INT_STATUS 0x24
46 #define HSI2C_ERR_STATUS 0x2C
47 #define HSI2C_FIFO_STATUS 0x30
48 #define HSI2C_TX_DATA 0x34
49 #define HSI2C_RX_DATA 0x38
50 #define HSI2C_CONF 0x40
51 #define HSI2C_AUTO_CONF 0x44
52 #define HSI2C_TIMEOUT 0x48
53 #define HSI2C_MANUAL_CMD 0x4C
54 #define HSI2C_TRANS_STATUS 0x50
55 #define HSI2C_TIMING_HS1 0x54
56 #define HSI2C_TIMING_HS2 0x58
57 #define HSI2C_TIMING_HS3 0x5C
58 #define HSI2C_TIMING_FS1 0x60
59 #define HSI2C_TIMING_FS2 0x64
60 #define HSI2C_TIMING_FS3 0x68
61 #define HSI2C_TIMING_SLA 0x6C
62 #define HSI2C_ADDR 0x70
63
64 /* I2C_CTL Register bits */
65 #define HSI2C_FUNC_MODE_I2C (1u << 0)
66 #define HSI2C_MASTER (1u << 3)
67 #define HSI2C_RXCHON (1u << 6)
68 #define HSI2C_TXCHON (1u << 7)
69 #define HSI2C_SW_RST (1u << 31)
70
71 /* I2C_FIFO_CTL Register bits */
72 #define HSI2C_RXFIFO_EN (1u << 0)
73 #define HSI2C_TXFIFO_EN (1u << 1)
74 #define HSI2C_RXFIFO_TRIGGER_LEVEL(x) ((x) << 4)
75 #define HSI2C_TXFIFO_TRIGGER_LEVEL(x) ((x) << 16)
76
77 /* I2C_TRAILING_CTL Register bits */
78 #define HSI2C_TRAILING_COUNT (0xf)
79
80 /* I2C_INT_EN Register bits */
81 #define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
82 #define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
83 #define HSI2C_INT_TRAILING_EN (1u << 6)
84
85 /* I2C_INT_STAT Register bits */
86 #define HSI2C_INT_TX_ALMOSTEMPTY (1u << 0)
87 #define HSI2C_INT_RX_ALMOSTFULL (1u << 1)
88 #define HSI2C_INT_TX_UNDERRUN (1u << 2)
89 #define HSI2C_INT_TX_OVERRUN (1u << 3)
90 #define HSI2C_INT_RX_UNDERRUN (1u << 4)
91 #define HSI2C_INT_RX_OVERRUN (1u << 5)
92 #define HSI2C_INT_TRAILING (1u << 6)
93 #define HSI2C_INT_I2C (1u << 9)
94
95 #define HSI2C_INT_TRANS_DONE (1u << 7)
96 #define HSI2C_INT_TRANS_ABORT (1u << 8)
97 #define HSI2C_INT_NO_DEV_ACK (1u << 9)
98 #define HSI2C_INT_NO_DEV (1u << 10)
99 #define HSI2C_INT_TIMEOUT (1u << 11)
100 #define HSI2C_INT_I2C_TRANS (HSI2C_INT_TRANS_DONE | \
101 HSI2C_INT_TRANS_ABORT | \
102 HSI2C_INT_NO_DEV_ACK | \
103 HSI2C_INT_NO_DEV | \
104 HSI2C_INT_TIMEOUT)
105
106 /* I2C_FIFO_STAT Register bits */
107 #define HSI2C_RX_FIFO_EMPTY (1u << 24)
108 #define HSI2C_RX_FIFO_FULL (1u << 23)
109 #define HSI2C_RX_FIFO_LVL(x) ((x >> 16) & 0x7f)
110 #define HSI2C_TX_FIFO_EMPTY (1u << 8)
111 #define HSI2C_TX_FIFO_FULL (1u << 7)
112 #define HSI2C_TX_FIFO_LVL(x) ((x >> 0) & 0x7f)
113
114 /* I2C_CONF Register bits */
115 #define HSI2C_AUTO_MODE (1u << 31)
116 #define HSI2C_10BIT_ADDR_MODE (1u << 30)
117 #define HSI2C_HS_MODE (1u << 29)
118
119 /* I2C_AUTO_CONF Register bits */
120 #define HSI2C_READ_WRITE (1u << 16)
121 #define HSI2C_STOP_AFTER_TRANS (1u << 17)
122 #define HSI2C_MASTER_RUN (1u << 31)
123
124 /* I2C_TIMEOUT Register bits */
125 #define HSI2C_TIMEOUT_EN (1u << 31)
126 #define HSI2C_TIMEOUT_MASK 0xff
127
128 /* I2C_MANUAL_CMD register bits */
129 #define HSI2C_CMD_READ_DATA (1u << 4)
130 #define HSI2C_CMD_SEND_STOP (1u << 2)
131
132 /* I2C_TRANS_STATUS register bits */
133 #define HSI2C_MASTER_BUSY (1u << 17)
134 #define HSI2C_SLAVE_BUSY (1u << 16)
135
136 /* I2C_TRANS_STATUS register bits for Exynos5 variant */
137 #define HSI2C_TIMEOUT_AUTO (1u << 4)
138 #define HSI2C_NO_DEV (1u << 3)
139 #define HSI2C_NO_DEV_ACK (1u << 2)
140 #define HSI2C_TRANS_ABORT (1u << 1)
141 #define HSI2C_TRANS_DONE (1u << 0)
142
143 /* I2C_TRANS_STATUS register bits for Exynos7 variant */
144 #define HSI2C_MASTER_ST_MASK 0xf
145 #define HSI2C_MASTER_ST_IDLE 0x0
146 #define HSI2C_MASTER_ST_START 0x1
147 #define HSI2C_MASTER_ST_RESTART 0x2
148 #define HSI2C_MASTER_ST_STOP 0x3
149 #define HSI2C_MASTER_ST_MASTER_ID 0x4
150 #define HSI2C_MASTER_ST_ADDR0 0x5
151 #define HSI2C_MASTER_ST_ADDR1 0x6
152 #define HSI2C_MASTER_ST_ADDR2 0x7
153 #define HSI2C_MASTER_ST_ADDR_SR 0x8
154 #define HSI2C_MASTER_ST_READ 0x9
155 #define HSI2C_MASTER_ST_WRITE 0xa
156 #define HSI2C_MASTER_ST_NO_ACK 0xb
157 #define HSI2C_MASTER_ST_LOSE 0xc
158 #define HSI2C_MASTER_ST_WAIT 0xd
159 #define HSI2C_MASTER_ST_WAIT_CMD 0xe
160
161 /* I2C_ADDR register bits */
162 #define HSI2C_SLV_ADDR_SLV(x) ((x & 0x3ff) << 0)
163 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
164 #define HSI2C_MASTER_ID(x) ((x & 0xff) << 24)
165 #define MASTER_ID(x) ((x & 0x7) + 0x08)
166
167 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
168
169 enum i2c_type_exynos {
170 I2C_TYPE_EXYNOS5,
171 I2C_TYPE_EXYNOS7,
172 };
173
174 struct exynos5_i2c {
175 struct i2c_adapter adap;
176
177 struct i2c_msg *msg;
178 struct completion msg_complete;
179 unsigned int msg_ptr;
180
181 unsigned int irq;
182
183 void __iomem *regs;
184 struct clk *clk;
185 struct device *dev;
186 int state;
187
188 spinlock_t lock; /* IRQ synchronization */
189
190 /*
191 * Since the TRANS_DONE bit is cleared on read, and we may read it
192 * either during an IRQ or after a transaction, keep track of its
193 * state here.
194 */
195 int trans_done;
196
197 /* Controller operating frequency */
198 unsigned int op_clock;
199
200 /* Version of HS-I2C Hardware */
201 const struct exynos_hsi2c_variant *variant;
202 };
203
204 /**
205 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
206 * @fifo_depth: the fifo depth supported by the HSI2C module
207 * @hw: the hardware variant of Exynos I2C controller
208 *
209 * Specifies platform specific configuration of HSI2C module.
210 * Note: A structure for driver specific platform data is used for future
211 * expansion of its usage.
212 */
213 struct exynos_hsi2c_variant {
214 unsigned int fifo_depth;
215 enum i2c_type_exynos hw;
216 };
217
218 static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
219 .fifo_depth = 64,
220 .hw = I2C_TYPE_EXYNOS5,
221 };
222
223 static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
224 .fifo_depth = 16,
225 .hw = I2C_TYPE_EXYNOS5,
226 };
227
228 static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
229 .fifo_depth = 16,
230 .hw = I2C_TYPE_EXYNOS7,
231 };
232
233 static const struct of_device_id exynos5_i2c_match[] = {
234 {
235 .compatible = "samsung,exynos5-hsi2c",
236 .data = &exynos5250_hsi2c_data
237 }, {
238 .compatible = "samsung,exynos5250-hsi2c",
239 .data = &exynos5250_hsi2c_data
240 }, {
241 .compatible = "samsung,exynos5260-hsi2c",
242 .data = &exynos5260_hsi2c_data
243 }, {
244 .compatible = "samsung,exynos7-hsi2c",
245 .data = &exynos7_hsi2c_data
246 }, {},
247 };
248 MODULE_DEVICE_TABLE(of, exynos5_i2c_match);
249
exynos5_i2c_clr_pend_irq(struct exynos5_i2c * i2c)250 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
251 {
252 writel(readl(i2c->regs + HSI2C_INT_STATUS),
253 i2c->regs + HSI2C_INT_STATUS);
254 }
255
256 /*
257 * exynos5_i2c_set_timing: updates the registers with appropriate
258 * timing values calculated
259 *
260 * Timing values for operation are calculated against either 100kHz
261 * or 1MHz controller operating frequency.
262 *
263 * Returns 0 on success, -EINVAL if the cycle length cannot
264 * be calculated.
265 */
exynos5_i2c_set_timing(struct exynos5_i2c * i2c,bool hs_timings)266 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
267 {
268 u32 i2c_timing_s1;
269 u32 i2c_timing_s2;
270 u32 i2c_timing_s3;
271 u32 i2c_timing_sla;
272 unsigned int t_start_su, t_start_hd;
273 unsigned int t_stop_su;
274 unsigned int t_data_su, t_data_hd;
275 unsigned int t_scl_l, t_scl_h;
276 unsigned int t_sr_release;
277 unsigned int t_ftl_cycle;
278 unsigned int clkin = clk_get_rate(i2c->clk);
279 unsigned int op_clk = hs_timings ? i2c->op_clock :
280 (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ :
281 i2c->op_clock;
282 int div, clk_cycle, temp;
283
284 /*
285 * In case of HSI2C controller in Exynos5 series
286 * FPCLK / FI2C =
287 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
288 *
289 * In case of HSI2C controllers in Exynos7 series
290 * FPCLK / FI2C =
291 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
292 *
293 * clk_cycle := TSCLK_L + TSCLK_H
294 * temp := (CLK_DIV + 1) * (clk_cycle + 2)
295 *
296 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
297 *
298 */
299 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
300 temp = clkin / op_clk - 8 - t_ftl_cycle;
301 if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
302 temp -= t_ftl_cycle;
303 div = temp / 512;
304 clk_cycle = temp / (div + 1) - 2;
305 if (temp < 4 || div >= 256 || clk_cycle < 2) {
306 dev_err(i2c->dev, "%s clock set-up failed\n",
307 hs_timings ? "HS" : "FS");
308 return -EINVAL;
309 }
310
311 t_scl_l = clk_cycle / 2;
312 t_scl_h = clk_cycle / 2;
313 t_start_su = t_scl_l;
314 t_start_hd = t_scl_l;
315 t_stop_su = t_scl_l;
316 t_data_su = t_scl_l / 2;
317 t_data_hd = t_scl_l / 2;
318 t_sr_release = clk_cycle;
319
320 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
321 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
322 i2c_timing_s3 = div << 16 | t_sr_release << 0;
323 i2c_timing_sla = t_data_hd << 0;
324
325 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n",
326 t_start_su, t_start_hd, t_stop_su);
327 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n",
328 t_data_su, t_scl_l, t_scl_h);
329 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n",
330 div, t_sr_release);
331 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
332
333 if (hs_timings) {
334 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
335 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
336 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
337 } else {
338 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1);
339 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2);
340 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3);
341 }
342 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA);
343
344 return 0;
345 }
346
exynos5_hsi2c_clock_setup(struct exynos5_i2c * i2c)347 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
348 {
349 /* always set Fast Speed timings */
350 int ret = exynos5_i2c_set_timing(i2c, false);
351
352 if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ)
353 return ret;
354
355 return exynos5_i2c_set_timing(i2c, true);
356 }
357
358 /*
359 * exynos5_i2c_init: configures the controller for I2C functionality
360 * Programs I2C controller for Master mode operation
361 */
exynos5_i2c_init(struct exynos5_i2c * i2c)362 static void exynos5_i2c_init(struct exynos5_i2c *i2c)
363 {
364 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF);
365 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT);
366
367 /* Clear to disable Timeout */
368 i2c_timeout &= ~HSI2C_TIMEOUT_EN;
369 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT);
370
371 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
372 i2c->regs + HSI2C_CTL);
373 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
374
375 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) {
376 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
377 i2c->regs + HSI2C_ADDR);
378 i2c_conf |= HSI2C_HS_MODE;
379 }
380
381 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF);
382 }
383
exynos5_i2c_reset(struct exynos5_i2c * i2c)384 static void exynos5_i2c_reset(struct exynos5_i2c *i2c)
385 {
386 u32 i2c_ctl;
387
388 /* Set and clear the bit for reset */
389 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
390 i2c_ctl |= HSI2C_SW_RST;
391 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
392
393 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
394 i2c_ctl &= ~HSI2C_SW_RST;
395 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
396
397 /* We don't expect calculations to fail during the run */
398 exynos5_hsi2c_clock_setup(i2c);
399 /* Initialize the configure registers */
400 exynos5_i2c_init(i2c);
401 }
402
403 /*
404 * exynos5_i2c_irq: top level IRQ servicing routine
405 *
406 * INT_STATUS registers gives the interrupt details. Further,
407 * FIFO_STATUS or TRANS_STATUS registers are to be check for detailed
408 * state of the bus.
409 */
exynos5_i2c_irq(int irqno,void * dev_id)410 static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
411 {
412 struct exynos5_i2c *i2c = dev_id;
413 u32 fifo_level, int_status, fifo_status, trans_status;
414 unsigned char byte;
415 int len = 0;
416
417 i2c->state = -EINVAL;
418
419 spin_lock(&i2c->lock);
420
421 int_status = readl(i2c->regs + HSI2C_INT_STATUS);
422 writel(int_status, i2c->regs + HSI2C_INT_STATUS);
423
424 /* handle interrupt related to the transfer status */
425 if (i2c->variant->hw == I2C_TYPE_EXYNOS7) {
426 if (int_status & HSI2C_INT_TRANS_DONE) {
427 i2c->trans_done = 1;
428 i2c->state = 0;
429 } else if (int_status & HSI2C_INT_TRANS_ABORT) {
430 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
431 i2c->state = -EAGAIN;
432 goto stop;
433 } else if (int_status & HSI2C_INT_NO_DEV_ACK) {
434 dev_dbg(i2c->dev, "No ACK from device\n");
435 i2c->state = -ENXIO;
436 goto stop;
437 } else if (int_status & HSI2C_INT_NO_DEV) {
438 dev_dbg(i2c->dev, "No device\n");
439 i2c->state = -ENXIO;
440 goto stop;
441 } else if (int_status & HSI2C_INT_TIMEOUT) {
442 dev_dbg(i2c->dev, "Accessing device timed out\n");
443 i2c->state = -ETIMEDOUT;
444 goto stop;
445 }
446 } else if (int_status & HSI2C_INT_I2C) {
447 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
448 if (trans_status & HSI2C_NO_DEV_ACK) {
449 dev_dbg(i2c->dev, "No ACK from device\n");
450 i2c->state = -ENXIO;
451 goto stop;
452 } else if (trans_status & HSI2C_NO_DEV) {
453 dev_dbg(i2c->dev, "No device\n");
454 i2c->state = -ENXIO;
455 goto stop;
456 } else if (trans_status & HSI2C_TRANS_ABORT) {
457 dev_dbg(i2c->dev, "Deal with arbitration lose\n");
458 i2c->state = -EAGAIN;
459 goto stop;
460 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
461 dev_dbg(i2c->dev, "Accessing device timed out\n");
462 i2c->state = -ETIMEDOUT;
463 goto stop;
464 } else if (trans_status & HSI2C_TRANS_DONE) {
465 i2c->trans_done = 1;
466 i2c->state = 0;
467 }
468 }
469
470 if ((i2c->msg->flags & I2C_M_RD) && (int_status &
471 (HSI2C_INT_TRAILING | HSI2C_INT_RX_ALMOSTFULL))) {
472 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
473 fifo_level = HSI2C_RX_FIFO_LVL(fifo_status);
474 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr);
475
476 while (len > 0) {
477 byte = (unsigned char)
478 readl(i2c->regs + HSI2C_RX_DATA);
479 i2c->msg->buf[i2c->msg_ptr++] = byte;
480 len--;
481 }
482 i2c->state = 0;
483 } else if (int_status & HSI2C_INT_TX_ALMOSTEMPTY) {
484 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS);
485 fifo_level = HSI2C_TX_FIFO_LVL(fifo_status);
486
487 len = i2c->variant->fifo_depth - fifo_level;
488 if (len > (i2c->msg->len - i2c->msg_ptr)) {
489 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE);
490
491 int_en &= ~HSI2C_INT_TX_ALMOSTEMPTY_EN;
492 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
493 len = i2c->msg->len - i2c->msg_ptr;
494 }
495
496 while (len > 0) {
497 byte = i2c->msg->buf[i2c->msg_ptr++];
498 writel(byte, i2c->regs + HSI2C_TX_DATA);
499 len--;
500 }
501 i2c->state = 0;
502 }
503
504 stop:
505 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) ||
506 (i2c->state < 0)) {
507 writel(0, i2c->regs + HSI2C_INT_ENABLE);
508 exynos5_i2c_clr_pend_irq(i2c);
509 complete(&i2c->msg_complete);
510 }
511
512 spin_unlock(&i2c->lock);
513
514 return IRQ_HANDLED;
515 }
516
517 /*
518 * exynos5_i2c_wait_bus_idle
519 *
520 * Wait for the bus to go idle, indicated by the MASTER_BUSY bit being
521 * cleared.
522 *
523 * Returns -EBUSY if the bus cannot be bought to idle
524 */
exynos5_i2c_wait_bus_idle(struct exynos5_i2c * i2c)525 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c)
526 {
527 unsigned long stop_time;
528 u32 trans_status;
529
530 /* wait for 100 milli seconds for the bus to be idle */
531 stop_time = jiffies + msecs_to_jiffies(100) + 1;
532 do {
533 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS);
534 if (!(trans_status & HSI2C_MASTER_BUSY))
535 return 0;
536
537 usleep_range(50, 200);
538 } while (time_before(jiffies, stop_time));
539
540 return -EBUSY;
541 }
542
exynos5_i2c_bus_recover(struct exynos5_i2c * i2c)543 static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c)
544 {
545 u32 val;
546
547 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON;
548 writel(val, i2c->regs + HSI2C_CTL);
549 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE;
550 writel(val, i2c->regs + HSI2C_CONF);
551
552 /*
553 * Specification says master should send nine clock pulses. It can be
554 * emulated by sending manual read command (nine pulses for read eight
555 * bits + one pulse for NACK).
556 */
557 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD);
558 exynos5_i2c_wait_bus_idle(i2c);
559 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD);
560 exynos5_i2c_wait_bus_idle(i2c);
561
562 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON;
563 writel(val, i2c->regs + HSI2C_CTL);
564 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE;
565 writel(val, i2c->regs + HSI2C_CONF);
566 }
567
exynos5_i2c_bus_check(struct exynos5_i2c * i2c)568 static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
569 {
570 unsigned long timeout;
571
572 if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
573 return;
574
575 /*
576 * HSI2C_MASTER_ST_LOSE state in EXYNOS7 variant before transaction
577 * indicates that bus is stuck (SDA is low). In such case bus recovery
578 * can be performed.
579 */
580 timeout = jiffies + msecs_to_jiffies(100);
581 for (;;) {
582 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS);
583
584 if ((st & HSI2C_MASTER_ST_MASK) != HSI2C_MASTER_ST_LOSE)
585 return;
586
587 if (time_is_before_jiffies(timeout))
588 return;
589
590 exynos5_i2c_bus_recover(i2c);
591 }
592 }
593
594 /*
595 * exynos5_i2c_message_start: Configures the bus and starts the xfer
596 * i2c: struct exynos5_i2c pointer for the current bus
597 * stop: Enables stop after transfer if set. Set for last transfer of
598 * in the list of messages.
599 *
600 * Configures the bus for read/write function
601 * Sets chip address to talk to, message length to be sent.
602 * Enables appropriate interrupts and sends start xfer command.
603 */
exynos5_i2c_message_start(struct exynos5_i2c * i2c,int stop)604 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
605 {
606 u32 i2c_ctl;
607 u32 int_en = 0;
608 u32 i2c_auto_conf = 0;
609 u32 fifo_ctl;
610 unsigned long flags;
611 unsigned short trig_lvl;
612
613 if (i2c->variant->hw == I2C_TYPE_EXYNOS7)
614 int_en |= HSI2C_INT_I2C_TRANS;
615 else
616 int_en |= HSI2C_INT_I2C;
617
618 i2c_ctl = readl(i2c->regs + HSI2C_CTL);
619 i2c_ctl &= ~(HSI2C_TXCHON | HSI2C_RXCHON);
620 fifo_ctl = HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN;
621
622 if (i2c->msg->flags & I2C_M_RD) {
623 i2c_ctl |= HSI2C_RXCHON;
624
625 i2c_auto_conf |= HSI2C_READ_WRITE;
626
627 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
628 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len;
629 fifo_ctl |= HSI2C_RXFIFO_TRIGGER_LEVEL(trig_lvl);
630
631 int_en |= (HSI2C_INT_RX_ALMOSTFULL_EN |
632 HSI2C_INT_TRAILING_EN);
633 } else {
634 i2c_ctl |= HSI2C_TXCHON;
635
636 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ?
637 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len;
638 fifo_ctl |= HSI2C_TXFIFO_TRIGGER_LEVEL(trig_lvl);
639
640 int_en |= HSI2C_INT_TX_ALMOSTEMPTY_EN;
641 }
642
643 writel(HSI2C_SLV_ADDR_MAS(i2c->msg->addr), i2c->regs + HSI2C_ADDR);
644
645 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL);
646 writel(i2c_ctl, i2c->regs + HSI2C_CTL);
647
648 exynos5_i2c_bus_check(i2c);
649
650 /*
651 * Enable interrupts before starting the transfer so that we don't
652 * miss any INT_I2C interrupts.
653 */
654 spin_lock_irqsave(&i2c->lock, flags);
655 writel(int_en, i2c->regs + HSI2C_INT_ENABLE);
656
657 if (stop == 1)
658 i2c_auto_conf |= HSI2C_STOP_AFTER_TRANS;
659 i2c_auto_conf |= i2c->msg->len;
660 i2c_auto_conf |= HSI2C_MASTER_RUN;
661 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF);
662 spin_unlock_irqrestore(&i2c->lock, flags);
663 }
664
exynos5_i2c_xfer_msg(struct exynos5_i2c * i2c,struct i2c_msg * msgs,int stop)665 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c,
666 struct i2c_msg *msgs, int stop)
667 {
668 unsigned long timeout;
669 int ret;
670
671 i2c->msg = msgs;
672 i2c->msg_ptr = 0;
673 i2c->trans_done = 0;
674
675 reinit_completion(&i2c->msg_complete);
676
677 exynos5_i2c_message_start(i2c, stop);
678
679 timeout = wait_for_completion_timeout(&i2c->msg_complete,
680 EXYNOS5_I2C_TIMEOUT);
681 if (timeout == 0)
682 ret = -ETIMEDOUT;
683 else
684 ret = i2c->state;
685
686 /*
687 * If this is the last message to be transfered (stop == 1)
688 * Then check if the bus can be brought back to idle.
689 */
690 if (ret == 0 && stop)
691 ret = exynos5_i2c_wait_bus_idle(i2c);
692
693 if (ret < 0) {
694 exynos5_i2c_reset(i2c);
695 if (ret == -ETIMEDOUT)
696 dev_warn(i2c->dev, "%s timeout\n",
697 (msgs->flags & I2C_M_RD) ? "rx" : "tx");
698 }
699
700 /* Return the state as in interrupt routine */
701 return ret;
702 }
703
exynos5_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)704 static int exynos5_i2c_xfer(struct i2c_adapter *adap,
705 struct i2c_msg *msgs, int num)
706 {
707 struct exynos5_i2c *i2c = adap->algo_data;
708 int i, ret;
709
710 ret = clk_enable(i2c->clk);
711 if (ret)
712 return ret;
713
714 for (i = 0; i < num; ++i) {
715 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num);
716 if (ret)
717 break;
718 }
719
720 clk_disable(i2c->clk);
721
722 return ret ?: num;
723 }
724
exynos5_i2c_func(struct i2c_adapter * adap)725 static u32 exynos5_i2c_func(struct i2c_adapter *adap)
726 {
727 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
728 }
729
730 static const struct i2c_algorithm exynos5_i2c_algorithm = {
731 .master_xfer = exynos5_i2c_xfer,
732 .functionality = exynos5_i2c_func,
733 };
734
exynos5_i2c_probe(struct platform_device * pdev)735 static int exynos5_i2c_probe(struct platform_device *pdev)
736 {
737 struct device_node *np = pdev->dev.of_node;
738 struct exynos5_i2c *i2c;
739 int ret;
740
741 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
742 if (!i2c)
743 return -ENOMEM;
744
745 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
746 i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ;
747
748 strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
749 i2c->adap.owner = THIS_MODULE;
750 i2c->adap.algo = &exynos5_i2c_algorithm;
751 i2c->adap.retries = 3;
752
753 i2c->dev = &pdev->dev;
754 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c");
755 if (IS_ERR(i2c->clk)) {
756 dev_err(&pdev->dev, "cannot get clock\n");
757 return -ENOENT;
758 }
759
760 ret = clk_prepare_enable(i2c->clk);
761 if (ret)
762 return ret;
763
764 i2c->regs = devm_platform_ioremap_resource(pdev, 0);
765 if (IS_ERR(i2c->regs)) {
766 ret = PTR_ERR(i2c->regs);
767 goto err_clk;
768 }
769
770 i2c->adap.dev.of_node = np;
771 i2c->adap.algo_data = i2c;
772 i2c->adap.dev.parent = &pdev->dev;
773
774 /* Clear pending interrupts from u-boot or misc causes */
775 exynos5_i2c_clr_pend_irq(i2c);
776
777 spin_lock_init(&i2c->lock);
778 init_completion(&i2c->msg_complete);
779
780 i2c->irq = ret = platform_get_irq(pdev, 0);
781 if (ret <= 0) {
782 dev_err(&pdev->dev, "cannot find HS-I2C IRQ\n");
783 ret = -EINVAL;
784 goto err_clk;
785 }
786
787 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq,
788 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c);
789 if (ret != 0) {
790 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq);
791 goto err_clk;
792 }
793
794 i2c->variant = of_device_get_match_data(&pdev->dev);
795
796 ret = exynos5_hsi2c_clock_setup(i2c);
797 if (ret)
798 goto err_clk;
799
800 exynos5_i2c_reset(i2c);
801
802 ret = i2c_add_adapter(&i2c->adap);
803 if (ret < 0)
804 goto err_clk;
805
806 platform_set_drvdata(pdev, i2c);
807
808 clk_disable(i2c->clk);
809
810 return 0;
811
812 err_clk:
813 clk_disable_unprepare(i2c->clk);
814 return ret;
815 }
816
exynos5_i2c_remove(struct platform_device * pdev)817 static int exynos5_i2c_remove(struct platform_device *pdev)
818 {
819 struct exynos5_i2c *i2c = platform_get_drvdata(pdev);
820
821 i2c_del_adapter(&i2c->adap);
822
823 clk_unprepare(i2c->clk);
824
825 return 0;
826 }
827
828 #ifdef CONFIG_PM_SLEEP
exynos5_i2c_suspend_noirq(struct device * dev)829 static int exynos5_i2c_suspend_noirq(struct device *dev)
830 {
831 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
832
833 i2c_mark_adapter_suspended(&i2c->adap);
834 clk_unprepare(i2c->clk);
835
836 return 0;
837 }
838
exynos5_i2c_resume_noirq(struct device * dev)839 static int exynos5_i2c_resume_noirq(struct device *dev)
840 {
841 struct exynos5_i2c *i2c = dev_get_drvdata(dev);
842 int ret = 0;
843
844 ret = clk_prepare_enable(i2c->clk);
845 if (ret)
846 return ret;
847
848 ret = exynos5_hsi2c_clock_setup(i2c);
849 if (ret) {
850 clk_disable_unprepare(i2c->clk);
851 return ret;
852 }
853
854 exynos5_i2c_init(i2c);
855 clk_disable(i2c->clk);
856 i2c_mark_adapter_resumed(&i2c->adap);
857
858 return 0;
859 }
860 #endif
861
862 static const struct dev_pm_ops exynos5_i2c_dev_pm_ops = {
863 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(exynos5_i2c_suspend_noirq,
864 exynos5_i2c_resume_noirq)
865 };
866
867 static struct platform_driver exynos5_i2c_driver = {
868 .probe = exynos5_i2c_probe,
869 .remove = exynos5_i2c_remove,
870 .driver = {
871 .name = "exynos5-hsi2c",
872 .pm = &exynos5_i2c_dev_pm_ops,
873 .of_match_table = exynos5_i2c_match,
874 },
875 };
876
877 module_platform_driver(exynos5_i2c_driver);
878
879 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");
880 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
881 MODULE_AUTHOR("Taekgyun Ko <taeggyun.ko@samsung.com>");
882 MODULE_LICENSE("GPL v2");
883
