1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2014
4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/debugfs.h>
10 #include <linux/module.h>
11 #include <linux/of_gpio.h>
12 #include <linux/platform_device.h>
13
14 #include <drm/drm_atomic_helper.h>
15 #include <drm/drm_bridge.h>
16 #include <drm/drm_device.h>
17 #include <drm/drm_panel.h>
18 #include <drm/drm_print.h>
19 #include <drm/drm_probe_helper.h>
20
21 #include "sti_awg_utils.h"
22 #include "sti_drv.h"
23 #include "sti_mixer.h"
24
25 /* DVO registers */
26 #define DVO_AWG_DIGSYNC_CTRL 0x0000
27 #define DVO_DOF_CFG 0x0004
28 #define DVO_LUT_PROG_LOW 0x0008
29 #define DVO_LUT_PROG_MID 0x000C
30 #define DVO_LUT_PROG_HIGH 0x0010
31 #define DVO_DIGSYNC_INSTR_I 0x0100
32
33 #define DVO_AWG_CTRL_EN BIT(0)
34 #define DVO_AWG_FRAME_BASED_SYNC BIT(2)
35
36 #define DVO_DOF_EN_LOWBYTE BIT(0)
37 #define DVO_DOF_EN_MIDBYTE BIT(1)
38 #define DVO_DOF_EN_HIGHBYTE BIT(2)
39 #define DVO_DOF_EN BIT(6)
40 #define DVO_DOF_MOD_COUNT_SHIFT 8
41
42 #define DVO_LUT_ZERO 0
43 #define DVO_LUT_Y_G 1
44 #define DVO_LUT_Y_G_DEL 2
45 #define DVO_LUT_CB_B 3
46 #define DVO_LUT_CB_B_DEL 4
47 #define DVO_LUT_CR_R 5
48 #define DVO_LUT_CR_R_DEL 6
49 #define DVO_LUT_HOLD 7
50
51 struct dvo_config {
52 u32 flags;
53 u32 lowbyte;
54 u32 midbyte;
55 u32 highbyte;
56 int (*awg_fwgen_fct)(
57 struct awg_code_generation_params *fw_gen_params,
58 struct awg_timing *timing);
59 };
60
61 static struct dvo_config rgb_24bit_de_cfg = {
62 .flags = (0L << DVO_DOF_MOD_COUNT_SHIFT),
63 .lowbyte = DVO_LUT_CR_R,
64 .midbyte = DVO_LUT_Y_G,
65 .highbyte = DVO_LUT_CB_B,
66 .awg_fwgen_fct = sti_awg_generate_code_data_enable_mode,
67 };
68
69 /*
70 * STI digital video output structure
71 *
72 * @dev: driver device
73 * @drm_dev: pointer to drm device
74 * @mode: current display mode selected
75 * @regs: dvo registers
76 * @clk_pix: pixel clock for dvo
77 * @clk: clock for dvo
78 * @clk_main_parent: dvo parent clock if main path used
79 * @clk_aux_parent: dvo parent clock if aux path used
80 * @panel_node: panel node reference from device tree
81 * @panel: reference to the panel connected to the dvo
82 * @enabled: true if dvo is enabled else false
83 * @encoder: drm_encoder it is bound
84 */
85 struct sti_dvo {
86 struct device dev;
87 struct drm_device *drm_dev;
88 struct drm_display_mode mode;
89 void __iomem *regs;
90 struct clk *clk_pix;
91 struct clk *clk;
92 struct clk *clk_main_parent;
93 struct clk *clk_aux_parent;
94 struct device_node *panel_node;
95 struct drm_panel *panel;
96 struct dvo_config *config;
97 bool enabled;
98 struct drm_encoder *encoder;
99 struct drm_bridge *bridge;
100 };
101
102 struct sti_dvo_connector {
103 struct drm_connector drm_connector;
104 struct drm_encoder *encoder;
105 struct sti_dvo *dvo;
106 };
107
108 #define to_sti_dvo_connector(x) \
109 container_of(x, struct sti_dvo_connector, drm_connector)
110
111 #define BLANKING_LEVEL 16
dvo_awg_generate_code(struct sti_dvo * dvo,u8 * ram_size,u32 * ram_code)112 static int dvo_awg_generate_code(struct sti_dvo *dvo, u8 *ram_size, u32 *ram_code)
113 {
114 struct drm_display_mode *mode = &dvo->mode;
115 struct dvo_config *config = dvo->config;
116 struct awg_code_generation_params fw_gen_params;
117 struct awg_timing timing;
118
119 fw_gen_params.ram_code = ram_code;
120 fw_gen_params.instruction_offset = 0;
121
122 timing.total_lines = mode->vtotal;
123 timing.active_lines = mode->vdisplay;
124 timing.blanking_lines = mode->vsync_start - mode->vdisplay;
125 timing.trailing_lines = mode->vtotal - mode->vsync_start;
126 timing.total_pixels = mode->htotal;
127 timing.active_pixels = mode->hdisplay;
128 timing.blanking_pixels = mode->hsync_start - mode->hdisplay;
129 timing.trailing_pixels = mode->htotal - mode->hsync_start;
130 timing.blanking_level = BLANKING_LEVEL;
131
132 if (config->awg_fwgen_fct(&fw_gen_params, &timing)) {
133 DRM_ERROR("AWG firmware not properly generated\n");
134 return -EINVAL;
135 }
136
137 *ram_size = fw_gen_params.instruction_offset;
138
139 return 0;
140 }
141
142 /* Configure AWG, writing instructions
143 *
144 * @dvo: pointer to DVO structure
145 * @awg_ram_code: pointer to AWG instructions table
146 * @nb: nb of AWG instructions
147 */
dvo_awg_configure(struct sti_dvo * dvo,u32 * awg_ram_code,int nb)148 static void dvo_awg_configure(struct sti_dvo *dvo, u32 *awg_ram_code, int nb)
149 {
150 int i;
151
152 DRM_DEBUG_DRIVER("\n");
153
154 for (i = 0; i < nb; i++)
155 writel(awg_ram_code[i],
156 dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4);
157 for (i = nb; i < AWG_MAX_INST; i++)
158 writel(0, dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4);
159
160 writel(DVO_AWG_CTRL_EN, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
161 }
162
163 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
164 readl(dvo->regs + reg))
165
dvo_dbg_awg_microcode(struct seq_file * s,void __iomem * reg)166 static void dvo_dbg_awg_microcode(struct seq_file *s, void __iomem *reg)
167 {
168 unsigned int i;
169
170 seq_puts(s, "\n\n");
171 seq_puts(s, " DVO AWG microcode:");
172 for (i = 0; i < AWG_MAX_INST; i++) {
173 if (i % 8 == 0)
174 seq_printf(s, "\n %04X:", i);
175 seq_printf(s, " %04X", readl(reg + i * 4));
176 }
177 }
178
dvo_dbg_show(struct seq_file * s,void * data)179 static int dvo_dbg_show(struct seq_file *s, void *data)
180 {
181 struct drm_info_node *node = s->private;
182 struct sti_dvo *dvo = (struct sti_dvo *)node->info_ent->data;
183
184 seq_printf(s, "DVO: (vaddr = 0x%p)", dvo->regs);
185 DBGFS_DUMP(DVO_AWG_DIGSYNC_CTRL);
186 DBGFS_DUMP(DVO_DOF_CFG);
187 DBGFS_DUMP(DVO_LUT_PROG_LOW);
188 DBGFS_DUMP(DVO_LUT_PROG_MID);
189 DBGFS_DUMP(DVO_LUT_PROG_HIGH);
190 dvo_dbg_awg_microcode(s, dvo->regs + DVO_DIGSYNC_INSTR_I);
191 seq_putc(s, '\n');
192 return 0;
193 }
194
195 static struct drm_info_list dvo_debugfs_files[] = {
196 { "dvo", dvo_dbg_show, 0, NULL },
197 };
198
dvo_debugfs_init(struct sti_dvo * dvo,struct drm_minor * minor)199 static void dvo_debugfs_init(struct sti_dvo *dvo, struct drm_minor *minor)
200 {
201 unsigned int i;
202
203 for (i = 0; i < ARRAY_SIZE(dvo_debugfs_files); i++)
204 dvo_debugfs_files[i].data = dvo;
205
206 drm_debugfs_create_files(dvo_debugfs_files,
207 ARRAY_SIZE(dvo_debugfs_files),
208 minor->debugfs_root, minor);
209 }
210
sti_dvo_disable(struct drm_bridge * bridge)211 static void sti_dvo_disable(struct drm_bridge *bridge)
212 {
213 struct sti_dvo *dvo = bridge->driver_private;
214
215 if (!dvo->enabled)
216 return;
217
218 DRM_DEBUG_DRIVER("\n");
219
220 if (dvo->config->awg_fwgen_fct)
221 writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
222
223 writel(0x00000000, dvo->regs + DVO_DOF_CFG);
224
225 drm_panel_disable(dvo->panel);
226
227 /* Disable/unprepare dvo clock */
228 clk_disable_unprepare(dvo->clk_pix);
229 clk_disable_unprepare(dvo->clk);
230
231 dvo->enabled = false;
232 }
233
sti_dvo_pre_enable(struct drm_bridge * bridge)234 static void sti_dvo_pre_enable(struct drm_bridge *bridge)
235 {
236 struct sti_dvo *dvo = bridge->driver_private;
237 struct dvo_config *config = dvo->config;
238 u32 val;
239
240 DRM_DEBUG_DRIVER("\n");
241
242 if (dvo->enabled)
243 return;
244
245 /* Make sure DVO is disabled */
246 writel(0x00000000, dvo->regs + DVO_DOF_CFG);
247 writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
248
249 if (config->awg_fwgen_fct) {
250 u8 nb_instr;
251 u32 awg_ram_code[AWG_MAX_INST];
252 /* Configure AWG */
253 if (!dvo_awg_generate_code(dvo, &nb_instr, awg_ram_code))
254 dvo_awg_configure(dvo, awg_ram_code, nb_instr);
255 else
256 return;
257 }
258
259 /* Prepare/enable clocks */
260 if (clk_prepare_enable(dvo->clk_pix))
261 DRM_ERROR("Failed to prepare/enable dvo_pix clk\n");
262 if (clk_prepare_enable(dvo->clk))
263 DRM_ERROR("Failed to prepare/enable dvo clk\n");
264
265 drm_panel_enable(dvo->panel);
266
267 /* Set LUT */
268 writel(config->lowbyte, dvo->regs + DVO_LUT_PROG_LOW);
269 writel(config->midbyte, dvo->regs + DVO_LUT_PROG_MID);
270 writel(config->highbyte, dvo->regs + DVO_LUT_PROG_HIGH);
271
272 /* Digital output formatter config */
273 val = (config->flags | DVO_DOF_EN);
274 writel(val, dvo->regs + DVO_DOF_CFG);
275
276 dvo->enabled = true;
277 }
278
sti_dvo_set_mode(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)279 static void sti_dvo_set_mode(struct drm_bridge *bridge,
280 const struct drm_display_mode *mode,
281 const struct drm_display_mode *adjusted_mode)
282 {
283 struct sti_dvo *dvo = bridge->driver_private;
284 struct sti_mixer *mixer = to_sti_mixer(dvo->encoder->crtc);
285 int rate = mode->clock * 1000;
286 struct clk *clkp;
287 int ret;
288
289 DRM_DEBUG_DRIVER("\n");
290
291 memcpy(&dvo->mode, mode, sizeof(struct drm_display_mode));
292
293 /* According to the path used (main or aux), the dvo clocks should
294 * have a different parent clock. */
295 if (mixer->id == STI_MIXER_MAIN)
296 clkp = dvo->clk_main_parent;
297 else
298 clkp = dvo->clk_aux_parent;
299
300 if (clkp) {
301 clk_set_parent(dvo->clk_pix, clkp);
302 clk_set_parent(dvo->clk, clkp);
303 }
304
305 /* DVO clocks = compositor clock */
306 ret = clk_set_rate(dvo->clk_pix, rate);
307 if (ret < 0) {
308 DRM_ERROR("Cannot set rate (%dHz) for dvo_pix clk\n", rate);
309 return;
310 }
311
312 ret = clk_set_rate(dvo->clk, rate);
313 if (ret < 0) {
314 DRM_ERROR("Cannot set rate (%dHz) for dvo clk\n", rate);
315 return;
316 }
317
318 /* For now, we only support 24bit data enable (DE) synchro format */
319 dvo->config = &rgb_24bit_de_cfg;
320 }
321
sti_dvo_bridge_nope(struct drm_bridge * bridge)322 static void sti_dvo_bridge_nope(struct drm_bridge *bridge)
323 {
324 /* do nothing */
325 }
326
327 static const struct drm_bridge_funcs sti_dvo_bridge_funcs = {
328 .pre_enable = sti_dvo_pre_enable,
329 .enable = sti_dvo_bridge_nope,
330 .disable = sti_dvo_disable,
331 .post_disable = sti_dvo_bridge_nope,
332 .mode_set = sti_dvo_set_mode,
333 };
334
sti_dvo_connector_get_modes(struct drm_connector * connector)335 static int sti_dvo_connector_get_modes(struct drm_connector *connector)
336 {
337 struct sti_dvo_connector *dvo_connector
338 = to_sti_dvo_connector(connector);
339 struct sti_dvo *dvo = dvo_connector->dvo;
340
341 if (dvo->panel)
342 return drm_panel_get_modes(dvo->panel, connector);
343
344 return 0;
345 }
346
347 #define CLK_TOLERANCE_HZ 50
348
sti_dvo_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)349 static int sti_dvo_connector_mode_valid(struct drm_connector *connector,
350 struct drm_display_mode *mode)
351 {
352 int target = mode->clock * 1000;
353 int target_min = target - CLK_TOLERANCE_HZ;
354 int target_max = target + CLK_TOLERANCE_HZ;
355 int result;
356 struct sti_dvo_connector *dvo_connector
357 = to_sti_dvo_connector(connector);
358 struct sti_dvo *dvo = dvo_connector->dvo;
359
360 result = clk_round_rate(dvo->clk_pix, target);
361
362 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
363 target, result);
364
365 if ((result < target_min) || (result > target_max)) {
366 DRM_DEBUG_DRIVER("dvo pixclk=%d not supported\n", target);
367 return MODE_BAD;
368 }
369
370 return MODE_OK;
371 }
372
373 static const
374 struct drm_connector_helper_funcs sti_dvo_connector_helper_funcs = {
375 .get_modes = sti_dvo_connector_get_modes,
376 .mode_valid = sti_dvo_connector_mode_valid,
377 };
378
379 static enum drm_connector_status
sti_dvo_connector_detect(struct drm_connector * connector,bool force)380 sti_dvo_connector_detect(struct drm_connector *connector, bool force)
381 {
382 struct sti_dvo_connector *dvo_connector
383 = to_sti_dvo_connector(connector);
384 struct sti_dvo *dvo = dvo_connector->dvo;
385
386 DRM_DEBUG_DRIVER("\n");
387
388 if (!dvo->panel) {
389 dvo->panel = of_drm_find_panel(dvo->panel_node);
390 if (IS_ERR(dvo->panel))
391 dvo->panel = NULL;
392 }
393
394 if (dvo->panel)
395 return connector_status_connected;
396
397 return connector_status_disconnected;
398 }
399
sti_dvo_late_register(struct drm_connector * connector)400 static int sti_dvo_late_register(struct drm_connector *connector)
401 {
402 struct sti_dvo_connector *dvo_connector
403 = to_sti_dvo_connector(connector);
404 struct sti_dvo *dvo = dvo_connector->dvo;
405
406 dvo_debugfs_init(dvo, dvo->drm_dev->primary);
407
408 return 0;
409 }
410
411 static const struct drm_connector_funcs sti_dvo_connector_funcs = {
412 .fill_modes = drm_helper_probe_single_connector_modes,
413 .detect = sti_dvo_connector_detect,
414 .destroy = drm_connector_cleanup,
415 .reset = drm_atomic_helper_connector_reset,
416 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
417 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
418 .late_register = sti_dvo_late_register,
419 };
420
sti_dvo_find_encoder(struct drm_device * dev)421 static struct drm_encoder *sti_dvo_find_encoder(struct drm_device *dev)
422 {
423 struct drm_encoder *encoder;
424
425 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
426 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
427 return encoder;
428 }
429
430 return NULL;
431 }
432
sti_dvo_bind(struct device * dev,struct device * master,void * data)433 static int sti_dvo_bind(struct device *dev, struct device *master, void *data)
434 {
435 struct sti_dvo *dvo = dev_get_drvdata(dev);
436 struct drm_device *drm_dev = data;
437 struct drm_encoder *encoder;
438 struct sti_dvo_connector *connector;
439 struct drm_connector *drm_connector;
440 struct drm_bridge *bridge;
441 int err;
442
443 /* Set the drm device handle */
444 dvo->drm_dev = drm_dev;
445
446 encoder = sti_dvo_find_encoder(drm_dev);
447 if (!encoder)
448 return -ENOMEM;
449
450 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
451 if (!connector)
452 return -ENOMEM;
453
454 connector->dvo = dvo;
455
456 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
457 if (!bridge)
458 return -ENOMEM;
459
460 bridge->driver_private = dvo;
461 bridge->funcs = &sti_dvo_bridge_funcs;
462 bridge->of_node = dvo->dev.of_node;
463 drm_bridge_add(bridge);
464
465 err = drm_bridge_attach(encoder, bridge, NULL, 0);
466 if (err) {
467 DRM_ERROR("Failed to attach bridge\n");
468 return err;
469 }
470
471 dvo->bridge = bridge;
472 connector->encoder = encoder;
473 dvo->encoder = encoder;
474
475 drm_connector = (struct drm_connector *)connector;
476
477 drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
478
479 drm_connector_init(drm_dev, drm_connector,
480 &sti_dvo_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
481 drm_connector_helper_add(drm_connector,
482 &sti_dvo_connector_helper_funcs);
483
484 err = drm_connector_attach_encoder(drm_connector, encoder);
485 if (err) {
486 DRM_ERROR("Failed to attach a connector to a encoder\n");
487 goto err_sysfs;
488 }
489
490 return 0;
491
492 err_sysfs:
493 drm_bridge_remove(bridge);
494 return -EINVAL;
495 }
496
sti_dvo_unbind(struct device * dev,struct device * master,void * data)497 static void sti_dvo_unbind(struct device *dev,
498 struct device *master, void *data)
499 {
500 struct sti_dvo *dvo = dev_get_drvdata(dev);
501
502 drm_bridge_remove(dvo->bridge);
503 }
504
505 static const struct component_ops sti_dvo_ops = {
506 .bind = sti_dvo_bind,
507 .unbind = sti_dvo_unbind,
508 };
509
sti_dvo_probe(struct platform_device * pdev)510 static int sti_dvo_probe(struct platform_device *pdev)
511 {
512 struct device *dev = &pdev->dev;
513 struct sti_dvo *dvo;
514 struct resource *res;
515 struct device_node *np = dev->of_node;
516
517 DRM_INFO("%s\n", __func__);
518
519 dvo = devm_kzalloc(dev, sizeof(*dvo), GFP_KERNEL);
520 if (!dvo) {
521 DRM_ERROR("Failed to allocate memory for DVO\n");
522 return -ENOMEM;
523 }
524
525 dvo->dev = pdev->dev;
526
527 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvo-reg");
528 if (!res) {
529 DRM_ERROR("Invalid dvo resource\n");
530 return -ENOMEM;
531 }
532 dvo->regs = devm_ioremap(dev, res->start,
533 resource_size(res));
534 if (!dvo->regs)
535 return -ENOMEM;
536
537 dvo->clk_pix = devm_clk_get(dev, "dvo_pix");
538 if (IS_ERR(dvo->clk_pix)) {
539 DRM_ERROR("Cannot get dvo_pix clock\n");
540 return PTR_ERR(dvo->clk_pix);
541 }
542
543 dvo->clk = devm_clk_get(dev, "dvo");
544 if (IS_ERR(dvo->clk)) {
545 DRM_ERROR("Cannot get dvo clock\n");
546 return PTR_ERR(dvo->clk);
547 }
548
549 dvo->clk_main_parent = devm_clk_get(dev, "main_parent");
550 if (IS_ERR(dvo->clk_main_parent)) {
551 DRM_DEBUG_DRIVER("Cannot get main_parent clock\n");
552 dvo->clk_main_parent = NULL;
553 }
554
555 dvo->clk_aux_parent = devm_clk_get(dev, "aux_parent");
556 if (IS_ERR(dvo->clk_aux_parent)) {
557 DRM_DEBUG_DRIVER("Cannot get aux_parent clock\n");
558 dvo->clk_aux_parent = NULL;
559 }
560
561 dvo->panel_node = of_parse_phandle(np, "sti,panel", 0);
562 if (!dvo->panel_node)
563 DRM_ERROR("No panel associated to the dvo output\n");
564 of_node_put(dvo->panel_node);
565
566 platform_set_drvdata(pdev, dvo);
567
568 return component_add(&pdev->dev, &sti_dvo_ops);
569 }
570
sti_dvo_remove(struct platform_device * pdev)571 static int sti_dvo_remove(struct platform_device *pdev)
572 {
573 component_del(&pdev->dev, &sti_dvo_ops);
574 return 0;
575 }
576
577 static const struct of_device_id dvo_of_match[] = {
578 { .compatible = "st,stih407-dvo", },
579 { /* end node */ }
580 };
581 MODULE_DEVICE_TABLE(of, dvo_of_match);
582
583 struct platform_driver sti_dvo_driver = {
584 .driver = {
585 .name = "sti-dvo",
586 .owner = THIS_MODULE,
587 .of_match_table = dvo_of_match,
588 },
589 .probe = sti_dvo_probe,
590 .remove = sti_dvo_remove,
591 };
592
593 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
594 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
595 MODULE_LICENSE("GPL");
596
