1 /* savage_drv.h -- Private header for the savage driver */ 2 /* 3 * Copyright 2004 Felix Kuehling 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sub license, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef __SAVAGE_DRV_H__ 27 #define __SAVAGE_DRV_H__ 28 29 #include <linux/io.h> 30 31 #include <drm/drm_ioctl.h> 32 #include <drm/drm_legacy.h> 33 #include <drm/savage_drm.h> 34 35 #define DRIVER_AUTHOR "Felix Kuehling" 36 37 #define DRIVER_NAME "savage" 38 #define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]" 39 #define DRIVER_DATE "20050313" 40 41 #define DRIVER_MAJOR 2 42 #define DRIVER_MINOR 4 43 #define DRIVER_PATCHLEVEL 1 44 /* Interface history: 45 * 46 * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy 47 * 2.0 The first real DRM 48 * 2.1 Scissors registers managed by the DRM, 3D operations clipped by 49 * cliprects of the cmdbuf ioctl 50 * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX 51 * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits 52 * wide and thus very long lived (unlikely to ever wrap). The size 53 * in the struct was 32 bits before, but only 16 bits were used 54 * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is 55 * actually used 56 */ 57 58 typedef struct drm_savage_age { 59 uint16_t event; 60 unsigned int wrap; 61 } drm_savage_age_t; 62 63 typedef struct drm_savage_buf_priv { 64 struct drm_savage_buf_priv *next; 65 struct drm_savage_buf_priv *prev; 66 drm_savage_age_t age; 67 struct drm_buf *buf; 68 } drm_savage_buf_priv_t; 69 70 typedef struct drm_savage_dma_page { 71 drm_savage_age_t age; 72 unsigned int used, flushed; 73 } drm_savage_dma_page_t; 74 #define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ 75 /* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command 76 * size of 16kbytes or 4k entries. Minimum requirement would be 77 * 10kbytes for 255 40-byte vertices in one drawing command. */ 78 #define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4) 79 80 /* interesting bits of hardware state that are saved in dev_priv */ 81 typedef union { 82 struct drm_savage_common_state { 83 uint32_t vbaddr; 84 } common; 85 struct { 86 unsigned char pad[sizeof(struct drm_savage_common_state)]; 87 uint32_t texctrl, texaddr; 88 uint32_t scstart, new_scstart; 89 uint32_t scend, new_scend; 90 } s3d; 91 struct { 92 unsigned char pad[sizeof(struct drm_savage_common_state)]; 93 uint32_t texdescr, texaddr0, texaddr1; 94 uint32_t drawctrl0, new_drawctrl0; 95 uint32_t drawctrl1, new_drawctrl1; 96 } s4; 97 } drm_savage_state_t; 98 99 /* these chip tags should match the ones in the 2D driver in savage_regs.h. */ 100 enum savage_family { 101 S3_UNKNOWN = 0, 102 S3_SAVAGE3D, 103 S3_SAVAGE_MX, 104 S3_SAVAGE4, 105 S3_PROSAVAGE, 106 S3_TWISTER, 107 S3_PROSAVAGEDDR, 108 S3_SUPERSAVAGE, 109 S3_SAVAGE2000, 110 S3_LAST 111 }; 112 113 extern const struct drm_ioctl_desc savage_ioctls[]; 114 extern int savage_max_ioctl; 115 116 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) 117 118 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ 119 || (chip==S3_PROSAVAGE) \ 120 || (chip==S3_TWISTER) \ 121 || (chip==S3_PROSAVAGEDDR)) 122 123 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) 124 125 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) 126 127 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \ 128 ||(chip==S3_PROSAVAGEDDR)) 129 130 /* flags */ 131 #define SAVAGE_IS_AGP 1 132 133 typedef struct drm_savage_private { 134 drm_savage_sarea_t *sarea_priv; 135 136 drm_savage_buf_priv_t head, tail; 137 138 /* who am I? */ 139 enum savage_family chipset; 140 141 unsigned int cob_size; 142 unsigned int bci_threshold_lo, bci_threshold_hi; 143 unsigned int dma_type; 144 145 /* frame buffer layout */ 146 unsigned int fb_bpp; 147 unsigned int front_offset, front_pitch; 148 unsigned int back_offset, back_pitch; 149 unsigned int depth_bpp; 150 unsigned int depth_offset, depth_pitch; 151 152 /* bitmap descriptors for swap and clear */ 153 unsigned int front_bd, back_bd, depth_bd; 154 155 /* local textures */ 156 unsigned int texture_offset; 157 unsigned int texture_size; 158 159 /* memory regions in physical memory */ 160 drm_local_map_t *sarea; 161 drm_local_map_t *mmio; 162 drm_local_map_t *fb; 163 drm_local_map_t *aperture; 164 drm_local_map_t *status; 165 drm_local_map_t *agp_textures; 166 drm_local_map_t *cmd_dma; 167 drm_local_map_t fake_dma; 168 169 int mtrr_handles[3]; 170 171 /* BCI and status-related stuff */ 172 volatile uint32_t *status_ptr, *bci_ptr; 173 uint32_t status_used_mask; 174 uint16_t event_counter; 175 unsigned int event_wrap; 176 177 /* Savage4 command DMA */ 178 drm_savage_dma_page_t *dma_pages; 179 unsigned int nr_dma_pages, first_dma_page, current_dma_page; 180 drm_savage_age_t last_dma_age; 181 182 /* saved hw state for global/local check on S3D */ 183 uint32_t hw_draw_ctrl, hw_zbuf_ctrl; 184 /* and for scissors (global, so don't emit if not changed) */ 185 uint32_t hw_scissors_start, hw_scissors_end; 186 187 drm_savage_state_t state; 188 189 /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */ 190 unsigned int waiting; 191 192 /* config/hardware-dependent function pointers */ 193 int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n); 194 int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e); 195 /* Err, there is a macro wait_event in include/linux/wait.h. 196 * Avoid unwanted macro expansion. */ 197 void (*emit_clip_rect) (struct drm_savage_private * dev_priv, 198 const struct drm_clip_rect * pbox); 199 void (*dma_flush) (struct drm_savage_private * dev_priv); 200 } drm_savage_private_t; 201 202 /* ioctls */ 203 extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv); 204 extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 205 206 /* BCI functions */ 207 extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, 208 unsigned int flags); 209 extern void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf); 210 extern void savage_dma_reset(drm_savage_private_t * dev_priv); 211 extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page); 212 extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, 213 unsigned int n); 214 extern int savage_driver_load(struct drm_device *dev, unsigned long chipset); 215 extern int savage_driver_firstopen(struct drm_device *dev); 216 extern void savage_driver_lastclose(struct drm_device *dev); 217 extern void savage_driver_unload(struct drm_device *dev); 218 extern void savage_reclaim_buffers(struct drm_device *dev, 219 struct drm_file *file_priv); 220 221 /* state functions */ 222 extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv, 223 const struct drm_clip_rect * pbox); 224 extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv, 225 const struct drm_clip_rect * pbox); 226 227 #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ 228 #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ 229 #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ 230 #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ 231 #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ 232 233 #define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region 234 * inside the MMIO region */ 235 #define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip 236 * BCI FIFO */ 237 238 /* 239 * MMIO registers 240 */ 241 #define SAVAGE_STATUS_WORD0 0x48C00 242 #define SAVAGE_STATUS_WORD1 0x48C04 243 #define SAVAGE_ALT_STATUS_WORD0 0x48C60 244 245 #define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff 246 #define SAVAGE_FIFO_USED_MASK_S4 0x001fffff 247 248 /* Copied from savage_bci.h in the 2D driver with some renaming. */ 249 250 /* Bitmap descriptors */ 251 #define SAVAGE_BD_STRIDE_SHIFT 0 252 #define SAVAGE_BD_BPP_SHIFT 16 253 #define SAVAGE_BD_TILE_SHIFT 24 254 #define SAVAGE_BD_BW_DISABLE (1<<28) 255 /* common: */ 256 #define SAVAGE_BD_TILE_LINEAR 0 257 /* savage4, MX, IX, 3D */ 258 #define SAVAGE_BD_TILE_16BPP 2 259 #define SAVAGE_BD_TILE_32BPP 3 260 /* twister, prosavage, DDR, supersavage, 2000 */ 261 #define SAVAGE_BD_TILE_DEST 1 262 #define SAVAGE_BD_TILE_TEXTURE 2 263 /* GBD - BCI enable */ 264 /* savage4, MX, IX, 3D */ 265 #define SAVAGE_GBD_BCI_ENABLE 8 266 /* twister, prosavage, DDR, supersavage, 2000 */ 267 #define SAVAGE_GBD_BCI_ENABLE_TWISTER 0 268 269 #define SAVAGE_GBD_BIG_ENDIAN 4 270 #define SAVAGE_GBD_LITTLE_ENDIAN 0 271 #define SAVAGE_GBD_64 1 272 273 /* Global Bitmap Descriptor */ 274 #define SAVAGE_BCI_GLB_BD_LOW 0x8168 275 #define SAVAGE_BCI_GLB_BD_HIGH 0x816C 276 277 /* 278 * BCI registers 279 */ 280 /* Savage4/Twister/ProSavage 3D registers */ 281 #define SAVAGE_DRAWLOCALCTRL_S4 0x1e 282 #define SAVAGE_TEXPALADDR_S4 0x1f 283 #define SAVAGE_TEXCTRL0_S4 0x20 284 #define SAVAGE_TEXCTRL1_S4 0x21 285 #define SAVAGE_TEXADDR0_S4 0x22 286 #define SAVAGE_TEXADDR1_S4 0x23 287 #define SAVAGE_TEXBLEND0_S4 0x24 288 #define SAVAGE_TEXBLEND1_S4 0x25 289 #define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ 290 #define SAVAGE_TEXDESCR_S4 0x27 291 #define SAVAGE_FOGTABLE_S4 0x28 292 #define SAVAGE_FOGCTRL_S4 0x30 293 #define SAVAGE_STENCILCTRL_S4 0x31 294 #define SAVAGE_ZBUFCTRL_S4 0x32 295 #define SAVAGE_ZBUFOFF_S4 0x33 296 #define SAVAGE_DESTCTRL_S4 0x34 297 #define SAVAGE_DRAWCTRL0_S4 0x35 298 #define SAVAGE_DRAWCTRL1_S4 0x36 299 #define SAVAGE_ZWATERMARK_S4 0x37 300 #define SAVAGE_DESTTEXRWWATERMARK_S4 0x38 301 #define SAVAGE_TEXBLENDCOLOR_S4 0x39 302 /* Savage3D/MX/IX 3D registers */ 303 #define SAVAGE_TEXPALADDR_S3D 0x18 304 #define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ 305 #define SAVAGE_TEXADDR_S3D 0x1A 306 #define SAVAGE_TEXDESCR_S3D 0x1B 307 #define SAVAGE_TEXCTRL_S3D 0x1C 308 #define SAVAGE_FOGTABLE_S3D 0x20 309 #define SAVAGE_FOGCTRL_S3D 0x30 310 #define SAVAGE_DRAWCTRL_S3D 0x31 311 #define SAVAGE_ZBUFCTRL_S3D 0x32 312 #define SAVAGE_ZBUFOFF_S3D 0x33 313 #define SAVAGE_DESTCTRL_S3D 0x34 314 #define SAVAGE_SCSTART_S3D 0x35 315 #define SAVAGE_SCEND_S3D 0x36 316 #define SAVAGE_ZWATERMARK_S3D 0x37 317 #define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38 318 /* common stuff */ 319 #define SAVAGE_VERTBUFADDR 0x3e 320 #define SAVAGE_BITPLANEWTMASK 0xd7 321 #define SAVAGE_DMABUFADDR 0x51 322 323 /* texture enable bits (needed for tex addr checking) */ 324 #define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ 325 #define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ 326 #define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ 327 328 /* Global fields in Savage4/Twister/ProSavage 3D registers: 329 * 330 * All texture registers and DrawLocalCtrl are local. All other 331 * registers are global. */ 332 333 /* Global fields in Savage3D/MX/IX 3D registers: 334 * 335 * All texture registers are local. DrawCtrl and ZBufCtrl are 336 * partially local. All other registers are global. 337 * 338 * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal 339 * ZBufCtrl global fields: zCmpFunc, zBufEn 340 */ 341 #define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c 342 #define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027 343 344 /* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d) 345 */ 346 #define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff 347 #define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff 348 349 /* 350 * BCI commands 351 */ 352 #define BCI_CMD_NOP 0x40000000 353 #define BCI_CMD_RECT 0x48000000 354 #define BCI_CMD_RECT_XP 0x01000000 355 #define BCI_CMD_RECT_YP 0x02000000 356 #define BCI_CMD_SCANLINE 0x50000000 357 #define BCI_CMD_LINE 0x5C000000 358 #define BCI_CMD_LINE_LAST_PIXEL 0x58000000 359 #define BCI_CMD_BYTE_TEXT 0x63000000 360 #define BCI_CMD_NT_BYTE_TEXT 0x67000000 361 #define BCI_CMD_BIT_TEXT 0x6C000000 362 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) 363 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) 364 #define BCI_CMD_SEND_COLOR 0x00008000 365 366 #define BCI_CMD_CLIP_NONE 0x00000000 367 #define BCI_CMD_CLIP_CURRENT 0x00002000 368 #define BCI_CMD_CLIP_LR 0x00004000 369 #define BCI_CMD_CLIP_NEW 0x00006000 370 371 #define BCI_CMD_DEST_GBD 0x00000000 372 #define BCI_CMD_DEST_PBD 0x00000800 373 #define BCI_CMD_DEST_PBD_NEW 0x00000C00 374 #define BCI_CMD_DEST_SBD 0x00001000 375 #define BCI_CMD_DEST_SBD_NEW 0x00001400 376 377 #define BCI_CMD_SRC_TRANSPARENT 0x00000200 378 #define BCI_CMD_SRC_SOLID 0x00000000 379 #define BCI_CMD_SRC_GBD 0x00000020 380 #define BCI_CMD_SRC_COLOR 0x00000040 381 #define BCI_CMD_SRC_MONO 0x00000060 382 #define BCI_CMD_SRC_PBD_COLOR 0x00000080 383 #define BCI_CMD_SRC_PBD_MONO 0x000000A0 384 #define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0 385 #define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0 386 #define BCI_CMD_SRC_SBD_COLOR 0x00000100 387 #define BCI_CMD_SRC_SBD_MONO 0x00000120 388 #define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 389 #define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160 390 391 #define BCI_CMD_PAT_TRANSPARENT 0x00000010 392 #define BCI_CMD_PAT_NONE 0x00000000 393 #define BCI_CMD_PAT_COLOR 0x00000002 394 #define BCI_CMD_PAT_MONO 0x00000003 395 #define BCI_CMD_PAT_PBD_COLOR 0x00000004 396 #define BCI_CMD_PAT_PBD_MONO 0x00000005 397 #define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006 398 #define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007 399 #define BCI_CMD_PAT_SBD_COLOR 0x00000008 400 #define BCI_CMD_PAT_SBD_MONO 0x00000009 401 #define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A 402 #define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B 403 404 #define BCI_BD_BW_DISABLE 0x10000000 405 #define BCI_BD_TILE_MASK 0x03000000 406 #define BCI_BD_TILE_NONE 0x00000000 407 #define BCI_BD_TILE_16 0x02000000 408 #define BCI_BD_TILE_32 0x03000000 409 #define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF) 410 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) 411 #define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF) 412 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) 413 414 #define BCI_CMD_SET_REGISTER 0x96000000 415 416 #define BCI_CMD_WAIT 0xC0000000 417 #define BCI_CMD_WAIT_3D 0x00010000 418 #define BCI_CMD_WAIT_2D 0x00020000 419 420 #define BCI_CMD_UPDATE_EVENT_TAG 0x98000000 421 422 #define BCI_CMD_DRAW_PRIM 0x80000000 423 #define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000 424 #define BCI_CMD_DRAW_CONT 0x01000000 425 #define BCI_CMD_DRAW_TRILIST 0x00000000 426 #define BCI_CMD_DRAW_TRISTRIP 0x02000000 427 #define BCI_CMD_DRAW_TRIFAN 0x04000000 428 #define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff 429 #define BCI_CMD_DRAW_NO_Z 0x00000001 430 #define BCI_CMD_DRAW_NO_W 0x00000002 431 #define BCI_CMD_DRAW_NO_CD 0x00000004 432 #define BCI_CMD_DRAW_NO_CS 0x00000008 433 #define BCI_CMD_DRAW_NO_U0 0x00000010 434 #define BCI_CMD_DRAW_NO_V0 0x00000020 435 #define BCI_CMD_DRAW_NO_UV0 0x00000030 436 #define BCI_CMD_DRAW_NO_U1 0x00000040 437 #define BCI_CMD_DRAW_NO_V1 0x00000080 438 #define BCI_CMD_DRAW_NO_UV1 0x000000c0 439 440 #define BCI_CMD_DMA 0xa8000000 441 442 #define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF) 443 #define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF) 444 #define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF) 445 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) 446 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) 447 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) 448 449 #define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF)) 450 #define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF)) 451 #define BCI_LINE_MISC(maj, ym, xp, yp, err) \ 452 (((maj) & 0x1FFF) | \ 453 ((ym) ? 1<<13 : 0) | \ 454 ((xp) ? 1<<14 : 0) | \ 455 ((yp) ? 1<<15 : 0) | \ 456 ((err) << 16)) 457 458 /* 459 * common commands 460 */ 461 #define BCI_SET_REGISTERS( first, n ) \ 462 BCI_WRITE(BCI_CMD_SET_REGISTER | \ 463 ((uint32_t)(n) & 0xff) << 16 | \ 464 ((uint32_t)(first) & 0xffff)) 465 #define DMA_SET_REGISTERS( first, n ) \ 466 DMA_WRITE(BCI_CMD_SET_REGISTER | \ 467 ((uint32_t)(n) & 0xff) << 16 | \ 468 ((uint32_t)(first) & 0xffff)) 469 470 #define BCI_DRAW_PRIMITIVE(n, type, skip) \ 471 BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 472 ((n) << 16)) 473 #define DMA_DRAW_PRIMITIVE(n, type, skip) \ 474 DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 475 ((n) << 16)) 476 477 #define BCI_DRAW_INDICES_S3D(n, type, i0) \ 478 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 479 ((n) << 16) | (i0)) 480 481 #define BCI_DRAW_INDICES_S4(n, type, skip) \ 482 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 483 (skip) | ((n) << 16)) 484 485 #define BCI_DMA(n) \ 486 BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1)) 487 488 /* 489 * access to MMIO 490 */ 491 #define SAVAGE_READ(reg) \ 492 readl(((void __iomem *)dev_priv->mmio->handle) + (reg)) 493 #define SAVAGE_WRITE(reg) \ 494 writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg)) 495 496 /* 497 * access to the burst command interface (BCI) 498 */ 499 #define SAVAGE_BCI_DEBUG 1 500 501 #define BCI_LOCALS volatile uint32_t *bci_ptr; 502 503 #define BEGIN_BCI( n ) do { \ 504 dev_priv->wait_fifo(dev_priv, (n)); \ 505 bci_ptr = dev_priv->bci_ptr; \ 506 } while(0) 507 508 #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val) 509 510 /* 511 * command DMA support 512 */ 513 #define SAVAGE_DMA_DEBUG 1 514 515 #define DMA_LOCALS uint32_t *dma_ptr; 516 517 #define BEGIN_DMA( n ) do { \ 518 unsigned int cur = dev_priv->current_dma_page; \ 519 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \ 520 dev_priv->dma_pages[cur].used; \ 521 if ((n) > rest) { \ 522 dma_ptr = savage_dma_alloc(dev_priv, (n)); \ 523 } else { /* fast path for small allocations */ \ 524 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \ 525 cur * SAVAGE_DMA_PAGE_SIZE + \ 526 dev_priv->dma_pages[cur].used; \ 527 if (dev_priv->dma_pages[cur].used == 0) \ 528 savage_dma_wait(dev_priv, cur); \ 529 dev_priv->dma_pages[cur].used += (n); \ 530 } \ 531 } while(0) 532 533 #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) 534 535 #define DMA_COPY(src, n) do { \ 536 memcpy(dma_ptr, (src), (n)*4); \ 537 dma_ptr += n; \ 538 } while(0) 539 540 #if SAVAGE_DMA_DEBUG 541 #define DMA_COMMIT() do { \ 542 unsigned int cur = dev_priv->current_dma_page; \ 543 uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \ 544 cur * SAVAGE_DMA_PAGE_SIZE + \ 545 dev_priv->dma_pages[cur].used; \ 546 if (dma_ptr != expected) { \ 547 DRM_ERROR("DMA allocation and use don't match: " \ 548 "%p != %p\n", expected, dma_ptr); \ 549 savage_dma_reset(dev_priv); \ 550 } \ 551 } while(0) 552 #else 553 #define DMA_COMMIT() do {/* nothing */} while(0) 554 #endif 555 556 #define DMA_FLUSH() dev_priv->dma_flush(dev_priv) 557 558 /* Buffer aging via event tag 559 */ 560 561 #define UPDATE_EVENT_COUNTER( ) do { \ 562 if (dev_priv->status_ptr) { \ 563 uint16_t count; \ 564 /* coordinate with Xserver */ \ 565 count = dev_priv->status_ptr[1023]; \ 566 if (count < dev_priv->event_counter) \ 567 dev_priv->event_wrap++; \ 568 dev_priv->event_counter = count; \ 569 } \ 570 } while(0) 571 572 #define SET_AGE( age, e, w ) do { \ 573 (age)->event = e; \ 574 (age)->wrap = w; \ 575 } while(0) 576 577 #define TEST_AGE( age, e, w ) \ 578 ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) ) 579 580 #endif /* __SAVAGE_DRV_H__ */ 581
